[libsigrok.git] / hardware / link-mso19 / protocol.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "protocol.h"
#include <arpa/inet.h>

extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
static struct sr_dev_driver *di = &link_mso19_driver_info;

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
    uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	if (!(buf = g_try_malloc(s))) {
		sr_err("Failed to malloc message buffer.");
		ret = SR_ERR_MALLOC;
		goto ret;
	}

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}


SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t threshold_value = mso_calc_raw_from_mv(devc);


  threshold_value = 0x153C;
  uint8_t trigger_config = 0; 

  if (devc->trigger_slope)
    trigger_config |= 0x04; //Trigger on falling edge

	switch (devc->trigger_outsrc) {
	case 1:
		trigger_config |= 0x00; //Trigger pulse output
		break;
	case 2:
		trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
		break;
	case 3:
		trigger_config |= 0x18; //White noise
		break;
	}

	switch (devc->trigger_chan) {
    case 0:
      trigger_config |= 0x00; //DSO level trigger //b00000000
      break;
    case 1:
      trigger_config |= 0x20; //DSO level trigger & width < trigger_width
      break;
    case 2:
      trigger_config |= 0x40; //DSO level trigger & width >= trigger_width 
      break;
    case 3:
      trigger_config |= 0x60; //LA combination trigger
      break;
  }

  //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
  //otherwise the trigger is not enabled
  if (devc->use_trigger)
    trigger_config |= 0x80;

	uint16_t ops[18];
	ops[0] = mso_trans(3, threshold_value & 0xff);
  //The trigger_config also holds the 2 MSB bits from the threshold value
	ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03);
	ops[2] = mso_trans(5, devc->la_trigger);
	ops[3] = mso_trans(6, devc->la_trigger_mask);
	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);

	ops[6] = mso_trans(11,
			devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
{
	return (uint16_t) (0x200 -
			((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			 devc->vbit));
}


SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
    struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

  iProduct = iProduct;
  /* FIXME: This code is in the original app, but I think its
   * used only for the GUI */
  /*	if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
      devc->num_sample_rates = 0x16;
      else
      devc->num_sample_rates = 0x10; */
  

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
				&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 |= BIT_CTL1_RESETFSM;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 &= ~BIT_CTL1_LED;
	if (state)
		devc->ctlbase1 |= BIT_CTL1_LED;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting LED toggle.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_datafeed_packet packet;
	struct dev_context *devc;

	devc = sdi->priv;
	sr_source_remove(devc->serial->fd);

	/* Terminate session */
	packet.type = SR_DF_END;
	sr_session_send(sdi, &packet);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}

  if (ret != SR_OK)
		sr_err("Unsupported rate.");

	return ret;
}


SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (info == NULL || ret != SR_OK)
		return ret;


  uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
		ret = SR_ERR;
	*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{

	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi;
	GSList *l;
	int i;

	struct drv_context *drvc = di->priv;

	/* Find this device's devc struct by its fd. */
	struct dev_context *devc = NULL;
	for (l = drvc->instances; l; l = l->next) {
		sdi = l->data;
		devc = sdi->priv;
		if (devc->serial->fd == fd)
			break;
		devc = NULL;
	}
	if (!devc)
		/* Shouldn't happen. */
		return TRUE;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));

	if (s <= 0)
		return FALSE;
  
  /* Check if we triggered, then send a command that we are ready
   * to read the data */
  if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
    devc->trigger_state = in[0];
    if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
      mso_read_buffer(sdi);
      devc->buffer_n = 0;
    } else {
      mso_check_trigger(devc->serial, NULL);
    }
    return TRUE;
  }

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return TRUE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
			((devc->buffer[i * 3 + 1] & 0xf) << 6);
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
			((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(cb_data, &packet);

  devc->num_samples += 1024;

	// Dont bother fixing this yet, keep it "old style"
	/*
	packet.type = SR_DF_ANALOG;
	packet.length = 1024;
	packet.unitsize = sizeof(double);
	packet.payload = analog_out;
	sr_session_send(ctx->session_dev_id, &packet);
	*/

  if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { 
    sr_info("Requested number of samples reached."); 
    sdi->driver->dev_acquisition_stop(sdi, cb_data); 
  } 

  return TRUE;
}

SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_probe *probe;
	GSList *l;
	int probe_bit, stage, i;
	char *tc;

  
	devc = sdi->priv;

  devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
  devc->la_trigger = 0x00;  //The value of the LA byte that generates a trigger event (in that mode).
  devc->dso_trigger_voltage = 3;
  devc->dso_probe_attn = 1;
  devc->trigger_outsrc = 0;
  devc->trigger_chan = 3; //LA combination trigger
  devc->use_trigger = FALSE;

	for (l = sdi->probes; l; l = l->next) {
		probe = (struct sr_probe *)l->data;
		if (probe->enabled == FALSE)
			continue;

		int probe_bit = 1 << (probe->index);
		if (!(probe->trigger))
			continue;

    devc->use_trigger = TRUE;
		//Configure trigger mask and value.
		for (tc = probe->trigger; *tc; tc++) {
			devc->la_trigger_mask &= ~probe_bit;
      if (*tc == '1')
        devc->la_trigger |= probe_bit;
    }
  }

	return SR_OK;
}
Commit	Line	Data
df92e5cf	1	/*
	2	* This file is part of the sigrok project.
	3	*
f48cef78 UH	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	* Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
	6	* Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
df92e5cf	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "protocol.h"
4db2aaff	23	#include <arpa/inet.h>
df92e5cf	24
	25	extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
	26	static struct sr_dev_driver *di = &link_mso19_driver_info;
	27
4db2aaff	28	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
	29	uint16_t payload[], int n)
	30	{
	31	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	32	char p, buf;
	33
	34	ret = SR_ERR;
	35
	36	if (serial->fd < 0)
	37	goto ret;
	38
	39	if (!(buf = g_try_malloc(s))) {
	40	sr_err("Failed to malloc message buffer.");
	41	ret = SR_ERR_MALLOC;
	42	goto ret;
	43	}
	44
	45	p = buf;
	46	memcpy(p, mso_head, sizeof(mso_head));
	47	p += sizeof(mso_head);
	48
	49	for (i = 0; i < n; i++) {
	50	(uint16_t ) p = htons(payload[i]);
	51	p += 2;
	52	}
	53	memcpy(p, mso_foot, sizeof(mso_foot));
	54
	55	w = 0;
	56	while (w < s) {
	57	ret = serial_write(serial, buf + w, s - w);
	58	if (ret < 0) {
	59	ret = SR_ERR;
	60	goto free;
	61	}
	62	w += ret;
	63	}
	64	ret = SR_OK;
	65	free:
	66	g_free(buf);
	67	ret:
	68	return ret;
	69	}
	70
	71
4b719338	72	SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
	73	{
	74	struct dev_context *devc = sdi->priv;
087a9161	75	uint16_t threshold_value = mso_calc_raw_from_mv(devc);
4b719338	76
4b719338	77
087a9161	78	threshold_value = 0x153C;
	79	uint8_t trigger_config = 0;
	80
	81	if (devc->trigger_slope)
	82	trigger_config \|= 0x04; //Trigger on falling edge
4b719338	83
	84	switch (devc->trigger_outsrc) {
	85	case 1:
087a9161	86	trigger_config \|= 0x00; //Trigger pulse output
4b719338	87	break;
4b719338	88	case 2:
087a9161	89	trigger_config \|= 0x08; //PWM DAC from the pattern generator buffer
4b719338	90	break;
4b719338	91	case 3:
087a9161	92	trigger_config \|= 0x18; //White noise
4b719338	93	break;
4b719338	94	}
4b719338	95
087a9161	96	switch (devc->trigger_chan) {
	97	case 0:
	98	trigger_config \|= 0x00; //DSO level trigger //b00000000
	99	break;
	100	case 1:
	101	trigger_config \|= 0x20; //DSO level trigger & width < trigger_width
	102	break;
	103	case 2:
	104	trigger_config \|= 0x40; //DSO level trigger & width >= trigger_width
	105	break;
	106	case 3:
	107	trigger_config \|= 0x60; //LA combination trigger
	108	break;
	109	}
	110
	111	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	112	//otherwise the trigger is not enabled
	113	if (devc->use_trigger)
	114	trigger_config \|= 0x80;
	115
	116	uint16_t ops[18];
	117	ops[0] = mso_trans(3, threshold_value & 0xff);
	118	//The trigger_config also holds the 2 MSB bits from the threshold value
	119	ops[1] = mso_trans(4, trigger_config \| (threshold_value >> 8) & 0x03);
	120	ops[2] = mso_trans(5, devc->la_trigger);
	121	ops[3] = mso_trans(6, devc->la_trigger_mask);
	122	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	123	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
	124
	125	ops[6] = mso_trans(11,
4b719338	126	devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));
	127
	128	/* Select the SPI/I2C trigger config bank */
087a9161	129	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
4b719338	130	/* Configure the SPI/I2C protocol trigger */
087a9161	131	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	132	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	133	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	134	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	135	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	136	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	137	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	138	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	139	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
4b719338	140	/* Select the default config bank */
087a9161	141	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
4b719338	142
4db2aaff	143	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
4b719338	144	}
	145
	146	SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
	147	{
	148	struct dev_context *devc = sdi->priv;
	149
	150	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
	151	}
	152
	153	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
	154	{
	155	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	156	struct dev_context *devc = sdi->priv;
	157
	158	sr_dbg("Requesting buffer dump.");
	159	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	160	}
	161
	162	SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
	163	{
	164	struct dev_context *devc = sdi->priv;
	165	uint16_t ops[] = {
	166	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
	167	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
	168	mso_trans(REG_CTL1, devc->ctlbase1),
	169	};
	170
	171	sr_dbg("Requesting trigger arm.");
	172	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	173	}
	174
	175	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
	176	{
	177	struct dev_context *devc = sdi->priv;
	178	uint16_t ops[] = {
	179	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
	180	mso_trans(REG_CTL1, devc->ctlbase1),
	181	};
	182
	183	sr_dbg("Requesting forced capture.");
	184	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	185	}
	186
	187	SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
	188	{
	189	struct dev_context *devc = sdi->priv;
	190	uint16_t ops[] = {
	191	mso_trans(REG_DAC1, (val >> 8) & 0xff),
	192	mso_trans(REG_DAC2, val & 0xff),
	193	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
	194	};
	195
	196	sr_dbg("Setting dac word to 0x%x.", val);
	197	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	198	}
	199
	200	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
	201	{
	202	return (uint16_t) (0x200 -
	203	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
	204	devc->vbit));
	205	}
	206
	207
df92e5cf	208	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
	209	struct dev_context *devc)
	210	{
	211	unsigned int u1, u2, u3, u4, u5, u6;
	212
	213	iProduct = iProduct;
	214	/* FIXME: This code is in the original app, but I think its
	215	* used only for the GUI */
	216	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	217	devc->num_sample_rates = 0x16;
	218	else
	219	devc->num_sample_rates = 0x10; */
	220
	221
	222	/* parse iSerial */
	223	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
	224	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
	225	return SR_ERR;
	226	devc->hwmodel = u4;
	227	devc->hwrev = u5;
df92e5cf	228	devc->vbit = u1 / 10000;
	229	if (devc->vbit == 0)
	230	devc->vbit = 4.19195;
	231	devc->dac_offset = u2;
	232	if (devc->dac_offset == 0)
	233	devc->dac_offset = 0x1ff;
	234	devc->offset_range = u3;
	235	if (devc->offset_range == 0)
	236	devc->offset_range = 0x17d;
	237
	238	/*
	239	* FIXME: There is more code on the original software to handle
	240	* bigger iSerial strings, but as I can't test on my device
	241	* I will not implement it yet
	242	*/
	243
	244	return SR_OK;
	245	}
	246
4db2aaff	247	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
df92e5cf	248	{
4db2aaff	249	struct dev_context *devc = sdi->priv;
4db2aaff	250	uint16_t ops[2];
df92e5cf	251
4db2aaff	252	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
	253	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	254	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
df92e5cf	255
4db2aaff	256	sr_dbg("Requesting ADC reset.");
	257	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	258	}
df92e5cf	259
4db2aaff	260	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
	261	{
	262	struct dev_context *devc = sdi->priv;
	263	uint16_t ops[1];
df92e5cf	264
4db2aaff	265	devc->ctlbase1 \|= BIT_CTL1_RESETFSM;
4db2aaff	266	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	267
4db2aaff	268	sr_dbg("Requesting ADC reset.");
4db2aaff	269	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
df92e5cf	270	}
df92e5cf	271
4db2aaff	272	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
df92e5cf	273	{
df92e5cf	274	struct dev_context *devc = sdi->priv;
4db2aaff	275	uint16_t ops[1];
df92e5cf	276
4db2aaff	277	devc->ctlbase1 &= ~BIT_CTL1_LED;
	278	if (state)
	279	devc->ctlbase1 \|= BIT_CTL1_LED;
	280	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	281
4db2aaff	282	sr_dbg("Requesting LED toggle.");
df92e5cf	283	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	284	}
	285
	286	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
	287	{
	288	struct sr_datafeed_packet packet;
	289	struct dev_context *devc;
	290
	291	devc = sdi->priv;
	292	sr_source_remove(devc->serial->fd);
	293
	294	/* Terminate session */
	295	packet.type = SR_DF_END;
	296	sr_session_send(sdi, &packet);
	297	}
	298
	299	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
	300	{
	301	uint16_t ops[] = {
	302	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
	303	mso_trans(REG_CLKRATE2, val & 0xff),
	304	};
	305
	306	sr_dbg("Setting clkrate word to 0x%x.", val);
	307	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	308	}
	309
	310	SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
	311	{
	312	struct dev_context *devc = sdi->priv;
	313	unsigned int i;
	314	int ret = SR_ERR;
	315
	316	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
	317	if (rate_map[i].rate == rate) {
	318	devc->ctlbase2 = rate_map[i].slowmode;
4b719338	319	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
df92e5cf	320	if (ret == SR_OK)
	321	devc->cur_rate = rate;
	322	return ret;
	323	}
	324	}
4db2aaff	325
	326	if (ret != SR_OK)
	327	sr_err("Unsupported rate.");
	328
df92e5cf	329	return ret;
	330	}
	331
	332
	333
	334
	335
	336	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
	337	{
	338	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	339	int ret;
	340
	341	sr_dbg("Requesting trigger state.");
	342	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	343	if (info == NULL \|\| ret != SR_OK)
	344	return ret;
	345
	346
	347	uint8_t buf = 0;
	348	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
	349	ret = SR_ERR;
	350	*info = buf;
	351
	352	sr_dbg("Trigger state is: 0x%x.", *info);
	353	return ret;
	354	}
	355
	356	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	357	{
	358
	359	struct sr_datafeed_packet packet;
	360	struct sr_datafeed_logic logic;
	361	struct sr_dev_inst *sdi;
df92e5cf	362	GSList *l;
4db2aaff	363	int i;
df92e5cf	364
4db2aaff	365	struct drv_context *drvc = di->priv;
df92e5cf	366
df92e5cf	367	/* Find this device's devc struct by its fd. */
4db2aaff	368	struct dev_context *devc = NULL;
df92e5cf	369	for (l = drvc->instances; l; l = l->next) {
	370	sdi = l->data;
	371	devc = sdi->priv;
	372	if (devc->serial->fd == fd)
	373	break;
	374	devc = NULL;
	375	}
	376	if (!devc)
	377	/* Shouldn't happen. */
	378	return TRUE;
	379
	380	(void)revents;
	381
	382	uint8_t in[1024];
	383	size_t s = serial_read(devc->serial, in, sizeof(in));
5a24e89c	384
df92e5cf	385	if (s <= 0)
	386	return FALSE;
	387
5a24e89c	388	/* Check if we triggered, then send a command that we are ready
5a24e89c	389	* to read the data */
df92e5cf	390	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
	391	devc->trigger_state = in[0];
	392	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
	393	mso_read_buffer(sdi);
	394	devc->buffer_n = 0;
	395	} else {
	396	mso_check_trigger(devc->serial, NULL);
	397	}
5a24e89c	398	return TRUE;
df92e5cf	399	}
	400
	401	/* the hardware always dumps 1024 samples, 24bits each */
	402	if (devc->buffer_n < 3072) {
	403	memcpy(devc->buffer + devc->buffer_n, in, s);
	404	devc->buffer_n += s;
	405	}
	406	if (devc->buffer_n < 3072)
5a24e89c	407	return TRUE;
df92e5cf	408
	409	/* do the conversion */
	410	uint8_t logic_out[1024];
	411	double analog_out[1024];
	412	for (i = 0; i < 1024; i++) {
	413	/* FIXME: Need to do conversion to mV */
	414	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
	415	((devc->buffer[i * 3 + 1] & 0xf) << 6);
	416	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
	417	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	418	}
	419
	420	packet.type = SR_DF_LOGIC;
	421	packet.payload = &logic;
	422	logic.length = 1024;
	423	logic.unitsize = 1;
	424	logic.data = logic_out;
	425	sr_session_send(cb_data, &packet);
	426
eb913174	427	devc->num_samples += 1024;
eb913174	428
df92e5cf	429	// Dont bother fixing this yet, keep it "old style"
	430	/*
	431	packet.type = SR_DF_ANALOG;
	432	packet.length = 1024;
	433	packet.unitsize = sizeof(double);
	434	packet.payload = analog_out;
	435	sr_session_send(ctx->session_dev_id, &packet);
	436	*/
	437
eb913174	438	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
	439	sr_info("Requested number of samples reached.");
	440	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	441	}
5a24e89c	442
4db2aaff	443	return TRUE;
df92e5cf	444	}
5a24e89c	445
	446	SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
	447	{
5a24e89c	448	struct dev_context *devc;
	449	struct sr_probe *probe;
	450	GSList *l;
	451	int probe_bit, stage, i;
	452	char *tc;
	453
087a9161	454
5a24e89c	455	devc = sdi->priv;
5a24e89c	456
087a9161	457	devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	458	devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
	459	devc->dso_trigger_voltage = 3;
	460	devc->dso_probe_attn = 1;
	461	devc->trigger_outsrc = 0;
	462	devc->trigger_chan = 3; //LA combination trigger
	463	devc->use_trigger = FALSE;
	464
5a24e89c	465	for (l = sdi->probes; l; l = l->next) {
	466	probe = (struct sr_probe *)l->data;
	467	if (probe->enabled == FALSE)
	468	continue;
	469
087a9161	470	int probe_bit = 1 << (probe->index);
5a24e89c	471	if (!(probe->trigger))
	472	continue;
	473
087a9161	474	devc->use_trigger = TRUE;
5a24e89c	475	//Configure trigger mask and value.
5a24e89c	476	for (tc = probe->trigger; *tc; tc++) {
087a9161	477	devc->la_trigger_mask &= ~probe_bit;
	478	if (*tc == '1')
	479	devc->la_trigger \|= probe_bit;
	480	}
	481	}
5a24e89c	482
5a24e89c	483	return SR_OK;
5a24e89c	484	}
	485
	486
	487