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Commit | Line | Data |
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df92e5cf | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
df92e5cf | 3 | * |
f48cef78 UH |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> |
5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> | |
6 | * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com> | |
df92e5cf | 7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
753d722f UH |
24 | /* serial protocol */ |
25 | #define mso_trans(a, v) \ | |
26 | (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \ | |
27 | ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7)) | |
28 | ||
29 | static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e }; | |
30 | static const char mso_foot[] = { 0x7e }; | |
31 | ||
df92e5cf | 32 | extern SR_PRIV struct sr_dev_driver link_mso19_driver_info; |
df92e5cf | 33 | |
4db2aaff | 34 | SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial, |
00b44ccb | 35 | uint16_t payload[], int n) |
4db2aaff | 36 | { |
37 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
38 | char *p, *buf; | |
39 | ||
40 | ret = SR_ERR; | |
41 | ||
42 | if (serial->fd < 0) | |
43 | goto ret; | |
44 | ||
45 | if (!(buf = g_try_malloc(s))) { | |
46 | sr_err("Failed to malloc message buffer."); | |
47 | ret = SR_ERR_MALLOC; | |
48 | goto ret; | |
49 | } | |
50 | ||
51 | p = buf; | |
52 | memcpy(p, mso_head, sizeof(mso_head)); | |
53 | p += sizeof(mso_head); | |
54 | ||
55 | for (i = 0; i < n; i++) { | |
a24e9d04 | 56 | *(uint16_t *) p = g_htons(payload[i]); |
4db2aaff | 57 | p += 2; |
58 | } | |
59 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
60 | ||
61 | w = 0; | |
62 | while (w < s) { | |
63 | ret = serial_write(serial, buf + w, s - w); | |
64 | if (ret < 0) { | |
65 | ret = SR_ERR; | |
66 | goto free; | |
67 | } | |
68 | w += ret; | |
69 | } | |
70 | ret = SR_OK; | |
71 | free: | |
72 | g_free(buf); | |
73 | ret: | |
74 | return ret; | |
75 | } | |
76 | ||
753d722f | 77 | SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi) |
4b719338 | 78 | { |
79 | struct dev_context *devc = sdi->priv; | |
087a9161 | 80 | uint16_t threshold_value = mso_calc_raw_from_mv(devc); |
4b719338 | 81 | |
00b44ccb UH |
82 | threshold_value = 0x153C; |
83 | uint8_t trigger_config = 0; | |
4b719338 | 84 | |
00b44ccb UH |
85 | if (devc->trigger_slope) |
86 | trigger_config |= 0x04; //Trigger on falling edge | |
4b719338 | 87 | |
88 | switch (devc->trigger_outsrc) { | |
89 | case 1: | |
00b44ccb | 90 | trigger_config |= 0x00; //Trigger pulse output |
4b719338 | 91 | break; |
92 | case 2: | |
00b44ccb | 93 | trigger_config |= 0x08; //PWM DAC from the pattern generator buffer |
4b719338 | 94 | break; |
95 | case 3: | |
00b44ccb | 96 | trigger_config |= 0x18; //White noise |
4b719338 | 97 | break; |
4b719338 | 98 | } |
99 | ||
087a9161 | 100 | switch (devc->trigger_chan) { |
00b44ccb UH |
101 | case 0: |
102 | trigger_config |= 0x00; //DSO level trigger //b00000000 | |
103 | break; | |
104 | case 1: | |
105 | trigger_config |= 0x20; //DSO level trigger & width < trigger_width | |
106 | break; | |
107 | case 2: | |
108 | trigger_config |= 0x40; //DSO level trigger & width >= trigger_width | |
109 | break; | |
110 | case 3: | |
111 | trigger_config |= 0x60; //LA combination trigger | |
112 | break; | |
113 | } | |
114 | ||
115 | //Last bit of trigger config reg 4 needs to be 1 for trigger enable, | |
116 | //otherwise the trigger is not enabled | |
117 | if (devc->use_trigger) | |
118 | trigger_config |= 0x80; | |
087a9161 | 119 | |
120 | uint16_t ops[18]; | |
121 | ops[0] = mso_trans(3, threshold_value & 0xff); | |
00b44ccb | 122 | //The trigger_config also holds the 2 MSB bits from the threshold value |
5952553f | 123 | ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03)); |
087a9161 | 124 | ops[2] = mso_trans(5, devc->la_trigger); |
125 | ops[3] = mso_trans(6, devc->la_trigger_mask); | |
126 | ops[4] = mso_trans(7, devc->trigger_holdoff[0]); | |
127 | ops[5] = mso_trans(8, devc->trigger_holdoff[1]); | |
128 | ||
129 | ops[6] = mso_trans(11, | |
00b44ccb UH |
130 | devc->dso_trigger_width / |
131 | SR_HZ_TO_NS(devc->cur_rate)); | |
4b719338 | 132 | |
133 | /* Select the SPI/I2C trigger config bank */ | |
087a9161 | 134 | ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2))); |
4b719338 | 135 | /* Configure the SPI/I2C protocol trigger */ |
087a9161 | 136 | ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]); |
137 | ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]); | |
138 | ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]); | |
139 | ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]); | |
140 | ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]); | |
141 | ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]); | |
142 | ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]); | |
143 | ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]); | |
144 | ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode); | |
4b719338 | 145 | /* Select the default config bank */ |
087a9161 | 146 | ops[17] = mso_trans(REG_CTL2, devc->ctlbase2); |
4b719338 | 147 | |
4db2aaff | 148 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
4b719338 | 149 | } |
150 | ||
753d722f | 151 | SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi) |
4b719338 | 152 | { |
153 | struct dev_context *devc = sdi->priv; | |
154 | ||
155 | return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]); | |
156 | } | |
157 | ||
158 | SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi) | |
159 | { | |
160 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
161 | struct dev_context *devc = sdi->priv; | |
162 | ||
163 | sr_dbg("Requesting buffer dump."); | |
164 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
165 | } | |
166 | ||
753d722f | 167 | SR_PRIV int mso_arm(const struct sr_dev_inst *sdi) |
4b719338 | 168 | { |
169 | struct dev_context *devc = sdi->priv; | |
170 | uint16_t ops[] = { | |
171 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM), | |
172 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM), | |
173 | mso_trans(REG_CTL1, devc->ctlbase1), | |
174 | }; | |
175 | ||
176 | sr_dbg("Requesting trigger arm."); | |
177 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
178 | } | |
179 | ||
180 | SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi) | |
181 | { | |
182 | struct dev_context *devc = sdi->priv; | |
183 | uint16_t ops[] = { | |
184 | mso_trans(REG_CTL1, devc->ctlbase1 | 8), | |
185 | mso_trans(REG_CTL1, devc->ctlbase1), | |
186 | }; | |
187 | ||
188 | sr_dbg("Requesting forced capture."); | |
189 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
190 | } | |
191 | ||
753d722f | 192 | SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val) |
4b719338 | 193 | { |
194 | struct dev_context *devc = sdi->priv; | |
195 | uint16_t ops[] = { | |
196 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
197 | mso_trans(REG_DAC2, val & 0xff), | |
198 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC), | |
199 | }; | |
200 | ||
201 | sr_dbg("Setting dac word to 0x%x.", val); | |
202 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
203 | } | |
204 | ||
00b44ccb | 205 | SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc) |
4b719338 | 206 | { |
207 | return (uint16_t) (0x200 - | |
00b44ccb UH |
208 | ((devc->dso_trigger_voltage / devc->dso_probe_attn) / |
209 | devc->vbit)); | |
4b719338 | 210 | } |
211 | ||
df92e5cf | 212 | SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct, |
00b44ccb | 213 | struct dev_context *devc) |
df92e5cf | 214 | { |
215 | unsigned int u1, u2, u3, u4, u5, u6; | |
216 | ||
31e53772 UH |
217 | (void)iProduct; |
218 | ||
00b44ccb UH |
219 | /* FIXME: This code is in the original app, but I think its |
220 | * used only for the GUI */ | |
221 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
222 | devc->num_sample_rates = 0x16; | |
223 | else | |
224 | devc->num_sample_rates = 0x10; */ | |
df92e5cf | 225 | |
226 | /* parse iSerial */ | |
227 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
00b44ccb | 228 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) |
df92e5cf | 229 | return SR_ERR; |
230 | devc->hwmodel = u4; | |
231 | devc->hwrev = u5; | |
df92e5cf | 232 | devc->vbit = u1 / 10000; |
233 | if (devc->vbit == 0) | |
234 | devc->vbit = 4.19195; | |
235 | devc->dac_offset = u2; | |
236 | if (devc->dac_offset == 0) | |
237 | devc->dac_offset = 0x1ff; | |
238 | devc->offset_range = u3; | |
239 | if (devc->offset_range == 0) | |
240 | devc->offset_range = 0x17d; | |
241 | ||
242 | /* | |
243 | * FIXME: There is more code on the original software to handle | |
244 | * bigger iSerial strings, but as I can't test on my device | |
245 | * I will not implement it yet | |
246 | */ | |
247 | ||
248 | return SR_OK; | |
249 | } | |
250 | ||
4db2aaff | 251 | SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi) |
df92e5cf | 252 | { |
4db2aaff | 253 | struct dev_context *devc = sdi->priv; |
254 | uint16_t ops[2]; | |
df92e5cf | 255 | |
4db2aaff | 256 | ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC)); |
257 | ops[1] = mso_trans(REG_CTL1, devc->ctlbase1); | |
258 | devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
df92e5cf | 259 | |
4db2aaff | 260 | sr_dbg("Requesting ADC reset."); |
261 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
262 | } | |
df92e5cf | 263 | |
4db2aaff | 264 | SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi) |
265 | { | |
266 | struct dev_context *devc = sdi->priv; | |
267 | uint16_t ops[1]; | |
df92e5cf | 268 | |
4db2aaff | 269 | devc->ctlbase1 |= BIT_CTL1_RESETFSM; |
270 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 271 | |
4db2aaff | 272 | sr_dbg("Requesting ADC reset."); |
273 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
df92e5cf | 274 | } |
275 | ||
4db2aaff | 276 | SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
df92e5cf | 277 | { |
278 | struct dev_context *devc = sdi->priv; | |
4db2aaff | 279 | uint16_t ops[1]; |
df92e5cf | 280 | |
4db2aaff | 281 | devc->ctlbase1 &= ~BIT_CTL1_LED; |
282 | if (state) | |
283 | devc->ctlbase1 |= BIT_CTL1_LED; | |
284 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 285 | |
4db2aaff | 286 | sr_dbg("Requesting LED toggle."); |
df92e5cf | 287 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
288 | } | |
289 | ||
290 | SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi) | |
291 | { | |
292 | struct sr_datafeed_packet packet; | |
293 | struct dev_context *devc; | |
294 | ||
295 | devc = sdi->priv; | |
102f1239 | 296 | serial_source_remove(sdi->session, devc->serial); |
df92e5cf | 297 | |
298 | /* Terminate session */ | |
299 | packet.type = SR_DF_END; | |
300 | sr_session_send(sdi, &packet); | |
301 | } | |
302 | ||
303 | SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val) | |
304 | { | |
305 | uint16_t ops[] = { | |
306 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
307 | mso_trans(REG_CLKRATE2, val & 0xff), | |
308 | }; | |
309 | ||
310 | sr_dbg("Setting clkrate word to 0x%x.", val); | |
311 | return mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
312 | } | |
313 | ||
753d722f | 314 | SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate) |
df92e5cf | 315 | { |
316 | struct dev_context *devc = sdi->priv; | |
317 | unsigned int i; | |
318 | int ret = SR_ERR; | |
319 | ||
320 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
321 | if (rate_map[i].rate == rate) { | |
322 | devc->ctlbase2 = rate_map[i].slowmode; | |
4b719338 | 323 | ret = mso_clkrate_out(devc->serial, rate_map[i].val); |
df92e5cf | 324 | if (ret == SR_OK) |
325 | devc->cur_rate = rate; | |
326 | return ret; | |
327 | } | |
328 | } | |
4db2aaff | 329 | |
00b44ccb | 330 | if (ret != SR_OK) |
4db2aaff | 331 | sr_err("Unsupported rate."); |
332 | ||
df92e5cf | 333 | return ret; |
334 | } | |
335 | ||
365f04d6 | 336 | SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info) |
df92e5cf | 337 | { |
338 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
339 | int ret; | |
340 | ||
341 | sr_dbg("Requesting trigger state."); | |
342 | ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
343 | if (info == NULL || ret != SR_OK) | |
344 | return ret; | |
345 | ||
00b44ccb UH |
346 | uint8_t buf = 0; |
347 | if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */ | |
df92e5cf | 348 | ret = SR_ERR; |
365f04d6 | 349 | if (!info) |
350 | *info = buf; | |
df92e5cf | 351 | |
352 | sr_dbg("Trigger state is: 0x%x.", *info); | |
353 | return ret; | |
354 | } | |
355 | ||
356 | SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data) | |
357 | { | |
df92e5cf | 358 | struct sr_datafeed_packet packet; |
359 | struct sr_datafeed_logic logic; | |
360 | struct sr_dev_inst *sdi; | |
df92e5cf | 361 | GSList *l; |
4db2aaff | 362 | int i; |
df92e5cf | 363 | |
4db2aaff | 364 | struct drv_context *drvc = di->priv; |
df92e5cf | 365 | |
366 | /* Find this device's devc struct by its fd. */ | |
4db2aaff | 367 | struct dev_context *devc = NULL; |
df92e5cf | 368 | for (l = drvc->instances; l; l = l->next) { |
369 | sdi = l->data; | |
370 | devc = sdi->priv; | |
371 | if (devc->serial->fd == fd) | |
372 | break; | |
373 | devc = NULL; | |
374 | } | |
375 | if (!devc) | |
376 | /* Shouldn't happen. */ | |
377 | return TRUE; | |
378 | ||
379 | (void)revents; | |
380 | ||
381 | uint8_t in[1024]; | |
382 | size_t s = serial_read(devc->serial, in, sizeof(in)); | |
5a24e89c | 383 | |
df92e5cf | 384 | if (s <= 0) |
385 | return FALSE; | |
00b44ccb UH |
386 | |
387 | /* Check if we triggered, then send a command that we are ready | |
388 | * to read the data */ | |
389 | if (devc->trigger_state != MSO_TRIGGER_DATAREADY) { | |
390 | devc->trigger_state = in[0]; | |
391 | if (devc->trigger_state == MSO_TRIGGER_DATAREADY) { | |
392 | mso_read_buffer(sdi); | |
393 | devc->buffer_n = 0; | |
394 | } else { | |
395 | mso_check_trigger(devc->serial, NULL); | |
396 | } | |
397 | return TRUE; | |
398 | } | |
df92e5cf | 399 | |
400 | /* the hardware always dumps 1024 samples, 24bits each */ | |
401 | if (devc->buffer_n < 3072) { | |
402 | memcpy(devc->buffer + devc->buffer_n, in, s); | |
403 | devc->buffer_n += s; | |
404 | } | |
405 | if (devc->buffer_n < 3072) | |
5a24e89c | 406 | return TRUE; |
df92e5cf | 407 | |
408 | /* do the conversion */ | |
409 | uint8_t logic_out[1024]; | |
410 | double analog_out[1024]; | |
411 | for (i = 0; i < 1024; i++) { | |
412 | /* FIXME: Need to do conversion to mV */ | |
413 | analog_out[i] = (devc->buffer[i * 3] & 0x3f) | | |
00b44ccb | 414 | ((devc->buffer[i * 3 + 1] & 0xf) << 6); |
ff08a52a | 415 | (void)analog_out; |
df92e5cf | 416 | logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) | |
00b44ccb | 417 | ((devc->buffer[i * 3 + 2] & 0x3f) << 2); |
df92e5cf | 418 | } |
419 | ||
420 | packet.type = SR_DF_LOGIC; | |
421 | packet.payload = &logic; | |
422 | logic.length = 1024; | |
423 | logic.unitsize = 1; | |
424 | logic.data = logic_out; | |
425 | sr_session_send(cb_data, &packet); | |
426 | ||
00b44ccb | 427 | devc->num_samples += 1024; |
eb913174 | 428 | |
00b44ccb UH |
429 | if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { |
430 | sr_info("Requested number of samples reached."); | |
431 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
432 | } | |
433 | ||
434 | return TRUE; | |
df92e5cf | 435 | } |
5a24e89c | 436 | |
ba7dd8bb | 437 | SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi) |
5a24e89c | 438 | { |
5a24e89c | 439 | struct dev_context *devc; |
ba7dd8bb | 440 | struct sr_channel *ch; |
5a24e89c | 441 | GSList *l; |
5a24e89c | 442 | char *tc; |
443 | ||
5a24e89c | 444 | devc = sdi->priv; |
5a24e89c | 445 | |
00b44ccb UH |
446 | devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored). |
447 | devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode). | |
448 | devc->dso_trigger_voltage = 3; | |
449 | devc->dso_probe_attn = 1; | |
450 | devc->trigger_outsrc = 0; | |
451 | devc->trigger_chan = 3; //LA combination trigger | |
452 | devc->use_trigger = FALSE; | |
087a9161 | 453 | |
ba7dd8bb UH |
454 | for (l = sdi->channels; l; l = l->next) { |
455 | ch = (struct sr_channel *)l->data; | |
456 | if (ch->enabled == FALSE) | |
5a24e89c | 457 | continue; |
458 | ||
ba7dd8bb UH |
459 | int channel_bit = 1 << (ch->index); |
460 | if (!(ch->trigger)) | |
5a24e89c | 461 | continue; |
462 | ||
00b44ccb | 463 | devc->use_trigger = TRUE; |
5a24e89c | 464 | //Configure trigger mask and value. |
ba7dd8bb UH |
465 | for (tc = ch->trigger; *tc; tc++) { |
466 | devc->la_trigger_mask &= ~channel_bit; | |
00b44ccb | 467 | if (*tc == '1') |
ba7dd8bb | 468 | devc->la_trigger |= channel_bit; |
00b44ccb UH |
469 | } |
470 | } | |
5a24e89c | 471 | |
472 | return SR_OK; | |
5a24e89c | 473 | } |