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df92e5cf | 1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "protocol.h" | |
4db2aaff | 21 | #include <arpa/inet.h> |
df92e5cf | 22 | |
23 | extern SR_PRIV struct sr_dev_driver link_mso19_driver_info; | |
24 | static struct sr_dev_driver *di = &link_mso19_driver_info; | |
25 | ||
4db2aaff | 26 | SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial, |
27 | uint16_t payload[], int n) | |
28 | { | |
29 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
30 | char *p, *buf; | |
31 | ||
32 | ret = SR_ERR; | |
33 | ||
34 | if (serial->fd < 0) | |
35 | goto ret; | |
36 | ||
37 | if (!(buf = g_try_malloc(s))) { | |
38 | sr_err("Failed to malloc message buffer."); | |
39 | ret = SR_ERR_MALLOC; | |
40 | goto ret; | |
41 | } | |
42 | ||
43 | p = buf; | |
44 | memcpy(p, mso_head, sizeof(mso_head)); | |
45 | p += sizeof(mso_head); | |
46 | ||
47 | for (i = 0; i < n; i++) { | |
48 | *(uint16_t *) p = htons(payload[i]); | |
49 | p += 2; | |
50 | } | |
51 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
52 | ||
53 | w = 0; | |
54 | while (w < s) { | |
55 | ret = serial_write(serial, buf + w, s - w); | |
56 | if (ret < 0) { | |
57 | ret = SR_ERR; | |
58 | goto free; | |
59 | } | |
60 | w += ret; | |
61 | } | |
62 | ret = SR_OK; | |
63 | free: | |
64 | g_free(buf); | |
65 | ret: | |
66 | return ret; | |
67 | } | |
68 | ||
69 | ||
4b719338 | 70 | SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi) |
71 | { | |
72 | struct dev_context *devc = sdi->priv; | |
73 | uint16_t ops[16]; | |
74 | uint16_t dso_trigger = mso_calc_raw_from_mv(devc); | |
75 | ||
76 | dso_trigger &= 0x3ff; | |
77 | if ((!devc->trigger_slope && devc->trigger_chan == 1) || | |
78 | (devc->trigger_slope && | |
79 | (devc->trigger_chan == 0 || | |
80 | devc->trigger_chan == 2 || | |
81 | devc->trigger_chan == 3))) | |
82 | dso_trigger |= 0x400; | |
83 | ||
84 | switch (devc->trigger_chan) { | |
85 | case 1: | |
86 | dso_trigger |= 0xe000; | |
87 | case 2: | |
88 | dso_trigger |= 0x4000; | |
89 | break; | |
90 | case 3: | |
91 | dso_trigger |= 0x2000; | |
92 | break; | |
93 | case 4: | |
94 | dso_trigger |= 0xa000; | |
95 | break; | |
96 | case 5: | |
97 | dso_trigger |= 0x8000; | |
98 | break; | |
99 | default: | |
100 | case 0: | |
101 | break; | |
102 | } | |
103 | ||
104 | switch (devc->trigger_outsrc) { | |
105 | case 1: | |
106 | dso_trigger |= 0x800; | |
107 | break; | |
108 | case 2: | |
109 | dso_trigger |= 0x1000; | |
110 | break; | |
111 | case 3: | |
112 | dso_trigger |= 0x1800; | |
113 | break; | |
114 | ||
115 | } | |
116 | ||
117 | ops[0] = mso_trans(5, devc->la_trigger); | |
118 | ops[1] = mso_trans(6, devc->la_trigger_mask); | |
119 | ops[2] = mso_trans(3, dso_trigger & 0xff); | |
120 | ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff); | |
121 | ops[4] = mso_trans(11, | |
122 | devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate)); | |
123 | ||
124 | /* Select the SPI/I2C trigger config bank */ | |
125 | ops[5] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2))); | |
126 | /* Configure the SPI/I2C protocol trigger */ | |
127 | ops[6] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]); | |
128 | ops[7] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]); | |
129 | ops[8] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]); | |
130 | ops[9] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]); | |
131 | ops[10] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]); | |
132 | ops[11] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]); | |
133 | ops[12] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]); | |
134 | ops[13] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]); | |
135 | ops[14] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode); | |
136 | /* Select the default config bank */ | |
137 | ops[15] = mso_trans(REG_CTL2, devc->ctlbase2); | |
138 | ||
4db2aaff | 139 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
4b719338 | 140 | } |
141 | ||
142 | SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi) | |
143 | { | |
144 | struct dev_context *devc = sdi->priv; | |
145 | ||
146 | return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]); | |
147 | } | |
148 | ||
149 | SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi) | |
150 | { | |
151 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
152 | struct dev_context *devc = sdi->priv; | |
153 | ||
154 | sr_dbg("Requesting buffer dump."); | |
155 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
156 | } | |
157 | ||
158 | SR_PRIV int mso_arm(struct sr_dev_inst *sdi) | |
159 | { | |
160 | struct dev_context *devc = sdi->priv; | |
161 | uint16_t ops[] = { | |
162 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM), | |
163 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM), | |
164 | mso_trans(REG_CTL1, devc->ctlbase1), | |
165 | }; | |
166 | ||
167 | sr_dbg("Requesting trigger arm."); | |
168 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
169 | } | |
170 | ||
171 | SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi) | |
172 | { | |
173 | struct dev_context *devc = sdi->priv; | |
174 | uint16_t ops[] = { | |
175 | mso_trans(REG_CTL1, devc->ctlbase1 | 8), | |
176 | mso_trans(REG_CTL1, devc->ctlbase1), | |
177 | }; | |
178 | ||
179 | sr_dbg("Requesting forced capture."); | |
180 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
181 | } | |
182 | ||
183 | SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val) | |
184 | { | |
185 | struct dev_context *devc = sdi->priv; | |
186 | uint16_t ops[] = { | |
187 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
188 | mso_trans(REG_DAC2, val & 0xff), | |
189 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC), | |
190 | }; | |
191 | ||
192 | sr_dbg("Setting dac word to 0x%x.", val); | |
193 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
194 | } | |
195 | ||
196 | SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc) | |
197 | { | |
198 | return (uint16_t) (0x200 - | |
199 | ((devc->dso_trigger_voltage / devc->dso_probe_attn) / | |
200 | devc->vbit)); | |
201 | } | |
202 | ||
203 | ||
df92e5cf | 204 | SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct, |
205 | struct dev_context *devc) | |
206 | { | |
207 | unsigned int u1, u2, u3, u4, u5, u6; | |
208 | ||
209 | iProduct = iProduct; | |
210 | /* FIXME: This code is in the original app, but I think its | |
211 | * used only for the GUI */ | |
212 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
213 | devc->num_sample_rates = 0x16; | |
214 | else | |
215 | devc->num_sample_rates = 0x10; */ | |
216 | ||
217 | ||
218 | /* parse iSerial */ | |
219 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
220 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) | |
221 | return SR_ERR; | |
222 | devc->hwmodel = u4; | |
223 | devc->hwrev = u5; | |
df92e5cf | 224 | devc->vbit = u1 / 10000; |
225 | if (devc->vbit == 0) | |
226 | devc->vbit = 4.19195; | |
227 | devc->dac_offset = u2; | |
228 | if (devc->dac_offset == 0) | |
229 | devc->dac_offset = 0x1ff; | |
230 | devc->offset_range = u3; | |
231 | if (devc->offset_range == 0) | |
232 | devc->offset_range = 0x17d; | |
233 | ||
234 | /* | |
235 | * FIXME: There is more code on the original software to handle | |
236 | * bigger iSerial strings, but as I can't test on my device | |
237 | * I will not implement it yet | |
238 | */ | |
239 | ||
240 | return SR_OK; | |
241 | } | |
242 | ||
4db2aaff | 243 | SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi) |
df92e5cf | 244 | { |
4db2aaff | 245 | struct dev_context *devc = sdi->priv; |
246 | uint16_t ops[2]; | |
df92e5cf | 247 | |
4db2aaff | 248 | ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC)); |
249 | ops[1] = mso_trans(REG_CTL1, devc->ctlbase1); | |
250 | devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
df92e5cf | 251 | |
4db2aaff | 252 | sr_dbg("Requesting ADC reset."); |
253 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
254 | } | |
df92e5cf | 255 | |
4db2aaff | 256 | SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi) |
257 | { | |
258 | struct dev_context *devc = sdi->priv; | |
259 | uint16_t ops[1]; | |
df92e5cf | 260 | |
4db2aaff | 261 | devc->ctlbase1 |= BIT_CTL1_RESETFSM; |
262 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 263 | |
4db2aaff | 264 | sr_dbg("Requesting ADC reset."); |
265 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
df92e5cf | 266 | } |
267 | ||
4db2aaff | 268 | SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
df92e5cf | 269 | { |
270 | struct dev_context *devc = sdi->priv; | |
4db2aaff | 271 | uint16_t ops[1]; |
df92e5cf | 272 | |
4db2aaff | 273 | devc->ctlbase1 &= ~BIT_CTL1_LED; |
274 | if (state) | |
275 | devc->ctlbase1 |= BIT_CTL1_LED; | |
276 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 277 | |
4db2aaff | 278 | sr_dbg("Requesting LED toggle."); |
df92e5cf | 279 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
280 | } | |
281 | ||
282 | SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi) | |
283 | { | |
284 | struct sr_datafeed_packet packet; | |
285 | struct dev_context *devc; | |
286 | ||
287 | devc = sdi->priv; | |
288 | sr_source_remove(devc->serial->fd); | |
289 | ||
290 | /* Terminate session */ | |
291 | packet.type = SR_DF_END; | |
292 | sr_session_send(sdi, &packet); | |
293 | } | |
294 | ||
295 | SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val) | |
296 | { | |
297 | uint16_t ops[] = { | |
298 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
299 | mso_trans(REG_CLKRATE2, val & 0xff), | |
300 | }; | |
301 | ||
302 | sr_dbg("Setting clkrate word to 0x%x.", val); | |
303 | return mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
304 | } | |
305 | ||
306 | SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate) | |
307 | { | |
308 | struct dev_context *devc = sdi->priv; | |
309 | unsigned int i; | |
310 | int ret = SR_ERR; | |
311 | ||
312 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
313 | if (rate_map[i].rate == rate) { | |
314 | devc->ctlbase2 = rate_map[i].slowmode; | |
4b719338 | 315 | ret = mso_clkrate_out(devc->serial, rate_map[i].val); |
df92e5cf | 316 | if (ret == SR_OK) |
317 | devc->cur_rate = rate; | |
318 | return ret; | |
319 | } | |
320 | } | |
4db2aaff | 321 | |
322 | if (ret != SR_OK) | |
323 | sr_err("Unsupported rate."); | |
324 | ||
df92e5cf | 325 | return ret; |
326 | } | |
327 | ||
328 | ||
329 | ||
330 | ||
331 | ||
332 | SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info) | |
333 | { | |
334 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
335 | int ret; | |
336 | ||
337 | sr_dbg("Requesting trigger state."); | |
5a24e89c | 338 | printf("Send Controll message\n"); |
df92e5cf | 339 | ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); |
340 | if (info == NULL || ret != SR_OK) | |
341 | return ret; | |
342 | ||
343 | ||
5a24e89c | 344 | printf("REad buffer\n"); |
df92e5cf | 345 | uint8_t buf = 0; |
346 | if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */ | |
347 | ret = SR_ERR; | |
348 | *info = buf; | |
349 | ||
350 | sr_dbg("Trigger state is: 0x%x.", *info); | |
351 | return ret; | |
352 | } | |
353 | ||
354 | SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data) | |
355 | { | |
356 | ||
357 | struct sr_datafeed_packet packet; | |
358 | struct sr_datafeed_logic logic; | |
359 | struct sr_dev_inst *sdi; | |
df92e5cf | 360 | GSList *l; |
4db2aaff | 361 | int i; |
df92e5cf | 362 | |
4db2aaff | 363 | struct drv_context *drvc = di->priv; |
df92e5cf | 364 | |
365 | /* Find this device's devc struct by its fd. */ | |
4db2aaff | 366 | struct dev_context *devc = NULL; |
df92e5cf | 367 | for (l = drvc->instances; l; l = l->next) { |
368 | sdi = l->data; | |
369 | devc = sdi->priv; | |
370 | if (devc->serial->fd == fd) | |
371 | break; | |
372 | devc = NULL; | |
373 | } | |
374 | if (!devc) | |
375 | /* Shouldn't happen. */ | |
376 | return TRUE; | |
377 | ||
378 | (void)revents; | |
379 | ||
380 | uint8_t in[1024]; | |
381 | size_t s = serial_read(devc->serial, in, sizeof(in)); | |
5a24e89c | 382 | |
df92e5cf | 383 | if (s <= 0) |
384 | return FALSE; | |
385 | ||
5a24e89c | 386 | /* Check if we triggered, then send a command that we are ready |
387 | * to read the data */ | |
df92e5cf | 388 | if (devc->trigger_state != MSO_TRIGGER_DATAREADY) { |
389 | devc->trigger_state = in[0]; | |
5a24e89c | 390 | printf("Got %c for trigger \n", in[0]); |
df92e5cf | 391 | if (devc->trigger_state == MSO_TRIGGER_DATAREADY) { |
5a24e89c | 392 | printf("Trigger is ready %c\n", MSO_TRIGGER_DATAREADY); |
df92e5cf | 393 | mso_read_buffer(sdi); |
394 | devc->buffer_n = 0; | |
395 | } else { | |
396 | mso_check_trigger(devc->serial, NULL); | |
397 | } | |
5a24e89c | 398 | return TRUE; |
df92e5cf | 399 | } |
400 | ||
401 | /* the hardware always dumps 1024 samples, 24bits each */ | |
402 | if (devc->buffer_n < 3072) { | |
403 | memcpy(devc->buffer + devc->buffer_n, in, s); | |
404 | devc->buffer_n += s; | |
405 | } | |
406 | if (devc->buffer_n < 3072) | |
5a24e89c | 407 | return TRUE; |
df92e5cf | 408 | |
5a24e89c | 409 | printf("Got samples, write out the data\n"); |
df92e5cf | 410 | /* do the conversion */ |
411 | uint8_t logic_out[1024]; | |
412 | double analog_out[1024]; | |
413 | for (i = 0; i < 1024; i++) { | |
414 | /* FIXME: Need to do conversion to mV */ | |
415 | analog_out[i] = (devc->buffer[i * 3] & 0x3f) | | |
416 | ((devc->buffer[i * 3 + 1] & 0xf) << 6); | |
417 | logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) | | |
418 | ((devc->buffer[i * 3 + 2] & 0x3f) << 2); | |
419 | } | |
420 | ||
421 | packet.type = SR_DF_LOGIC; | |
422 | packet.payload = &logic; | |
423 | logic.length = 1024; | |
424 | logic.unitsize = 1; | |
425 | logic.data = logic_out; | |
5a24e89c | 426 | printf("Send Data\n"); |
df92e5cf | 427 | sr_session_send(cb_data, &packet); |
428 | ||
429 | // Dont bother fixing this yet, keep it "old style" | |
430 | /* | |
431 | packet.type = SR_DF_ANALOG; | |
432 | packet.length = 1024; | |
433 | packet.unitsize = sizeof(double); | |
434 | packet.payload = analog_out; | |
435 | sr_session_send(ctx->session_dev_id, &packet); | |
436 | */ | |
437 | ||
5a24e89c | 438 | //printf("Send END\n"); |
439 | //packet.type = SR_DF_END; | |
440 | //sr_session_send(devc->session_dev_id, &packet); | |
df92e5cf | 441 | |
5a24e89c | 442 | // serial_flush(devc->serial); |
443 | // abort_acquisition(sdi); | |
444 | // serial_close(devc->serial); | |
445 | ||
446 | return FALSE; | |
447 | printf("REturn \n"); | |
4db2aaff | 448 | return TRUE; |
df92e5cf | 449 | } |
5a24e89c | 450 | |
451 | SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi) | |
452 | { | |
453 | ||
454 | struct dev_context *devc; | |
455 | struct sr_probe *probe; | |
456 | GSList *l; | |
457 | int probe_bit, stage, i; | |
458 | char *tc; | |
459 | ||
460 | /* | |
461 | devc = sdi->priv; | |
462 | for (i = 0; i < NUM_TRIGGER_STAGES; i++) { | |
463 | devc->la_trigger_mask[i] = 0; | |
464 | devc->la_trigger[i] = 0; | |
465 | } | |
466 | ||
467 | stage = -1; | |
468 | for (l = sdi->probes; l; l = l->next) { | |
469 | probe = (struct sr_probe *)l->data; | |
470 | if (probe->enabled == FALSE) | |
471 | continue; | |
472 | ||
473 | //if (probe->index > 7) | |
474 | // devc->sample_wide = TRUE; | |
475 | ||
476 | probe_bit = 1 << (probe->index); | |
477 | if (!(probe->trigger)) | |
478 | continue; | |
479 | ||
480 | //Configure trigger mask and value. | |
481 | stage = 0; | |
482 | for (tc = probe->trigger; *tc; tc++) { | |
483 | devc->trigger_mask[stage] |= probe_bit; | |
484 | if (*tc == '1') | |
485 | devc->trigger_value[stage] |= probe_bit; | |
486 | stage++; | |
487 | if (stage > NUM_TRIGGER_STAGES) | |
488 | return SR_ERR; | |
489 | } | |
490 | } | |
491 | ||
492 | */ | |
493 | ||
494 | //if (stage == -1) | |
495 | // /* | |
496 | // * We didn't configure any triggers, make sure acquisition | |
497 | // * doesn't wait for any. | |
498 | // */ | |
499 | // devc->trigger_stage = TRIGGER_FIRED; | |
500 | //else | |
501 | // devc->trigger_stage = 0; | |
502 | ||
503 | return SR_OK; | |
504 | ||
505 | ||
506 | } | |
507 | ||
508 | ||
509 |