Difference between revisions of "Main Page"

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== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Documentation</span> ==
== [[File:Sigrok_stone.png]] <span style="font-variant:small-caps">Documentation</span> ==


* [[Downloads]]
* Building: [[Linux]], [[Mac OS X]], [[Windows]], [[FreeBSD]]
* Building: [[Linux]], [[Mac OS X]], [[Windows]], [[FreeBSD]]
* [[Status]]
* [[FAQ]]
* [[Supported hardware]]
* [[Command-line]]
* [[Command-line]]
* [[GUI|Cross-platform GUI]]
* [[GUI|Cross-platform GUI]]
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* [[Protocol decoders]]
* [[Protocol decoders]]
* [[Logic Analyzer Comparison]]
* [[Logic Analyzer Comparison]]
* [[Current events]], [[Press]], [[Logo]]
* [[Press]]
* [[Logo]]


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'''<span style="font-variant:small-caps; font-size:120%">[[File:Sigrok_stone.png]] [[News]]</span>'''<hr />
'''<span style="font-variant:small-caps; font-size:120%">[[File:Sigrok_stone.png]] [[News]] / [[Current events|Events]]</span>'''<hr />
<!-- Please always make this list 7 items long (7 most recent news items). -->
<!-- Please always make this list 7 items long (7 most recent news items). -->
<small>
<small>

Revision as of 22:40, 28 April 2011

The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source logic analyzer software that supports various (usually USB-based) logic analyzer hardware products. The code is licensed under the terms of the GNU GPL. Some of the design goals and features include:

  • Broad hardware support. Supports a wide variety of logic analyzers from various vendors with different capabilities.
  • Cross-platform. Works on Linux, Mac OS X, Windows, and FreeBSD, and on many architectures including x86, ARM, Sparc and PowerPC.
  • Scriptable protocol decoding. Extendable with protocol decoders and analyzers written in Python.
  • Format support. Supports various input and output formats (raw, ASCII, hex, CSV, gnuplot, VCD, others).

Supported hardware

Saleae Logic.jpgNuvola OK.png
Saleae Logic
Eeelec xla esla100.jpgNuvola OK.png
EE Eleec. XLA/ESLA100
ASIX SIGMA.jpgNuvola OK.png
ASIX SIGMA
Openbench logic sniffer front.jpgNuvola OK.png
Openbench Logic Sniffer
Zeroplus Logic Cube.jpgNuvola OK.png
Zeroplus Logic Cube LAP-C
Chronovu la8 device.jpgNuvola OK.png
ChronoVu LA8
Robomotic minilogic.jpgNuvola OK.png
Robomotic MiniLogic
Cwav usbee sx.jpgNuvola Orange.png
CWAV USBee SX
Braintechnology usb lps.jpgNuvola Orange.png
Braintechnology USB-LPS
Intronix Logicport.jpgNuvola Orange.png
Intronix Logicport
Ant18e closed.jpgNuvola Orange.png
RockyLogic Ant18e
File:MSO-19.JPGNuvola Orange.png
Link Instruments MSO-19
File:Buspirate v3 front.jpgNuvola Red.png
Buspirate
Picoscope 2203 front.jpgNuvola Red.png
Pico Tech PicoScope 2203
Ikalogic scanalogic2 device with probes.jpgNuvola Red.png
Ikalogic SCANALOGIC-2 PRO
Microchip pickit2 device front.jpgNuvola Red.png
Microchip PICkit2
Minila mockup.jpgNuvola Red.png
MiniLA Mockup
Logic-shrimp-front.pngNuvola Red.png
Logic Shrimp

Sigrok stone.png Documentation

Sigrok stone.png Development

Sigrok stone.png Getting in touch

Small logic analyzer collection


Sigrok stone.png News / Events


IMPORTANT: Please note that (unless explicitly specified otherwise) all contents in this wiki (including text and images) are released under the CC-BY-SA 3.0 license. If you don't want that, please explicitly specify another free-ish license when adding pages or images to the wiki!