Logic Shrimp

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Logic Shrimp
Logic-shrimp-front.png
Status supported
Source code openbench-logic-sniffer
Channels 4
Samplerate 20MHz
Samplerate (state) ?
Triggers ?
Min/max voltage ?
Memory 256ksamples per channel
Compression ?
Website dangerousprototypes.com

The Dangerous Prototypes Logic Shrimp is a USB-based, 4-channel logic analyzer with up to 20MHz sampling rate.

The hardware design is available under a Creative Commons (CC-BY-SA) license.

See Logic Shrimp/Info for more details (such as lsusb -v output) about the device.

Hardware

The device essentially consists of a Microchip PIC microcontroller running at 20MHz, sampling each of its 4 probes into its own 256kBit (32kByte) SRAM chip. A buffer chip makes the design 5V tolerant.

Photos

Protocol

The Logic Shrimp uses the extended SUMP protocol, as used by the Openbench Logic Sniffer driver. It is thus supported in sigrok out of the box. However, the current firmware in the Logic Shrimp does not properly publish metadata according to its capabilities. In order to get valid data from it, make sure to always restrict the probes sampled to 1-4.

Resources