]> sigrok.org Git - sigrok-test.git/blame - decoder/test/spiflash/winbond_w25q80dv_chip_erase_and_writes_start.output
spiflash: Add a few Winbond W25Q80DV tests.
[sigrok-test.git] / decoder / test / spiflash / winbond_w25q80dv_chip_erase_and_writes_start.output
CommitLineData
27130f5d
UH
1149-166 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
2170-187 spiflash: bit: "No write operation in progress.
3Internal write enable latch is not set.
4Block protection bits (BP3-BP0): 0x0.
5Device is not in continuously program mode (CP mode).
6Status register writes are allowed.
7"
8170-187 spiflash: field: "Status register"
9149-187 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
10206-223 spiflash: field: "Command: Read identification (RDID)" "Command: Read identification" "Cmd: Read identification" "Cmd: RDID" "RDID"
11227-244 spiflash: field: "Manufacturer ID: 0xef"
12245-262 spiflash: field: "Memory type: 0x40"
13264-280 spiflash: field: "Device ID: 0x14"
14206-280 spiflash: rdid: "Read identification (RDID): Device = Winbond Unknown" "Read identification: Device = Winbond Unknown" "RDID: Device = Winbond Unknown" "Device = Winbond Unknown" "Winbond Unknown"
15520-537 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
16541-558 spiflash: bit: "No write operation in progress.
17Internal write enable latch is not set.
18Block protection bits (BP3-BP0): 0x0.
19Device is not in continuously program mode (CP mode).
20Status register writes are allowed.
21"
22541-558 spiflash: field: "Status register"
23520-558 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
24579-595 spiflash: wren: "Command: Write enable (WREN)" "Command: Write enable" "Cmd: Write enable" "Cmd: WREN" "WREN"
25611-628 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
26631-648 spiflash: bit: "No write operation in progress.
27Internal write enable latch is set.
28Block protection bits (BP3-BP0): 0x0.
29Device is not in continuously program mode (CP mode).
30Status register writes are allowed.
31"
32631-648 spiflash: field: "Status register"
33611-648 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
34712-729 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
35733-750 spiflash: bit: "Write operation in progress.
36Internal write enable latch is set.
37Block protection bits (BP3-BP0): 0x0.
38Device is not in continuously program mode (CP mode).
39Status register writes are allowed.
40"
41733-750 spiflash: field: "Status register"
42712-750 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
43768-786 spiflash: field: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"
44788-805 spiflash: bit: "Write operation in progress.
45Internal write enable latch is set.
46Block protection bits (BP3-BP0): 0x0.
47Device is not in continuously program mode (CP mode).
48Status register writes are allowed.
49"
50788-805 spiflash: field: "Status register"
51768-805 spiflash: rdsr: "Command: Read status register (RDSR)" "Command: Read status register" "Cmd: Read status register" "Cmd: RDSR" "RDSR"