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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
7047acc8 | 4 | * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net> |
f2cd2deb FS |
5 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> |
6 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
7 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
8 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
9 | * | |
10 | * This program is free software: you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation, either version 3 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
24 | #include <config.h> | |
a7740b06 | 25 | |
f2cd2deb | 26 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
27 | #include <string.h> |
28 | ||
f2cd2deb FS |
29 | #include "libsigrok-internal.h" |
30 | #include "protocol.h" | |
31 | ||
d466f61c GS |
32 | /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */ |
33 | #define MCU_FWFILE_FMT "kingst-la-%04x.fw" | |
34 | #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream" | |
35 | ||
36 | /* | |
37 | * List of supported devices and their features. See @ref kingst_model | |
38 | * for the fields' type and meaning. Table is sorted by EEPROM magic. | |
39 | * | |
40 | * TODO | |
41 | * - Below LA1016 properties were guessed, need verification. | |
42 | * - Add LA5016 and LA5032 devices when their EEPROM magic is known. | |
43 | * - Does LA1010 fit the driver implementation? Samplerates vary with | |
44 | * channel counts, lack of local sample memory. Most probably not. | |
45 | */ | |
46 | static const struct kingst_model models[] = { | |
47 | { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, }, | |
48 | { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, }, | |
49 | { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, }, | |
50 | { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, }, | |
51 | }; | |
f2cd2deb | 52 | |
96dc954e | 53 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 54 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
55 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
56 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
57 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
58 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
59 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
60 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 61 | |
42f6dd55 | 62 | /* |
96dc954e GS |
63 | * FPGA register addresses (base addresses when registers span multiple |
64 | * bytes, in that case data is kept in little endian format). Passed to | |
65 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
66 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
67 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
68 | * |
69 | * Unfortunately the FPGA registers change their meaning between the | |
70 | * read and write directions of access, or exclusively provide one of | |
71 | * these directions and not the other. This is an arbitrary vendor's | |
72 | * choice, there is nothing which the sigrok driver could do about it. | |
73 | * Values written to registers typically cannot get read back, neither | |
74 | * verified after writing a configuration, nor queried upon startup for | |
75 | * automatic detection of the current configuration. Neither appear to | |
76 | * be there echo registers for presence and communication checks, nor | |
77 | * version identifying registers, as far as we know. | |
42f6dd55 | 78 | */ |
96dc954e GS |
79 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
80 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
81 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
82 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
83 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
3ab60908 GS |
84 | #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */ |
85 | #define REG_UNKNOWN_30 0x30 | |
96dc954e GS |
86 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ |
87 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
88 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 89 | |
972d191b GS |
90 | /* Bit patterns to write to REG_CAPT_MODE. */ |
91 | #define CAPTMODE_TO_RAM 0x00 | |
92 | #define CAPTMODE_STREAM 0x01 | |
93 | ||
852c7d14 GS |
94 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
95 | #define RUNMODE_HALT 0x00 | |
96 | #define RUNMODE_RUN 0x03 | |
97 | ||
b711fd8e GS |
98 | /* Bit patterns when reading from REG_RUN, get run state. */ |
99 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
100 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
101 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
102 | #define RUNSTATE_POST_BIT (1UL << 3) | |
103 | ||
f2cd2deb | 104 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
105 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
106 | void *data, uint16_t wLength) | |
f2cd2deb FS |
107 | { |
108 | struct sr_usb_dev_inst *usb; | |
109 | int ret; | |
110 | ||
111 | usb = sdi->conn; | |
112 | ||
411ad77c GS |
113 | ret = libusb_control_transfer(usb->devhdl, |
114 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
115 | bRequest, wValue, wIndex, data, wLength, | |
116 | DEFAULT_TIMEOUT_MS); | |
117 | if (ret != wLength) { | |
91f73872 GS |
118 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
119 | wLength, bRequest, wValue, wIndex, | |
120 | libusb_error_name(ret)); | |
121 | sr_err("Cannot read %d bytes from USB: %s.", | |
122 | wLength, libusb_error_name(ret)); | |
286b3e13 | 123 | return SR_ERR_IO; |
f2cd2deb FS |
124 | } |
125 | ||
126 | return SR_OK; | |
127 | } | |
128 | ||
129 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
130 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
131 | void *data, uint16_t wLength) | |
f2cd2deb FS |
132 | { |
133 | struct sr_usb_dev_inst *usb; | |
134 | int ret; | |
135 | ||
136 | usb = sdi->conn; | |
137 | ||
411ad77c GS |
138 | ret = libusb_control_transfer(usb->devhdl, |
139 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
140 | bRequest, wValue, wIndex, data, wLength, | |
141 | DEFAULT_TIMEOUT_MS); | |
142 | if (ret != wLength) { | |
91f73872 GS |
143 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
144 | wLength, bRequest, wValue, wIndex, | |
145 | libusb_error_name(ret)); | |
146 | sr_err("Cannot write %d bytes to USB: %s.", | |
147 | wLength, libusb_error_name(ret)); | |
286b3e13 | 148 | return SR_ERR_IO; |
f2cd2deb FS |
149 | } |
150 | ||
151 | return SR_OK; | |
152 | } | |
153 | ||
33020165 GS |
154 | /* HACK Experiment to spot FPGA registers of interest. */ |
155 | static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi, | |
156 | const char *caption, size_t reg_lower, size_t reg_upper) | |
157 | { | |
158 | static const size_t dump_chunk_len = 16; | |
159 | ||
160 | size_t rdlen; | |
161 | uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */ | |
162 | const uint8_t *rdptr; | |
163 | int ret; | |
164 | size_t dump_addr, indent, dump_len; | |
165 | GString *txt; | |
166 | ||
167 | if (sr_log_loglevel_get() < SR_LOG_SPEW) | |
168 | return; | |
169 | ||
170 | if (!reg_lower && !reg_upper) { | |
171 | reg_lower = 0; | |
172 | reg_upper = sizeof(rdbuf); | |
173 | } | |
174 | if (reg_upper - reg_lower > sizeof(rdbuf)) | |
175 | reg_upper = sizeof(rdbuf) - reg_lower; | |
176 | ||
177 | rdlen = reg_upper - reg_lower; | |
178 | ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen); | |
179 | if (ret != SR_OK) { | |
180 | sr_err("Cannot get registers space."); | |
181 | return; | |
182 | } | |
183 | rdptr = rdbuf; | |
184 | ||
185 | sr_spew("FPGA registers dump: %s", caption ? : "for fun"); | |
186 | dump_addr = reg_lower; | |
187 | while (rdlen) { | |
188 | dump_len = rdlen; | |
189 | indent = dump_addr % dump_chunk_len; | |
190 | if (dump_len > dump_chunk_len) | |
191 | dump_len = dump_chunk_len; | |
192 | if (dump_len + indent > dump_chunk_len) | |
193 | dump_len = dump_chunk_len - indent; | |
194 | txt = sr_hexdump_new(rdptr, dump_len); | |
195 | sr_spew(" %04zx %*s%s", | |
196 | dump_addr, (int)(3 * indent), "", txt->str); | |
197 | sr_hexdump_free(txt); | |
198 | dump_addr += dump_len; | |
199 | rdptr += dump_len; | |
200 | rdlen -= dump_len; | |
201 | } | |
202 | } | |
203 | ||
d6f89d4b GS |
204 | /* |
205 | * Check the necessity for FPGA bitstream upload, because another upload | |
206 | * would take some 600ms which is undesirable after program startup. Try | |
207 | * to access some FPGA registers and check the values' plausibility. The | |
208 | * check should fail on the safe side, request another upload when in | |
209 | * doubt. A positive response (the request to continue operation with the | |
210 | * currently active bitstream) should be conservative. Accessing multiple | |
211 | * registers is considered cheap compared to the cost of bitstream upload. | |
212 | * | |
213 | * It helps though that both the vendor software and the sigrok driver | |
214 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
215 | * supported models. We don't expect to successfully communicate to the | |
216 | * device yet disagree on its protocol. Ideally we would access version | |
217 | * identifying registers for improved robustness, but are not aware of | |
218 | * any. A bitstream reload can always be forced by a power cycle. | |
219 | */ | |
220 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
221 | { | |
222 | uint8_t init_rsp; | |
3ab60908 | 223 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */ |
d6f89d4b GS |
224 | int ret; |
225 | uint16_t run_state; | |
226 | uint8_t pwm_en; | |
227 | size_t read_len; | |
d6f89d4b GS |
228 | const uint8_t *rdptr; |
229 | ||
230 | sr_dbg("Checking operation of the FPGA bitstream."); | |
33020165 | 231 | la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0); |
d6f89d4b | 232 | |
852c7d14 | 233 | init_rsp = ~0; |
d6f89d4b GS |
234 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
235 | if (ret != SR_OK || init_rsp != 0) { | |
236 | sr_dbg("FPGA init query failed, or unexpected response."); | |
237 | return SR_ERR_IO; | |
238 | } | |
239 | ||
240 | read_len = sizeof(run_state); | |
241 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
242 | if (ret != SR_OK) { | |
243 | sr_dbg("FPGA register access failed (run state)."); | |
244 | return SR_ERR_IO; | |
245 | } | |
246 | rdptr = buff; | |
247 | run_state = read_u16le_inc(&rdptr); | |
248 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
249 | if (run_state && (run_state & 0x3) != 0x1) { | |
250 | sr_dbg("Unexpected FPGA register content (run state)."); | |
251 | return SR_ERR_DATA; | |
252 | } | |
253 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
254 | sr_dbg("Unexpected FPGA register content (run state)."); | |
255 | return SR_ERR_DATA; | |
256 | } | |
257 | ||
258 | read_len = sizeof(pwm_en); | |
259 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
260 | if (ret != SR_OK) { | |
261 | sr_dbg("FPGA register access failed (PWM enable)."); | |
262 | return SR_ERR_IO; | |
263 | } | |
264 | rdptr = buff; | |
265 | pwm_en = read_u8_inc(&rdptr); | |
266 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
267 | if ((pwm_en & 0x3) != 0x0) { | |
268 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
269 | return SR_ERR_DATA; | |
270 | } | |
271 | ||
272 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
273 | return SR_OK; | |
274 | } | |
275 | ||
1ed93110 GS |
276 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
277 | const char *bitstream_fname) | |
f2cd2deb FS |
278 | { |
279 | struct drv_context *drvc; | |
280 | struct sr_usb_dev_inst *usb; | |
281 | struct sr_resource bitstream; | |
b0d0131e | 282 | uint32_t bitstream_size; |
c3d40037 HK |
283 | uint8_t buffer[sizeof(uint32_t)]; |
284 | uint8_t *wrptr; | |
f2cd2deb | 285 | uint8_t block[4096]; |
3f48ab02 FS |
286 | int len, act_len; |
287 | unsigned int pos; | |
f2cd2deb | 288 | int ret; |
b0d0131e | 289 | unsigned int zero_pad_to; |
f2cd2deb FS |
290 | |
291 | drvc = sdi->driver->context; | |
292 | usb = sdi->conn; | |
293 | ||
9de389b1 | 294 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 295 | |
411ad77c GS |
296 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
297 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 298 | if (ret != SR_OK) { |
91f73872 | 299 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
300 | return ret; |
301 | } | |
302 | ||
b0d0131e | 303 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 304 | wrptr = buffer; |
b0d0131e | 305 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
306 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
307 | if (ret != SR_OK) { | |
91f73872 | 308 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
309 | sr_resource_close(drvc->sr_ctx, &bitstream); |
310 | return ret; | |
311 | } | |
b0d0131e GS |
312 | zero_pad_to = bitstream_size; |
313 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
314 | zero_pad_to /= LA2016_EP2_PADDING; | |
315 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
316 | |
317 | pos = 0; | |
318 | while (1) { | |
3f48ab02 | 319 | if (pos < bitstream.size) { |
411ad77c GS |
320 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
321 | block, sizeof(block)); | |
3f48ab02 | 322 | if (len < 0) { |
91f73872 | 323 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 | 324 | sr_resource_close(drvc->sr_ctx, &bitstream); |
286b3e13 | 325 | return SR_ERR_IO; |
3f48ab02 FS |
326 | } |
327 | } else { | |
96dc954e | 328 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
329 | len = zero_pad_to - pos; |
330 | if ((unsigned)len > sizeof(block)) | |
331 | len = sizeof(block); | |
332 | memset(&block, 0, len); | |
f2cd2deb FS |
333 | } |
334 | if (len == 0) | |
335 | break; | |
336 | ||
852c7d14 | 337 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 338 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 339 | if (ret != 0) { |
91f73872 GS |
340 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
341 | pos, (int)len, libusb_error_name(ret)); | |
286b3e13 | 342 | ret = SR_ERR_IO; |
f2cd2deb FS |
343 | break; |
344 | } | |
345 | if (act_len != len) { | |
91f73872 GS |
346 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
347 | pos, (int)len, act_len); | |
286b3e13 | 348 | ret = SR_ERR_IO; |
f2cd2deb FS |
349 | break; |
350 | } | |
351 | pos += len; | |
352 | } | |
353 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
5eb1b63d | 354 | if (ret != SR_OK) |
f2cd2deb | 355 | return ret; |
91f73872 GS |
356 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
357 | bitstream.size); | |
f2cd2deb | 358 | |
d6f89d4b GS |
359 | return SR_OK; |
360 | } | |
361 | ||
362 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
363 | { | |
364 | int ret; | |
411ad77c | 365 | uint8_t resp; |
d6f89d4b | 366 | |
411ad77c GS |
367 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
368 | if (ret != SR_OK) { | |
91f73872 | 369 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
370 | return ret; |
371 | } | |
411ad77c | 372 | if (resp != 0) { |
91f73872 | 373 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 374 | resp); |
286b3e13 | 375 | return SR_ERR_DATA; |
3f48ab02 | 376 | } |
852c7d14 | 377 | g_usleep(30 * 1000); |
f2cd2deb | 378 | |
411ad77c GS |
379 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
380 | if (ret != SR_OK) { | |
91f73872 | 381 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
382 | return ret; |
383 | } | |
852c7d14 | 384 | g_usleep(40 * 1000); |
d6f89d4b | 385 | |
f2cd2deb FS |
386 | return SR_OK; |
387 | } | |
388 | ||
389 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
390 | { | |
f2cd2deb | 391 | int ret; |
1ed93110 | 392 | uint16_t duty_R79, duty_R56; |
3ab60908 | 393 | uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */ |
f2ad79d1 KG |
394 | uint8_t *wrptr; |
395 | ||
96dc954e | 396 | /* Clamp threshold setting to valid range for LA2016. */ |
c35baf6e GS |
397 | if (voltage > LA2016_THR_VOLTAGE_MAX) { |
398 | voltage = LA2016_THR_VOLTAGE_MAX; | |
399 | } else if (voltage < -LA2016_THR_VOLTAGE_MAX) { | |
400 | voltage = -LA2016_THR_VOLTAGE_MAX; | |
f2ad79d1 KG |
401 | } |
402 | ||
403 | /* | |
96dc954e GS |
404 | * Two PWM output channels feed one DAC which generates a bias |
405 | * voltage, which offsets the input probe's voltage level, and | |
406 | * in combination with the FPGA pins' fixed threshold result in | |
407 | * a programmable input threshold from the user's perspective. | |
408 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
409 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
410 | * uses three discrete settings. The R56 PWM varies with desired | |
411 | * thresholds and depends on the R79 PWM configuration. See the | |
412 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
413 | */ |
414 | if (voltage >= 2.9) { | |
96dc954e | 415 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 416 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 417 | } else if (voltage > -0.4) { |
96dc954e | 418 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 419 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
420 | } else { |
421 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
422 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
423 | } |
424 | ||
96dc954e | 425 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
426 | if (duty_R56 < 10) { |
427 | duty_R56 = 10; | |
1ed93110 | 428 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
429 | duty_R56 = 1100; |
430 | } | |
431 | ||
91f73872 GS |
432 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
433 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
434 | |
435 | wrptr = buf; | |
436 | write_u16le_inc(&wrptr, duty_R56); | |
437 | write_u16le_inc(&wrptr, duty_R79); | |
438 | ||
439 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 440 | if (ret != SR_OK) { |
91f73872 | 441 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
442 | return ret; |
443 | } | |
f2cd2deb FS |
444 | |
445 | return SR_OK; | |
446 | } | |
447 | ||
08a49848 GS |
448 | /* |
449 | * Communicates a channel's configuration to the device after the | |
450 | * parameters may have changed. Configuration of one channel may | |
451 | * interfere with other channels since they share FPGA registers. | |
452 | */ | |
453 | static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
f2cd2deb | 454 | { |
08a49848 | 455 | static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, }; |
86d77b75 | 456 | |
f2cd2deb | 457 | struct dev_context *devc; |
08a49848 GS |
458 | struct pwm_setting *params; |
459 | uint8_t reg_base; | |
460 | double val_f; | |
461 | uint32_t val_u; | |
462 | uint32_t period, duty; | |
463 | size_t ch; | |
f2cd2deb | 464 | int ret; |
08a49848 GS |
465 | uint8_t enable_all, enable_cfg, reg_val; |
466 | uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */ | |
c3d40037 | 467 | uint8_t *wrptr; |
f2cd2deb FS |
468 | |
469 | devc = sdi->priv; | |
08a49848 GS |
470 | if (idx >= ARRAY_SIZE(devc->pwm_setting)) |
471 | return SR_ERR_ARG; | |
472 | params = &devc->pwm_setting[idx]; | |
473 | if (idx >= ARRAY_SIZE(reg_bases)) | |
474 | return SR_ERR_ARG; | |
475 | reg_base = reg_bases[idx]; | |
f2cd2deb | 476 | |
08a49848 GS |
477 | /* |
478 | * Map application's specs to hardware register values. Do math | |
479 | * in floating point initially, but convert to u32 eventually. | |
480 | */ | |
481 | sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.", | |
482 | idx, params->enabled ? 1 : 0, params->freq, params->duty); | |
483 | val_f = PWM_CLOCK; | |
484 | val_f /= params->freq; | |
485 | val_u = val_f; | |
486 | period = val_u; | |
487 | val_f = period; | |
488 | val_f *= params->duty; | |
489 | val_f /= 100.0; | |
490 | val_f += 0.5; | |
491 | val_u = val_f; | |
492 | duty = val_u; | |
493 | sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.", | |
494 | (unsigned)reg_base, (unsigned)period, (unsigned)duty); | |
495 | ||
496 | /* Get the "enabled" state of all supported PWM channels. */ | |
497 | enable_all = 0; | |
498 | for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) { | |
499 | if (!devc->pwm_setting[ch].enabled) | |
500 | continue; | |
501 | enable_all |= 1U << ch; | |
f2cd2deb | 502 | } |
08a49848 GS |
503 | enable_cfg = 1U << idx; |
504 | sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.", | |
505 | enable_all, enable_cfg); | |
f2cd2deb | 506 | |
08a49848 GS |
507 | /* |
508 | * Disable the to-get-configured channel before its parameters | |
509 | * will change. Or disable and exit when the channel is supposed | |
510 | * to get turned off. | |
511 | */ | |
512 | sr_spew("PWM config, disabling before param change."); | |
513 | reg_val = enable_all & ~enable_cfg; | |
514 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
515 | ®_val, sizeof(reg_val)); | |
f2cd2deb | 516 | if (ret != SR_OK) { |
08a49848 | 517 | sr_err("Cannot adjust PWM enabled state."); |
f2cd2deb FS |
518 | return ret; |
519 | } | |
08a49848 GS |
520 | if (!params->enabled) |
521 | return SR_OK; | |
86d77b75 | 522 | |
08a49848 GS |
523 | /* Write register values to device. */ |
524 | sr_spew("PWM config, sending new parameters."); | |
525 | wrptr = buf; | |
526 | write_u32le_inc(&wrptr, period); | |
527 | write_u32le_inc(&wrptr, duty); | |
528 | ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf); | |
529 | if (ret != SR_OK) { | |
530 | sr_err("Cannot change PWM parameters."); | |
f2cd2deb | 531 | return ret; |
08a49848 | 532 | } |
f2cd2deb | 533 | |
08a49848 GS |
534 | /* Enable configured channel after write completion. */ |
535 | sr_spew("PWM config, enabling after param change."); | |
536 | reg_val = enable_all | enable_cfg; | |
537 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
538 | ®_val, sizeof(reg_val)); | |
539 | if (ret != SR_OK) { | |
540 | sr_err("Cannot adjust PWM enabled state."); | |
f2cd2deb | 541 | return ret; |
08a49848 | 542 | } |
f2cd2deb FS |
543 | |
544 | return SR_OK; | |
545 | } | |
546 | ||
4276ca94 | 547 | static uint32_t get_channels_mask(const struct sr_dev_inst *sdi) |
ea436ba7 | 548 | { |
4276ca94 | 549 | uint32_t channels; |
ea436ba7 GS |
550 | GSList *l; |
551 | struct sr_channel *ch; | |
552 | ||
553 | channels = 0; | |
554 | for (l = sdi->channels; l; l = l->next) { | |
555 | ch = l->data; | |
556 | if (ch->type != SR_CHANNEL_LOGIC) | |
557 | continue; | |
558 | if (!ch->enabled) | |
559 | continue; | |
560 | channels |= 1UL << ch->index; | |
561 | } | |
562 | ||
563 | return channels; | |
564 | } | |
565 | ||
f2cd2deb FS |
566 | static int set_trigger_config(const struct sr_dev_inst *sdi) |
567 | { | |
568 | struct dev_context *devc; | |
569 | struct sr_trigger *trigger; | |
edb13f41 | 570 | struct trigger_cfg { |
972d191b GS |
571 | uint32_t channels; /* Actually: Enabled channels? */ |
572 | uint32_t enabled; /* Actually: Triggering channels? */ | |
edb13f41 GS |
573 | uint32_t level; |
574 | uint32_t high_or_falling; | |
575 | } cfg; | |
f2cd2deb FS |
576 | GSList *stages; |
577 | GSList *channel; | |
578 | struct sr_trigger_stage *stage1; | |
579 | struct sr_trigger_match *match; | |
4276ca94 | 580 | uint32_t ch_mask; |
f2cd2deb | 581 | int ret; |
3ab60908 | 582 | uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */ |
c3d40037 | 583 | uint8_t *wrptr; |
f2cd2deb FS |
584 | |
585 | devc = sdi->priv; | |
586 | trigger = sr_session_trigger_get(sdi->session); | |
587 | ||
588 | memset(&cfg, 0, sizeof(cfg)); | |
589 | ||
ea436ba7 | 590 | cfg.channels = get_channels_mask(sdi); |
f2cd2deb FS |
591 | |
592 | if (trigger && trigger->stages) { | |
593 | stages = trigger->stages; | |
594 | stage1 = stages->data; | |
595 | if (stages->next) { | |
596 | sr_err("Only one trigger stage supported for now."); | |
286b3e13 | 597 | return SR_ERR_ARG; |
f2cd2deb FS |
598 | } |
599 | channel = stage1->matches; | |
600 | while (channel) { | |
601 | match = channel->data; | |
cf057ac4 | 602 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
603 | |
604 | switch (match->match) { | |
605 | case SR_TRIGGER_ZERO: | |
606 | cfg.level |= ch_mask; | |
607 | cfg.high_or_falling &= ~ch_mask; | |
608 | break; | |
609 | case SR_TRIGGER_ONE: | |
610 | cfg.level |= ch_mask; | |
611 | cfg.high_or_falling |= ch_mask; | |
612 | break; | |
613 | case SR_TRIGGER_RISING: | |
614 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 615 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 616 | return SR_ERR_ARG; |
f2cd2deb FS |
617 | } |
618 | cfg.level &= ~ch_mask; | |
619 | cfg.high_or_falling &= ~ch_mask; | |
620 | break; | |
621 | case SR_TRIGGER_FALLING: | |
622 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 623 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 624 | return SR_ERR_ARG; |
f2cd2deb FS |
625 | } |
626 | cfg.level &= ~ch_mask; | |
627 | cfg.high_or_falling |= ch_mask; | |
628 | break; | |
629 | default: | |
91f73872 | 630 | sr_err("Unknown trigger condition."); |
286b3e13 | 631 | return SR_ERR_ARG; |
f2cd2deb FS |
632 | } |
633 | cfg.enabled |= ch_mask; | |
634 | channel = channel->next; | |
635 | } | |
636 | } | |
91f73872 | 637 | sr_dbg("Set trigger config: " |
972d191b | 638 | "enabled-channels 0x%04x, triggering-channels 0x%04x, " |
91f73872 GS |
639 | "level-triggered 0x%04x, high/falling 0x%04x.", |
640 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 641 | |
cf057ac4 | 642 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 643 | |
c3d40037 HK |
644 | wrptr = buf; |
645 | write_u32le_inc(&wrptr, cfg.channels); | |
646 | write_u32le_inc(&wrptr, cfg.enabled); | |
647 | write_u32le_inc(&wrptr, cfg.level); | |
648 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
649 | /* TODO |
650 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
651 | * register offset, nor the transfer length. Is it a channels | |
652 | * count that is relevant for 16 and 32 channel models? Is it | |
653 | * an obsolete experiment? | |
654 | */ | |
42f6dd55 | 655 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 656 | if (ret != SR_OK) { |
91f73872 | 657 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
658 | return ret; |
659 | } | |
660 | ||
661 | return SR_OK; | |
662 | } | |
663 | ||
664 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
665 | { | |
666 | struct dev_context *devc; | |
d8fbfcd9 | 667 | uint64_t min_samplerate, eff_samplerate; |
adab4d91 | 668 | uint16_t divider_u16; |
a38f0f5e | 669 | uint64_t limit_samples; |
adab4d91 GS |
670 | uint64_t pre_trigger_samples; |
671 | uint64_t pre_trigger_memory; | |
672 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 673 | uint8_t *wrptr; |
adab4d91 | 674 | int ret; |
f2cd2deb FS |
675 | |
676 | devc = sdi->priv; | |
f2cd2deb | 677 | |
edc0b015 | 678 | if (devc->samplerate > devc->model->samplerate) { |
91f73872 | 679 | sr_err("Too high a sample rate: %" PRIu64 ".", |
edc0b015 | 680 | devc->samplerate); |
ea436ba7 GS |
681 | return SR_ERR_ARG; |
682 | } | |
d8fbfcd9 GS |
683 | min_samplerate = devc->model->samplerate; |
684 | min_samplerate /= 65536; | |
edc0b015 | 685 | if (devc->samplerate < min_samplerate) { |
ea436ba7 | 686 | sr_err("Too low a sample rate: %" PRIu64 ".", |
edc0b015 | 687 | devc->samplerate); |
ea436ba7 | 688 | return SR_ERR_ARG; |
f2cd2deb | 689 | } |
edc0b015 | 690 | divider_u16 = devc->model->samplerate / devc->samplerate; |
d8fbfcd9 | 691 | eff_samplerate = devc->model->samplerate / divider_u16; |
f2cd2deb | 692 | |
a38f0f5e GS |
693 | ret = sr_sw_limits_get_remain(&devc->sw_limits, |
694 | &limit_samples, NULL, NULL, NULL); | |
695 | if (ret != SR_OK) { | |
696 | sr_err("Cannot get acquisition limits."); | |
697 | return ret; | |
f2cd2deb | 698 | } |
a38f0f5e | 699 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { |
d8fbfcd9 GS |
700 | sr_warn("Too high a sample depth: %" PRIu64 ", capping.", |
701 | limit_samples); | |
702 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
a38f0f5e | 703 | } |
d8fbfcd9 GS |
704 | if (limit_samples == 0) { |
705 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
706 | sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.", | |
707 | limit_samples); | |
ea436ba7 | 708 | } |
f2cd2deb | 709 | |
adab4d91 GS |
710 | /* |
711 | * The acquisition configuration communicates "pre-trigger" | |
712 | * specs in several formats. sigrok users provide a percentage | |
713 | * (0-100%), which translates to a pre-trigger samples count | |
714 | * (assuming that a total samples count limit was specified). | |
715 | * The device supports hardware compression, which depends on | |
716 | * slowly changing input data to be effective. Fast changing | |
717 | * input data may occupy more space in sample memory than its | |
718 | * uncompressed form would. This is why a third parameter can | |
719 | * limit the amount of sample memory to use for pre-trigger | |
720 | * data. Only the upper 24 bits of that memory size spec get | |
721 | * communicated to the device (written to its FPGA register). | |
d8fbfcd9 GS |
722 | * |
723 | * TODO Determine whether the pre-trigger memory size gets | |
724 | * specified in samples or in bytes. A previous implementation | |
725 | * suggests bytes but this is suspicious when every other spec | |
726 | * is in terms of samples. | |
adab4d91 | 727 | */ |
d8fbfcd9 GS |
728 | if (devc->trigger_involved) { |
729 | pre_trigger_samples = limit_samples; | |
730 | pre_trigger_samples *= devc->capture_ratio; | |
731 | pre_trigger_samples /= 100; | |
732 | pre_trigger_memory = devc->model->memory_bits; | |
733 | pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024); | |
734 | pre_trigger_memory /= 8; /* devc->model->channel_count ? */ | |
735 | pre_trigger_memory *= devc->capture_ratio; | |
736 | pre_trigger_memory /= 100; | |
737 | } else { | |
738 | sr_dbg("No trigger setup, skipping pre-trigger config."); | |
739 | pre_trigger_samples = 1; | |
740 | pre_trigger_memory = 0; | |
741 | } | |
742 | /* Ensure non-zero value after LSB shift out in HW reg. */ | |
743 | if (pre_trigger_memory < 0x100) { | |
744 | pre_trigger_memory = 0x100; | |
745 | } | |
f2cd2deb | 746 | |
adab4d91 | 747 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", |
d8fbfcd9 | 748 | eff_samplerate / SR_KHZ(1), limit_samples); |
adab4d91 GS |
749 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", |
750 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 751 | |
b1a17c1a GS |
752 | /* |
753 | * The acquisition configuration occupies a total of 16 bytes: | |
754 | * - A 34bit total samples count limit (up to 10 billions) that | |
755 | * is kept in a 40bit register. | |
756 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
757 | * in another 40bit register. | |
758 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
759 | * the upper 24bits are kept in an FPGA register. | |
760 | * - A 16bit clock divider which gets applied to the maximum | |
761 | * samplerate of the device. | |
762 | * - An 8bit register of unknown meaning. Currently always 0. | |
763 | */ | |
c3d40037 | 764 | wrptr = buf; |
a38f0f5e | 765 | write_u40le_inc(&wrptr, limit_samples); |
b1a17c1a GS |
766 | write_u40le_inc(&wrptr, pre_trigger_samples); |
767 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 768 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 769 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 770 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 771 | if (ret != SR_OK) { |
91f73872 | 772 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
773 | return ret; |
774 | } | |
775 | ||
776 | return SR_OK; | |
777 | } | |
778 | ||
96dc954e GS |
779 | /* |
780 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
781 | * of interest: | |
782 | * bit 0: value 1 = idle | |
783 | * bit 1: value 1 = writing to SDRAM | |
784 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
785 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
786 | * The meaning of other bit fields is unknown. | |
7601dca7 | 787 | * |
96dc954e | 788 | * Typical values in order of appearance during execution: |
b711fd8e GS |
789 | * 0x85e1: idle, no acquisition pending |
790 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
791 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
792 | * 0x85e2: pre-sampling, samples before the trigger position, |
793 | * when capture ratio > 0% | |
b711fd8e GS |
794 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
795 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
796 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
797 | * (whilst sampling continuously) | |
b711fd8e GS |
798 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
799 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 800 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
801 | * IDLE clear, TRGD set, POST set; DRAM don't care |
802 | * "Triggered and in post, not idle yet." | |
96dc954e | 803 | * 0x85ed: idle |
b711fd8e GS |
804 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
805 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 806 | */ |
b711fd8e GS |
807 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
808 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
809 | static const uint16_t runstate_mask_step = | |
810 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
811 | static const uint16_t runstate_patt_pre_trig = 0; | |
812 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
813 | static const uint16_t runstate_patt_post_trig = | |
814 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
815 | ||
f2cd2deb FS |
816 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
817 | { | |
21d68fd9 GS |
818 | static uint16_t previous_state; |
819 | ||
f2cd2deb | 820 | int ret; |
21d68fd9 | 821 | uint16_t state; |
3ab60908 | 822 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */ |
21d68fd9 GS |
823 | const uint8_t *rdptr; |
824 | const char *label; | |
f2cd2deb | 825 | |
411ad77c GS |
826 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
827 | if (ret != SR_OK) { | |
91f73872 | 828 | sr_err("Cannot read run state."); |
f2cd2deb FS |
829 | return ret; |
830 | } | |
21d68fd9 GS |
831 | rdptr = buff; |
832 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 833 | |
96dc954e GS |
834 | /* |
835 | * Avoid flooding the log, only dump values as they change. | |
836 | * The routine is called about every 50ms. | |
7601dca7 | 837 | */ |
b711fd8e GS |
838 | if (state == previous_state) |
839 | return state; | |
840 | ||
841 | previous_state = state; | |
842 | label = NULL; | |
843 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
844 | label = "idle"; | |
845 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
846 | label = "pre-trigger sampling"; | |
847 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
848 | label = "sampling, waiting for trigger"; | |
849 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
850 | label = "post-trigger sampling"; | |
851 | if (label && *label) | |
852 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
853 | else | |
854 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
855 | |
856 | return state; | |
857 | } | |
858 | ||
cf057ac4 | 859 | static int la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
860 | { |
861 | uint16_t state; | |
862 | ||
863 | state = run_state(sdi); | |
b711fd8e | 864 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
c34f4a89 GS |
865 | return 1; |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
871 | { |
872 | int ret; | |
873 | ||
411ad77c GS |
874 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
875 | if (ret != SR_OK) { | |
c34f4a89 | 876 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
877 | return ret; |
878 | } | |
879 | ||
880 | return SR_OK; | |
881 | } | |
882 | ||
883 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
884 | { | |
885 | struct dev_context *devc; | |
886 | int ret; | |
3ab60908 | 887 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ |
c3d40037 | 888 | const uint8_t *rdptr; |
f2cd2deb FS |
889 | |
890 | devc = sdi->priv; | |
891 | ||
411ad77c GS |
892 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
893 | if (ret != SR_OK) { | |
91f73872 | 894 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
895 | return ret; |
896 | } | |
c3d40037 HK |
897 | |
898 | rdptr = buf; | |
899 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
900 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
901 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 902 | |
cf057ac4 | 903 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
904 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
905 | devc->info.n_rep_packets_before_trigger, | |
906 | devc->info.n_rep_packets_before_trigger, | |
907 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 908 | |
038e65c1 GS |
909 | if (devc->info.n_rep_packets % devc->packets_per_chunk) { |
910 | sr_warn("Unexpected packets count %lu, not a multiple of %lu.", | |
852c7d14 | 911 | (unsigned long)devc->info.n_rep_packets, |
038e65c1 | 912 | (unsigned long)devc->packets_per_chunk); |
91f73872 | 913 | } |
f2cd2deb FS |
914 | |
915 | return SR_OK; | |
916 | } | |
917 | ||
d466f61c | 918 | SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, |
91aa0f04 | 919 | struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload) |
f2cd2deb | 920 | { |
d466f61c | 921 | struct dev_context *devc; |
91aa0f04 GS |
922 | uint16_t pid; |
923 | char *fw; | |
d466f61c GS |
924 | int ret; |
925 | ||
926 | devc = sdi ? sdi->priv : NULL; | |
91aa0f04 GS |
927 | if (!devc || !devc->usb_pid) |
928 | return SR_ERR_ARG; | |
929 | pid = devc->usb_pid; | |
d466f61c | 930 | |
91aa0f04 GS |
931 | fw = g_strdup_printf(MCU_FWFILE_FMT, pid); |
932 | sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw); | |
933 | devc->mcu_firmware = g_strdup(fw); | |
d466f61c | 934 | |
91aa0f04 GS |
935 | if (skip_upload) |
936 | ret = SR_OK; | |
937 | else | |
938 | ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw); | |
939 | g_free(fw); | |
940 | if (ret != SR_OK) | |
d466f61c | 941 | return ret; |
d466f61c GS |
942 | |
943 | return SR_OK; | |
f2cd2deb FS |
944 | } |
945 | ||
9270f8f4 GS |
946 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi, |
947 | double voltage) | |
f2cd2deb | 948 | { |
f2cd2deb FS |
949 | int ret; |
950 | uint8_t cmd; | |
951 | ||
9270f8f4 | 952 | ret = set_threshold_voltage(sdi, voltage); |
f2cd2deb FS |
953 | if (ret != SR_OK) |
954 | return ret; | |
955 | ||
972d191b | 956 | cmd = CAPTMODE_TO_RAM; |
411ad77c GS |
957 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
958 | if (ret != SR_OK) { | |
91f73872 | 959 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
960 | return ret; |
961 | } | |
962 | ||
963 | ret = set_trigger_config(sdi); | |
964 | if (ret != SR_OK) | |
965 | return ret; | |
966 | ||
967 | ret = set_sample_config(sdi); | |
968 | if (ret != SR_OK) | |
969 | return ret; | |
970 | ||
971 | return SR_OK; | |
972 | } | |
973 | ||
974 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
975 | { | |
3ebc1cb2 GS |
976 | int ret; |
977 | ||
852c7d14 | 978 | ret = set_run_mode(sdi, RUNMODE_RUN); |
3ebc1cb2 GS |
979 | if (ret != SR_OK) |
980 | return ret; | |
981 | ||
982 | return SR_OK; | |
f2cd2deb FS |
983 | } |
984 | ||
3ebc1cb2 | 985 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 986 | { |
3ebc1cb2 GS |
987 | int ret; |
988 | ||
852c7d14 | 989 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
990 | if (ret != SR_OK) |
991 | return ret; | |
992 | ||
993 | return SR_OK; | |
f2cd2deb FS |
994 | } |
995 | ||
996 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
997 | { | |
3ebc1cb2 GS |
998 | int ret; |
999 | struct dev_context *devc; | |
1000 | ||
1001 | ret = la2016_stop_acquisition(sdi); | |
1002 | if (ret != SR_OK) | |
1003 | return ret; | |
1004 | ||
1005 | devc = sdi ? sdi->priv : NULL; | |
1006 | if (devc && devc->transfer) | |
1007 | libusb_cancel_transfer(devc->transfer); | |
1008 | ||
1009 | return SR_OK; | |
f2cd2deb FS |
1010 | } |
1011 | ||
cf057ac4 | 1012 | static int la2016_start_download(const struct sr_dev_inst *sdi, |
1ed93110 | 1013 | libusb_transfer_cb_fn cb) |
f2cd2deb FS |
1014 | { |
1015 | struct dev_context *devc; | |
1016 | struct sr_usb_dev_inst *usb; | |
1017 | int ret; | |
3ab60908 | 1018 | uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */ |
c3d40037 | 1019 | uint8_t *wrptr; |
f2cd2deb FS |
1020 | uint32_t to_read; |
1021 | uint8_t *buffer; | |
1022 | ||
1023 | devc = sdi->priv; | |
1024 | usb = sdi->conn; | |
1025 | ||
411ad77c GS |
1026 | ret = get_capture_info(sdi); |
1027 | if (ret != SR_OK) | |
f2cd2deb FS |
1028 | return ret; |
1029 | ||
038e65c1 GS |
1030 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets; |
1031 | devc->n_transfer_packets_to_read /= devc->packets_per_chunk; | |
1032 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read; | |
1033 | devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
1034 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
1035 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
1036 | ||
91f73872 | 1037 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 1038 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 1039 | |
411ad77c GS |
1040 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1041 | if (ret != SR_OK) { | |
91f73872 | 1042 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
1043 | return ret; |
1044 | } | |
91f73872 GS |
1045 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
1046 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
1047 | wrptr = wrbuf; |
1048 | write_u32le_inc(&wrptr, devc->read_pos); | |
1049 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
1050 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
1051 | if (ret != SR_OK) { | |
91f73872 | 1052 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
1053 | return ret; |
1054 | } | |
411ad77c GS |
1055 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
1056 | if (ret != SR_OK) { | |
91f73872 | 1057 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
1058 | return ret; |
1059 | } | |
1060 | ||
96dc954e GS |
1061 | /* |
1062 | * Pick a buffer size for all USB transfers. The buffer size | |
1063 | * must be a multiple of the endpoint packet size. And cannot | |
1064 | * exceed a maximum value. | |
1065 | */ | |
f2cd2deb | 1066 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
1067 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
1068 | to_read = LA2016_USB_BUFSZ; | |
418dfd7e GS |
1069 | to_read += LA2016_EP6_PKTSZ - 1; |
1070 | to_read /= LA2016_EP6_PKTSZ; | |
1071 | to_read *= LA2016_EP6_PKTSZ; | |
f2cd2deb FS |
1072 | buffer = g_try_malloc(to_read); |
1073 | if (!buffer) { | |
91f73872 GS |
1074 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
1075 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
1076 | return SR_ERR_MALLOC; |
1077 | } | |
1078 | ||
1079 | devc->transfer = libusb_alloc_transfer(0); | |
852c7d14 GS |
1080 | libusb_fill_bulk_transfer(devc->transfer, |
1081 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
411ad77c | 1082 | buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 1083 | |
411ad77c GS |
1084 | ret = libusb_submit_transfer(devc->transfer); |
1085 | if (ret != 0) { | |
91f73872 | 1086 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
1087 | libusb_free_transfer(devc->transfer); |
1088 | devc->transfer = NULL; | |
1089 | g_free(buffer); | |
286b3e13 | 1090 | return SR_ERR_IO; |
f2cd2deb FS |
1091 | } |
1092 | ||
1093 | return SR_OK; | |
1094 | } | |
1095 | ||
480efba2 GS |
1096 | /* |
1097 | * A chunk (received via USB) contains a number of transfers (USB length | |
1098 | * divided by 16) which contain a number of packets (5 per transfer) which | |
1099 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
1100 | */ | |
dfac9592 | 1101 | static void send_chunk(struct sr_dev_inst *sdi, |
480efba2 | 1102 | const uint8_t *packets, size_t num_xfers) |
dfac9592 GS |
1103 | { |
1104 | struct dev_context *devc; | |
480efba2 | 1105 | size_t num_pkts; |
dfac9592 | 1106 | const uint8_t *rp; |
4276ca94 | 1107 | uint32_t sample_value; |
480efba2 GS |
1108 | size_t repetitions; |
1109 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1110 | |
1111 | devc = sdi->priv; | |
1112 | ||
a38f0f5e GS |
1113 | /* Ignore incoming USB data after complete sample data download. */ |
1114 | if (devc->download_finished) | |
1115 | return; | |
dfac9592 | 1116 | |
cf057ac4 | 1117 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
a38f0f5e | 1118 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1119 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1120 | } |
1121 | ||
4276ca94 | 1122 | sample_value = 0; |
dfac9592 | 1123 | rp = packets; |
480efba2 | 1124 | while (num_xfers--) { |
038e65c1 | 1125 | num_pkts = devc->packets_per_chunk; |
480efba2 | 1126 | while (num_pkts--) { |
dfac9592 | 1127 | |
4276ca94 GS |
1128 | /* TODO Verify 32channel layout. */ |
1129 | if (devc->model->channel_count == 32) | |
1130 | sample_value = read_u32le_inc(&rp); | |
1131 | else if (devc->model->channel_count == 16) | |
1132 | sample_value = read_u16le_inc(&rp); | |
dfac9592 | 1133 | repetitions = read_u8_inc(&rp); |
dfac9592 | 1134 | |
dfac9592 | 1135 | devc->total_samples += repetitions; |
480efba2 | 1136 | |
4276ca94 | 1137 | write_u32le(sample_buff, sample_value); |
a38f0f5e GS |
1138 | feed_queue_logic_submit(devc->feed_queue, |
1139 | sample_buff, repetitions); | |
1140 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1141 | repetitions); | |
480efba2 | 1142 | |
cf057ac4 GS |
1143 | if (devc->trigger_involved && !devc->trigger_marked) { |
1144 | if (!--devc->n_reps_until_trigger) { | |
a38f0f5e | 1145 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1146 | devc->trigger_marked = TRUE; |
91f73872 | 1147 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 | 1148 | devc->total_samples, |
edc0b015 | 1149 | (double)devc->total_samples / devc->samplerate * 1e3); |
dfac9592 GS |
1150 | } |
1151 | } | |
1152 | } | |
1153 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1154 | } | |
a38f0f5e GS |
1155 | |
1156 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { | |
1157 | sr_dbg("Acquisition limit reached."); | |
1158 | devc->download_finished = TRUE; | |
1159 | } | |
1160 | if (devc->download_finished) { | |
1161 | sr_dbg("Download finished, flushing session feed queue."); | |
1162 | feed_queue_logic_flush(devc->feed_queue); | |
dfac9592 | 1163 | } |
a38f0f5e | 1164 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); |
dfac9592 GS |
1165 | } |
1166 | ||
1167 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1168 | { | |
1169 | struct sr_dev_inst *sdi; | |
1170 | struct dev_context *devc; | |
1171 | struct sr_usb_dev_inst *usb; | |
a38f0f5e | 1172 | size_t num_xfers; |
dfac9592 GS |
1173 | int ret; |
1174 | ||
1175 | sdi = transfer->user_data; | |
1176 | devc = sdi->priv; | |
1177 | usb = sdi->conn; | |
1178 | ||
1179 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 1180 | libusb_error_name(transfer->status), transfer->actual_length); |
a38f0f5e GS |
1181 | /* |
1182 | * Implementation detail: A USB transfer timeout is not fatal | |
1183 | * here. We just process whatever was received, empty input is | |
1184 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1185 | * or exhausting the device's captured data will complete the | |
1186 | * sample data download. | |
1187 | */ | |
1188 | num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH; | |
1189 | send_chunk(sdi, transfer->buffer, num_xfers); | |
dfac9592 GS |
1190 | |
1191 | devc->n_bytes_to_read -= transfer->actual_length; | |
1192 | if (devc->n_bytes_to_read) { | |
1193 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
1194 | /* |
1195 | * Determine read size for the next USB transfer. Make | |
1196 | * the buffer size a multiple of the endpoint packet | |
1197 | * size. Don't exceed a maximum value. | |
1198 | */ | |
dfac9592 GS |
1199 | if (to_read >= LA2016_USB_BUFSZ) |
1200 | to_read = LA2016_USB_BUFSZ; | |
418dfd7e GS |
1201 | to_read += LA2016_EP6_PKTSZ - 1; |
1202 | to_read /= LA2016_EP6_PKTSZ; | |
1203 | to_read *= LA2016_EP6_PKTSZ; | |
852c7d14 GS |
1204 | libusb_fill_bulk_transfer(transfer, |
1205 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1206 | transfer->buffer, to_read, | |
dfac9592 GS |
1207 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); |
1208 | ||
411ad77c GS |
1209 | ret = libusb_submit_transfer(transfer); |
1210 | if (ret == 0) | |
dfac9592 | 1211 | return; |
91f73872 GS |
1212 | sr_err("Cannot submit another USB transfer: %s.", |
1213 | libusb_error_name(ret)); | |
dfac9592 GS |
1214 | } |
1215 | ||
1216 | g_free(transfer->buffer); | |
1217 | libusb_free_transfer(transfer); | |
cf057ac4 | 1218 | devc->download_finished = TRUE; |
dfac9592 GS |
1219 | } |
1220 | ||
1221 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1222 | { | |
1223 | const struct sr_dev_inst *sdi; | |
1224 | struct dev_context *devc; | |
1225 | struct drv_context *drvc; | |
1226 | struct timeval tv; | |
a38f0f5e | 1227 | int ret; |
dfac9592 GS |
1228 | |
1229 | (void)fd; | |
1230 | (void)revents; | |
1231 | ||
1232 | sdi = cb_data; | |
1233 | devc = sdi->priv; | |
1234 | drvc = sdi->driver->context; | |
1235 | ||
a38f0f5e GS |
1236 | /* |
1237 | * Wait for the acquisition to complete in hardware. | |
1238 | * Periodically check a potentially configured msecs timeout. | |
1239 | */ | |
cf057ac4 GS |
1240 | if (!devc->completion_seen) { |
1241 | if (!la2016_is_idle(sdi)) { | |
a38f0f5e GS |
1242 | if (sr_sw_limits_check(&devc->sw_limits)) { |
1243 | devc->sw_limits.limit_msec = 0; | |
1244 | sr_dbg("Limit reached. Stopping acquisition."); | |
1245 | la2016_stop_acquisition(sdi); | |
1246 | } | |
96dc954e | 1247 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1248 | return TRUE; |
1249 | } | |
a38f0f5e GS |
1250 | sr_dbg("Acquisition completion seen (hardware)."); |
1251 | devc->sw_limits.limit_msec = 0; | |
cf057ac4 GS |
1252 | devc->completion_seen = TRUE; |
1253 | devc->download_finished = FALSE; | |
1254 | devc->trigger_marked = FALSE; | |
dfac9592 | 1255 | devc->total_samples = 0; |
a38f0f5e | 1256 | |
33020165 GS |
1257 | la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0); |
1258 | ||
a38f0f5e GS |
1259 | /* Initiate the download of acquired sample data. */ |
1260 | std_session_send_df_frame_begin(sdi); | |
96a405ab | 1261 | devc->frame_begin_sent = TRUE; |
a38f0f5e GS |
1262 | ret = la2016_start_download(sdi, receive_transfer); |
1263 | if (ret != SR_OK) { | |
91f73872 | 1264 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1265 | return FALSE; |
1266 | } | |
91f73872 | 1267 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1268 | |
1269 | return TRUE; | |
1270 | } | |
1271 | ||
a38f0f5e | 1272 | /* Handle USB reception. Drives sample data download. */ |
dfac9592 GS |
1273 | tv.tv_sec = tv.tv_usec = 0; |
1274 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1275 | ||
a38f0f5e | 1276 | /* Postprocess completion of sample data download. */ |
cf057ac4 | 1277 | if (devc->download_finished) { |
91f73872 | 1278 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1279 | |
1280 | la2016_stop_acquisition(sdi); | |
a38f0f5e | 1281 | usb_source_remove(sdi->session, drvc->sr_ctx); |
dfac9592 GS |
1282 | devc->transfer = NULL; |
1283 | ||
a38f0f5e GS |
1284 | feed_queue_logic_flush(devc->feed_queue); |
1285 | feed_queue_logic_free(devc->feed_queue); | |
1286 | devc->feed_queue = NULL; | |
96a405ab GS |
1287 | if (devc->frame_begin_sent) { |
1288 | std_session_send_df_frame_end(sdi); | |
1289 | devc->frame_begin_sent = FALSE; | |
1290 | } | |
a38f0f5e GS |
1291 | std_session_send_df_end(sdi); |
1292 | ||
91f73872 | 1293 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1294 | } |
1295 | ||
1296 | return TRUE; | |
1297 | } | |
1298 | ||
d466f61c GS |
1299 | SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, |
1300 | gboolean show_message) | |
f2cd2deb | 1301 | { |
8b172e78 | 1302 | struct dev_context *devc; |
3ab60908 | 1303 | uint8_t buf[8]; /* Larger size of manuf date and device type magic. */ |
64172b16 | 1304 | size_t rdoff, rdlen; |
43d2e52f GS |
1305 | const uint8_t *rdptr; |
1306 | uint8_t date_yy, date_mm; | |
1307 | uint8_t dinv_yy, dinv_mm; | |
9de389b1 | 1308 | uint8_t magic; |
d466f61c GS |
1309 | size_t model_idx; |
1310 | const struct kingst_model *model; | |
9de389b1 | 1311 | int ret; |
f2cd2deb | 1312 | |
8b172e78 KG |
1313 | devc = sdi->priv; |
1314 | ||
96dc954e | 1315 | /* |
43d2e52f GS |
1316 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1317 | * year and month in BCD format, followed by inverted values for | |
1318 | * consistency checks. For example bytes 20 04 df fb translate | |
1319 | * to 2020-04. This information can help identify the vintage of | |
1320 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1321 | */ |
64172b16 GS |
1322 | rdoff = 0x20; |
1323 | rdlen = 4 * sizeof(uint8_t); | |
1324 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen); | |
d466f61c | 1325 | if (ret != SR_OK && !show_message) { |
64172b16 | 1326 | /* Non-fatal weak attempt during probe. Not worth logging. */ |
d466f61c GS |
1327 | sr_dbg("Cannot access EEPROM."); |
1328 | return SR_ERR_IO; | |
1329 | } else if (ret != SR_OK) { | |
64172b16 | 1330 | /* Failed attempt in regular use. Non-fatal. Worth logging. */ |
43d2e52f | 1331 | sr_err("Cannot read manufacture date in EEPROM."); |
1ed93110 | 1332 | } else { |
64172b16 GS |
1333 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1334 | GString *txt; | |
1335 | txt = sr_hexdump_new(buf, rdlen); | |
1336 | sr_spew("Manufacture date bytes %s.", txt->str); | |
1337 | sr_hexdump_free(txt); | |
1338 | } | |
43d2e52f GS |
1339 | rdptr = &buf[0]; |
1340 | date_yy = read_u8_inc(&rdptr); | |
1341 | date_mm = read_u8_inc(&rdptr); | |
1342 | dinv_yy = read_u8_inc(&rdptr); | |
1343 | dinv_mm = read_u8_inc(&rdptr); | |
1344 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1345 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1346 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1347 | } |
f2cd2deb | 1348 | |
9de389b1 | 1349 | /* |
96dc954e GS |
1350 | * Several Kingst logic analyzer devices share the same USB VID |
1351 | * and PID. The product ID determines which MCU firmware to load. | |
1352 | * The MCU firmware provides access to EEPROM content which then | |
1353 | * allows to identify the device model. Which in turn determines | |
1354 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1355 | * to get inspected. | |
9de389b1 | 1356 | * |
96dc954e GS |
1357 | * EEPROM content for model identification is kept redundantly |
1358 | * in memory. The values are stored in verbatim and in inverted | |
1359 | * form, multiple copies are kept at different offsets. Example | |
1360 | * data: | |
9de389b1 | 1361 | * |
96dc954e GS |
1362 | * magic 0x08 |
1363 | * | ~magic 0xf7 | |
1364 | * | | | |
1365 | * 08f7000008f710ef | |
1366 | * | | | |
1367 | * | ~magic backup | |
1368 | * magic backup | |
9de389b1 | 1369 | * |
96dc954e GS |
1370 | * Exclusively inspecting the magic byte appears to be sufficient, |
1371 | * other fields seem to be 'don't care'. | |
9de389b1 | 1372 | * |
96dc954e GS |
1373 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1374 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1375 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1376 | * (latest v1.3.0 PCB, perhaps others) | |
1377 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1378 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1379 | * |
96dc954e GS |
1380 | * When EEPROM content does not match the hardware configuration |
1381 | * (the board layout), the software may load but yield incorrect | |
1382 | * results (like swapped channels). The FPGA bitstream itself | |
1383 | * will authenticate with IC U10 and fail when its capabilities | |
1384 | * do not match the hardware model. An LA1016 won't become a | |
1385 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1386 | */ |
d466f61c | 1387 | devc->identify_magic = 0; |
64172b16 GS |
1388 | rdoff = 0x08; |
1389 | rdlen = 8 * sizeof(uint8_t); | |
1390 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen); | |
1391 | if (ret != SR_OK) { | |
91f73872 | 1392 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1393 | return ret; |
1394 | } | |
64172b16 GS |
1395 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1396 | GString *txt; | |
1397 | txt = sr_hexdump_new(buf, rdlen); | |
1398 | sr_spew("EEPROM magic bytes %s.", txt->str); | |
1399 | sr_hexdump_free(txt); | |
1400 | } | |
43d2e52f | 1401 | if ((buf[0] ^ buf[1]) == 0xff) { |
96dc954e | 1402 | /* Primary copy of magic passes complement check. */ |
9de389b1 | 1403 | magic = buf[0]; |
64172b16 | 1404 | sr_dbg("Using primary magic, value %d.", (int)magic); |
43d2e52f | 1405 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
96dc954e | 1406 | /* Backup copy of magic passes complement check. */ |
9de389b1 | 1407 | magic = buf[4]; |
64172b16 | 1408 | sr_dbg("Using backup magic, value %d.", (int)magic); |
43d2e52f GS |
1409 | } else { |
1410 | sr_err("Cannot find consistent device type identification."); | |
1411 | magic = 0; | |
f2cd2deb | 1412 | } |
d466f61c | 1413 | devc->identify_magic = magic; |
9de389b1 | 1414 | |
d466f61c GS |
1415 | devc->model = NULL; |
1416 | for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) { | |
1417 | model = &models[model_idx]; | |
1418 | if (model->magic != magic) | |
1419 | continue; | |
1420 | devc->model = model; | |
64172b16 GS |
1421 | sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.", |
1422 | model->name, model->channel_count, | |
1423 | model->samplerate / SR_MHZ(1)); | |
d466f61c GS |
1424 | devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT, |
1425 | model->fpga_stem); | |
d466f61c | 1426 | sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream); |
d6f89d4b GS |
1427 | break; |
1428 | } | |
d466f61c | 1429 | if (!devc->model) { |
91f73872 | 1430 | sr_err("Cannot identify as one of the supported models."); |
286b3e13 | 1431 | return SR_ERR_DATA; |
3f48ab02 | 1432 | } |
f2cd2deb | 1433 | |
d466f61c GS |
1434 | return SR_OK; |
1435 | } | |
1436 | ||
6d53e949 | 1437 | SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) |
d466f61c GS |
1438 | { |
1439 | struct dev_context *devc; | |
1440 | const char *bitstream_fn; | |
1441 | int ret; | |
1442 | uint16_t state; | |
1443 | ||
1444 | devc = sdi->priv; | |
1445 | bitstream_fn = devc ? devc->fpga_bitstream : ""; | |
1446 | ||
1447 | ret = check_fpga_bitstream(sdi); | |
1448 | if (ret != SR_OK) { | |
d6f89d4b GS |
1449 | ret = upload_fpga_bitstream(sdi, bitstream_fn); |
1450 | if (ret != SR_OK) { | |
1451 | sr_err("Cannot upload FPGA bitstream."); | |
1452 | return ret; | |
1453 | } | |
1454 | } | |
1455 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1456 | if (ret != SR_OK) { |
d6f89d4b | 1457 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1458 | return ret; |
1459 | } | |
1460 | ||
f2cd2deb | 1461 | state = run_state(sdi); |
44947217 GS |
1462 | if ((state & 0xfff0) != 0x85e0) { |
1463 | sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state); | |
9de389b1 | 1464 | } |
f2cd2deb | 1465 | |
6d53e949 GS |
1466 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1467 | if (ret != SR_OK) { | |
91f73872 | 1468 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1469 | return ret; |
1470 | } | |
9de389b1 | 1471 | |
91f73872 | 1472 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1473 | |
6d53e949 GS |
1474 | return SR_OK; |
1475 | } | |
1476 | ||
6d53e949 | 1477 | SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
1478 | { |
1479 | int ret; | |
1480 | ||
6d53e949 GS |
1481 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0); |
1482 | if (ret != SR_OK) { | |
91f73872 | 1483 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1484 | return ret; |
1485 | } | |
1486 | ||
1487 | return SR_OK; | |
1488 | } | |
08a49848 GS |
1489 | |
1490 | SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
1491 | { | |
1492 | return set_pwm_config(sdi, idx); | |
1493 | } |