[libsigrok.git] / src / hardware / dslogic / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

/*
 * This should be larger than the FPGA bitstream image so that it'll get
 * uploaded in one big operation. There seem to be issues when uploading
 * it in chunks.
 */
#define FW_BUFSIZE (1024 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
{
	struct sr_usb_dev_inst *usb;
	int ret;
	const uint8_t value = (vth / 5.0) * 255;
	const uint16_t cmd = value | (DS_ADDR_VTH << 8);

	usb = sdi->conn;

	/* Send the control command. */
	ret = libusb_control_transfer(usb->devhdl,
			LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
			DS_CMD_WR_REG, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), 3000);
	if (ret < 0) {
		sr_err("Unable to send VTH command: %s.",
		libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *name)
{
	uint64_t sum;
	struct sr_resource bitstream;
	struct drv_context *drvc;
	struct sr_usb_dev_inst *usb;
	unsigned char *buf;
	ssize_t chunksize;
	int transferred;
	int result, ret;
	const uint8_t cmd[3] = {0, 0, 0};

	drvc = sdi->driver->context;
	usb = sdi->conn;

	sr_dbg("Uploading FPGA firmware '%s'.", name);

	result = sr_resource_open(drvc->sr_ctx, &bitstream,
			SR_RESOURCE_FIRMWARE, name);
	if (result != SR_OK)
		return result;

	/* Tell the device firmware is coming. */
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		sr_resource_close(drvc->sr_ctx, &bitstream);
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	buf = g_malloc(FW_BUFSIZE);
	sum = 0;
	result = SR_OK;
	while (1) {
		chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
				buf, FW_BUFSIZE);
		if (chunksize < 0)
			result = SR_ERR;
		if (chunksize <= 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
			sum, bitstream.size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	g_free(buf);
	sr_resource_close(drvc->sr_ctx, &bitstream);

	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

/*
 * Get the session trigger and configure the FPGA structure
 * accordingly.
 */
static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	struct dslogic_fpga_config *cfg)
{
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	struct dev_context *devc;
	const GSList *l, *m;
	int channelbit, i = 0;
	uint16_t v16;

	devc = sdi->priv;

	cfg->ch_en = 0;
	for (l = sdi->channels; l; l = l->next) {
		const struct sr_channel *const probe = (struct sr_channel *)l->data;
		cfg->ch_en |= probe->enabled << probe->index;
	}

	cfg->trig_mask0[0] = 0xffff;
	cfg->trig_mask1[0] = 0xffff;

	cfg->trig_value0[0] = 0;
	cfg->trig_value1[0] = 0;

	cfg->trig_edge0[0] = 0;
	cfg->trig_edge1[0] = 0;

	cfg->trig_logic0[0] = 0;
	cfg->trig_logic1[0] = 0;

	cfg->trig_count[0] = 0;

	cfg->trig_glb = 0;

	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
		cfg->trig_mask0[i] = 0xff;
		cfg->trig_mask1[i] = 0xff;
		cfg->trig_value0[i] = 0;
		cfg->trig_value1[i] = 0;
		cfg->trig_edge0[i] = 0;
		cfg->trig_edge1[i] = 0;
		cfg->trig_logic0[i] = 2;
		cfg->trig_logic1[i] = 2;
		cfg->trig_count[i] = 0;
	}

	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	sr_dbg("pos: %d", cfg->trig_pos);

	sr_dbg("configuring trigger");

	if (!(trigger = sr_session_trigger_get(sdi->session))) {
		sr_dbg("No session trigger found");
		return SR_OK;
	}

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channelbit = 1 << (match->channel->index);
			/* Simple trigger support (event). */
			if (match->match == SR_TRIGGER_ONE) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_ZERO) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
			} else if (match->match == SR_TRIGGER_FALLING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_RISING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_EDGE) {
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			}
		}
	}

	v16 = RL16(&cfg->mode);
	v16 |= 1 << 0;
	WL16(&cfg->mode, v16);

	return SR_OK;
}

SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");

	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	WL16(&cfg.count_header, DS_CFG_COUNT);
	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
	WL16(&cfg.trig_header, DS_CFG_TRIG);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
			c, sizeof(c), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.",
			libusb_error_name(ret));
		return SR_ERR;
	}

	v16 = 0x0000;

	if (devc->mode == DS_OP_INTERNAL_TEST)
		v16 = DS_MODE_INT_TEST;
	else if (devc->mode == DS_OP_EXTERNAL_TEST)
		v16 = DS_MODE_EXT_TEST;
	else if (devc->mode == DS_OP_LOOPBACK_TEST)
		v16 = DS_MODE_LPB_TEST;
	if (devc->continuous_mode)
		v16 |= DS_MODE_STREAM_MODE;
	if (devc->external_clock) {
		v16 |= DS_MODE_CLK_TYPE;
		if (devc->clock_edge == DS_EDGE_FALLING)
			v16 |= DS_MODE_CLK_EDGE;
	}
	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
		ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
		&& !devc->continuous_mode) {
		/* Enable RLE for long captures.
		 * Without this, captured data present errors.
		 */
		v16 |= DS_MODE_RLE_MODE;
	}

	WL16(&cfg.mode, v16);
	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	dslogic_set_trigger(sdi, &cfg);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

static int to_bytes_per_ms(struct dev_context *devc)
{
	if (devc->cur_samplerate > SR_MHZ(100))
		return SR_MHZ(100) / 1000 * 2;
	return devc->cur_samplerate / 1000 * 2;
}

static size_t get_buffer_size(struct dev_context *devc)
{
	size_t s;

	/*
	 * The buffer should be large enough to hold 10ms of data and
	 * a multiple of 512.
	 */
	s = 10 * to_bytes_per_ms(devc);
	// s = to_bytes_per_ms(devc->cur_samplerate);
	return (s + 511) & ~511;
}

SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
{
	unsigned int n;

	/* Total buffer size should be able to hold about 100ms of data. */
	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
	sr_info("New calculation: %d", n);

	if (n > NUM_SIMUL_TRANSFERS)
		return NUM_SIMUL_TRANSFERS;

	return n;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <math.h>
	23	#include <glib.h>
	24	#include <glib/gstdio.h>
	25	#include "protocol.h"
	26	#include "dslogic.h"
	27
3f0ff412 DA	28	/*
	29	* This should be larger than the FPGA bitstream image so that it'll get
	30	* uploaded in one big operation. There seem to be issues when uploading
	31	* it in chunks.
	32	*/
	33	#define FW_BUFSIZE (1024 * 1024)
1a46cc62	34
4df5739a UH	35	#define FPGA_UPLOAD_DELAY (10 * 1000)
	36
	37	#define USB_TIMEOUT (3 * 1000)
	38
3fc3fbe4 DA	39	SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
	40	{
	41	struct sr_usb_dev_inst *usb;
3fc3fbe4	42	int ret;
c2f35321 JH	43	const uint8_t value = (vth / 5.0) * 255;
c2f35321 JH	44	const uint16_t cmd = value \| (DS_ADDR_VTH << 8);
3fc3fbe4	45
9803346f UH	46	usb = sdi->conn;
9803346f UH	47
3fc3fbe4	48	/* Send the control command. */
c2f35321 JH	49	ret = libusb_control_transfer(usb->devhdl,
	50	LIBUSB_REQUEST_TYPE_VENDOR \| LIBUSB_ENDPOINT_OUT,
	51	DS_CMD_WR_REG, 0x0000, 0x0000,
9803346f	52	(unsigned char *)&cmd, sizeof(cmd), 3000);
3fc3fbe4 DA	53	if (ret < 0) {
	54	sr_err("Unable to send VTH command: %s.",
	55	libusb_error_name(ret));
	56	return SR_ERR;
	57	}
	58
	59	return SR_OK;
	60	}
	61
8e2d6c9d DE	62	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
8e2d6c9d DE	63	const char *name)
b9d53092	64	{
8e2d6c9d DE	65	uint64_t sum;
	66	struct sr_resource bitstream;
	67	struct drv_context *drvc;
b9d53092	68	struct sr_usb_dev_inst *usb;
b9d53092	69	unsigned char *buf;
8e2d6c9d DE	70	ssize_t chunksize;
	71	int transferred;
	72	int result, ret;
cd189a44	73	const uint8_t cmd[3] = {0, 0, 0};
b9d53092	74
8e2d6c9d	75	drvc = sdi->driver->context;
b9d53092	76	usb = sdi->conn;
8e2d6c9d DE	77
	78	sr_dbg("Uploading FPGA firmware '%s'.", name);
	79
	80	result = sr_resource_open(drvc->sr_ctx, &bitstream,
	81	SR_RESOURCE_FIRMWARE, name);
	82	if (result != SR_OK)
	83	return result;
b9d53092 BV	84
	85	/* Tell the device firmware is coming. */
	86	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
9d71f815	87	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
d93c1470	88	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092	89	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
8e2d6c9d	90	sr_resource_close(drvc->sr_ctx, &bitstream);
b9d53092 BV	91	return SR_ERR;
	92	}
	93
	94	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	95	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092	96
8e2d6c9d	97	buf = g_malloc(FW_BUFSIZE);
b9d53092 BV	98	sum = 0;
	99	result = SR_OK;
	100	while (1) {
8e2d6c9d DE	101	chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
	102	buf, FW_BUFSIZE);
	103	if (chunksize < 0)
	104	result = SR_ERR;
	105	if (chunksize <= 0)
b9d53092 BV	106	break;
	107
	108	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	109	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	110	sr_err("Unable to configure FPGA firmware: %s.",
	111	libusb_error_name(ret));
	112	result = SR_ERR;
	113	break;
	114	}
	115	sum += transferred;
8e2d6c9d DE	116	sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
8e2d6c9d DE	117	sum, bitstream.size);
b9d53092 BV	118
	119	if (transferred != chunksize) {
	120	sr_err("Short transfer while uploading FPGA firmware.");
	121	result = SR_ERR;
	122	break;
	123	}
	124	}
b9d53092	125	g_free(buf);
8e2d6c9d DE	126	sr_resource_close(drvc->sr_ctx, &bitstream);
8e2d6c9d DE	127
b9d53092 BV	128	if (result == SR_OK)
	129	sr_dbg("FPGA firmware upload done.");
	130
	131	return result;
	132	}
	133
8e2d6c9d	134	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
b9d53092	135	{
b9d53092 BV	136	struct sr_usb_dev_inst *usb;
	137	struct dslogic_mode mode;
	138	int ret;
	139
adcb9951	140	mode.flags = DS_START_FLAGS_MODE_LA \| DS_START_FLAGS_SAMPLE_WIDE;
b9d53092	141	mode.sample_delay_h = mode.sample_delay_l = 0;
b9d53092 BV	142
	143	usb = sdi->conn;
	144	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	145	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	146	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	147	if (ret < 0) {
	148	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	149	return SR_ERR;
	150	}
	151
	152	return SR_OK;
	153	}
	154
8e2d6c9d	155	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	156	{
	157	struct sr_usb_dev_inst *usb;
	158	struct dslogic_mode mode;
	159	int ret;
	160
	161	mode.flags = DS_START_FLAGS_STOP;
	162	mode.sample_delay_h = mode.sample_delay_l = 0;
	163
	164	usb = sdi->conn;
	165	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	166	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	167	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	168	if (ret < 0) {
	169	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	170	return SR_ERR;
	171	}
	172
	173	return SR_OK;
	174	}
	175
3db03efa DA	176	/*
	177	* Get the session trigger and configure the FPGA structure
	178	* accordingly.
	179	*/
	180	static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	181	struct dslogic_fpga_config *cfg)
	182	{
	183	struct sr_trigger *trigger;
	184	struct sr_trigger_stage *stage;
	185	struct sr_trigger_match *match;
	186	struct dev_context *devc;
	187	const GSList l, m;
	188	int channelbit, i = 0;
	189	uint16_t v16;
	190
9803346f UH	191	devc = sdi->priv;
9803346f UH	192
e40ee26b JH	193	cfg->ch_en = 0;
	194	for (l = sdi->channels; l; l = l->next) {
	195	const struct sr_channel const probe = (struct sr_channel )l->data;
	196	cfg->ch_en \|= probe->enabled << probe->index;
	197	}
	198
3db03efa DA	199	cfg->trig_mask0[0] = 0xffff;
	200	cfg->trig_mask1[0] = 0xffff;
	201
	202	cfg->trig_value0[0] = 0;
	203	cfg->trig_value1[0] = 0;
	204
	205	cfg->trig_edge0[0] = 0;
	206	cfg->trig_edge1[0] = 0;
	207
	208	cfg->trig_logic0[0] = 0;
	209	cfg->trig_logic1[0] = 0;
	210
e40ee26b	211	cfg->trig_count[0] = 0;
3db03efa	212
4237fbca	213	cfg->trig_glb = 0;
4237fbca	214
adcb9951	215	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
4237fbca DA	216	cfg->trig_mask0[i] = 0xff;
	217	cfg->trig_mask1[i] = 0xff;
	218	cfg->trig_value0[i] = 0;
	219	cfg->trig_value1[i] = 0;
	220	cfg->trig_edge0[i] = 0;
	221	cfg->trig_edge1[i] = 0;
4237fbca DA	222	cfg->trig_logic0[i] = 2;
4237fbca DA	223	cfg->trig_logic1[i] = 2;
e40ee26b	224	cfg->trig_count[i] = 0;
4237fbca DA	225	}
	226
	227	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	228	sr_dbg("pos: %d", cfg->trig_pos);
	229
	230	sr_dbg("configuring trigger");
	231
9803346f	232	if (!(trigger = sr_session_trigger_get(sdi->session))) {
4237fbca	233	sr_dbg("No session trigger found");
3db03efa	234	return SR_OK;
4237fbca	235	}
3db03efa DA	236
	237	for (l = trigger->stages; l; l = l->next) {
	238	stage = l->data;
	239	for (m = stage->matches; m; m = m->next) {
	240	match = m->data;
	241	if (!match->channel->enabled)
	242	/* Ignore disabled channels with a trigger. */
	243	continue;
	244	channelbit = 1 << (match->channel->index);
3db03efa DA	245	/* Simple trigger support (event). */
	246	if (match->match == SR_TRIGGER_ONE) {
	247	cfg->trig_mask0[0] &= ~channelbit;
	248	cfg->trig_mask1[0] &= ~channelbit;
	249	cfg->trig_value0[0] \|= channelbit;
	250	cfg->trig_value1[0] \|= channelbit;
	251	} else if (match->match == SR_TRIGGER_ZERO) {
	252	cfg->trig_mask0[0] &= ~channelbit;
	253	cfg->trig_mask1[0] &= ~channelbit;
	254	} else if (match->match == SR_TRIGGER_FALLING) {
	255	cfg->trig_mask0[0] &= ~channelbit;
	256	cfg->trig_mask1[0] &= ~channelbit;
	257	cfg->trig_edge0[0] \|= channelbit;
	258	cfg->trig_edge1[0] \|= channelbit;
	259	} else if (match->match == SR_TRIGGER_RISING) {
	260	cfg->trig_mask0[0] &= ~channelbit;
	261	cfg->trig_mask1[0] &= ~channelbit;
	262	cfg->trig_value0[0] \|= channelbit;
	263	cfg->trig_value1[0] \|= channelbit;
	264	cfg->trig_edge0[0] \|= channelbit;
	265	cfg->trig_edge1[0] \|= channelbit;
9803346f	266	} else if (match->match == SR_TRIGGER_EDGE) {
3db03efa DA	267	cfg->trig_edge0[0] \|= channelbit;
	268	cfg->trig_edge1[0] \|= channelbit;
	269	}
	270	}
	271	}
9803346f	272
4237fbca DA	273	v16 = RL16(&cfg->mode);
	274	v16 \|= 1 << 0;
	275	WL16(&cfg->mode, v16);
9803346f	276
3db03efa DA	277	return SR_OK;
	278	}
	279
8e2d6c9d	280	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
b9d53092 BV	281	{
	282	struct dev_context *devc;
	283	struct sr_usb_dev_inst *usb;
	284	uint8_t c[3];
	285	struct dslogic_fpga_config cfg;
	286	uint16_t v16;
	287	uint32_t v32;
	288	int transferred, len, ret;
	289
	290	sr_dbg("Configuring FPGA.");
9803346f	291
b9d53092 BV	292	usb = sdi->conn;
	293	devc = sdi->priv;
	294
	295	WL32(&cfg.sync, DS_CFG_START);
	296	WL16(&cfg.mode_header, DS_CFG_MODE);
e40ee26b JH	297	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	298	WL16(&cfg.count_header, DS_CFG_COUNT);
	299	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
b9d53092	300	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
e40ee26b JH	301	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
e40ee26b JH	302	WL16(&cfg.trig_header, DS_CFG_TRIG);
b9d53092 BV	303	WL32(&cfg.end_sync, DS_CFG_END);
	304
	305	/* Pass in the length of a fixed-size struct. Really. */
	306	len = sizeof(struct dslogic_fpga_config) / 2;
	307	c[0] = len & 0xff;
	308	c[1] = (len >> 8) & 0xff;
	309	c[2] = (len >> 16) & 0xff;
	310
	311	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
e40ee26b JH	312	LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
e40ee26b JH	313	c, sizeof(c), USB_TIMEOUT);
b9d53092	314	if (ret < 0) {
9803346f UH	315	sr_err("Failed to send FPGA configure command: %s.",
9803346f UH	316	libusb_error_name(ret));
b9d53092 BV	317	return SR_ERR;
	318	}
	319
b9d53092	320	v16 = 0x0000;
e40ee26b	321
adcb9951	322	if (devc->mode == DS_OP_INTERNAL_TEST)
cf398cc0	323	v16 = DS_MODE_INT_TEST;
adcb9951	324	else if (devc->mode == DS_OP_EXTERNAL_TEST)
cf398cc0	325	v16 = DS_MODE_EXT_TEST;
adcb9951	326	else if (devc->mode == DS_OP_LOOPBACK_TEST)
cf398cc0	327	v16 = DS_MODE_LPB_TEST;
adcb9951	328	if (devc->continuous_mode)
cf398cc0	329	v16 \|= DS_MODE_STREAM_MODE;
adcb9951	330	if (devc->external_clock) {
cf398cc0	331	v16 \|= DS_MODE_CLK_TYPE;
adcb9951	332	if (devc->clock_edge == DS_EDGE_FALLING)
cf398cc0	333	v16 \|= DS_MODE_CLK_EDGE;
d9a58763	334	}
9803346f	335	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
176d785d	336	ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
adcb9951	337	&& !devc->continuous_mode) {
9803346f UH	338	/* Enable RLE for long captures.
	339	* Without this, captured data present errors.
	340	*/
cf398cc0	341	v16 \|= DS_MODE_RLE_MODE;
a9a9bfaa	342	}
3fc3fbe4	343
b9d53092	344	WL16(&cfg.mode, v16);
a04b28ce	345	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
b9d53092 BV	346	WL32(&cfg.divider, v32);
	347	WL32(&cfg.count, devc->limit_samples);
	348
3db03efa DA	349	dslogic_set_trigger(sdi, &cfg);
3db03efa DA	350
b9d53092 BV	351	len = sizeof(struct dslogic_fpga_config);
b9d53092 BV	352	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	353	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	354	if (ret < 0 \|\| transferred != len) {
	355	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	356	return SR_ERR;
	357	}
	358
	359	return SR_OK;
	360	}
a04b28ce	361
9803346f UH	362	static int to_bytes_per_ms(struct dev_context *devc)
9803346f UH	363	{
a04b28ce	364	if (devc->cur_samplerate > SR_MHZ(100))
adcb9951 JH	365	return SR_MHZ(100) / 1000 * 2;
adcb9951 JH	366	return devc->cur_samplerate / 1000 * 2;
a04b28ce DA	367	}
	368
	369	static size_t get_buffer_size(struct dev_context *devc)
	370	{
9803346f UH	371	size_t s;
	372
	373	/*
	374	* The buffer should be large enough to hold 10ms of data and
	375	* a multiple of 512.
	376	*/
	377	s = 10 * to_bytes_per_ms(devc);
	378	// s = to_bytes_per_ms(devc->cur_samplerate);
	379	return (s + 511) & ~511;
a04b28ce DA	380	}
a04b28ce DA	381
9803346f UH	382	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
9803346f UH	383	{
a04b28ce	384	unsigned int n;
9803346f	385
a04b28ce	386	/* Total buffer size should be able to hold about 100ms of data. */
9803346f	387	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
a04b28ce DA	388	sr_info("New calculation: %d", n);
	389
	390	if (n > NUM_SIMUL_TRANSFERS)
	391	return NUM_SIMUL_TRANSFERS;
	392
	393	return n;
	394	}