src/hardware/dslogic/dslogic.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
   5  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 3 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <config.h>
  22 #include <math.h>
  23 #include <glib.h>
  24 #include <glib/gstdio.h>
  25 #include "protocol.h"
  26 #include "dslogic.h"
  27
  28 /*
  29  * This should be larger than the FPGA bitstream image so that it'll get
  30  * uploaded in one big operation. There seem to be issues when uploading
  31  * it in chunks.
  32  */
  33 #define FW_BUFSIZE (1024 * 1024)
  34
  35 #define FPGA_UPLOAD_DELAY (10 * 1000)
  36
  37 #define USB_TIMEOUT (3 * 1000)
  38
  39 SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
  40 {
  41         struct sr_usb_dev_inst *usb;
  42         int ret;
  43         const uint8_t value = (vth / 5.0) * 255;
  44         const uint16_t cmd = value | (DS_ADDR_VTH << 8);
  45
  46         usb = sdi->conn;
  47
  48         /* Send the control command. */
  49         ret = libusb_control_transfer(usb->devhdl,
  50                         LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
  51                         DS_CMD_WR_REG, 0x0000, 0x0000,
  52                         (unsigned char *)&cmd, sizeof(cmd), 3000);
  53         if (ret < 0) {
  54                 sr_err("Unable to send VTH command: %s.",
  55                 libusb_error_name(ret));
  56                 return SR_ERR;
  57         }
  58
  59         return SR_OK;
  60 }
  61
  62 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
  63                 const char *name)
  64 {
  65         uint64_t sum;
  66         struct sr_resource bitstream;
  67         struct drv_context *drvc;
  68         struct sr_usb_dev_inst *usb;
  69         unsigned char *buf;
  70         ssize_t chunksize;
  71         int transferred;
  72         int result, ret;
  73         const uint8_t cmd[3] = {0, 0, 0};
  74
  75         drvc = sdi->driver->context;
  76         usb = sdi->conn;
  77
  78         sr_dbg("Uploading FPGA firmware '%s'.", name);
  79
  80         result = sr_resource_open(drvc->sr_ctx, &bitstream,
  81                         SR_RESOURCE_FIRMWARE, name);
  82         if (result != SR_OK)
  83                 return result;
  84
  85         /* Tell the device firmware is coming. */
  86         if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
  87                         LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
  88                         (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
  89                 sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
  90                 sr_resource_close(drvc->sr_ctx, &bitstream);
  91                 return SR_ERR;
  92         }
  93
  94         /* Give the FX2 time to get ready for FPGA firmware upload. */
  95         g_usleep(FPGA_UPLOAD_DELAY);
  96
  97         buf = g_malloc(FW_BUFSIZE);
  98         sum = 0;
  99         result = SR_OK;
 100         while (1) {
 101                 chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
 102                                 buf, FW_BUFSIZE);
 103                 if (chunksize < 0)
 104                         result = SR_ERR;
 105                 if (chunksize <= 0)
 106                         break;
 107
 108                 if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 109                                 buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
 110                         sr_err("Unable to configure FPGA firmware: %s.",
 111                                         libusb_error_name(ret));
 112                         result = SR_ERR;
 113                         break;
 114                 }
 115                 sum += transferred;
 116                 sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
 117                         sum, bitstream.size);
 118
 119                 if (transferred != chunksize) {
 120                         sr_err("Short transfer while uploading FPGA firmware.");
 121                         result = SR_ERR;
 122                         break;
 123                 }
 124         }
 125         g_free(buf);
 126         sr_resource_close(drvc->sr_ctx, &bitstream);
 127
 128         if (result == SR_OK)
 129                 sr_dbg("FPGA firmware upload done.");
 130
 131         return result;
 132 }
 133
 134 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 135 {
 136         struct sr_usb_dev_inst *usb;
 137         struct dslogic_mode mode;
 138         int ret;
 139
 140         mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
 141         mode.sample_delay_h = mode.sample_delay_l = 0;
 142
 143         usb = sdi->conn;
 144         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 145                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 146                         (unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
 147         if (ret < 0) {
 148                 sr_err("Failed to send start command: %s.", libusb_error_name(ret));
 149                 return SR_ERR;
 150         }
 151
 152         return SR_OK;
 153 }
 154
 155 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 156 {
 157         struct sr_usb_dev_inst *usb;
 158         struct dslogic_mode mode;
 159         int ret;
 160
 161         mode.flags = DS_START_FLAGS_STOP;
 162         mode.sample_delay_h = mode.sample_delay_l = 0;
 163
 164         usb = sdi->conn;
 165         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 166                         LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
 167                         (unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
 168         if (ret < 0) {
 169                 sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
 170                 return SR_ERR;
 171         }
 172
 173         return SR_OK;
 174 }
 175
 176 /*
 177  * Get the session trigger and configure the FPGA structure
 178  * accordingly.
 179  */
 180 static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
 181         struct dslogic_fpga_config *cfg)
 182 {
 183         struct sr_trigger *trigger;
 184         struct sr_trigger_stage *stage;
 185         struct sr_trigger_match *match;
 186         struct dev_context *devc;
 187         const GSList *l, *m;
 188         int channelbit, i = 0;
 189         uint16_t v16;
 190
 191         devc = sdi->priv;
 192
 193         cfg->ch_en = 0;
 194         for (l = sdi->channels; l; l = l->next) {
 195                 const struct sr_channel *const probe = (struct sr_channel *)l->data;
 196                 cfg->ch_en |= probe->enabled << probe->index;
 197         }
 198
 199         cfg->trig_mask0[0] = 0xffff;
 200         cfg->trig_mask1[0] = 0xffff;
 201
 202         cfg->trig_value0[0] = 0;
 203         cfg->trig_value1[0] = 0;
 204
 205         cfg->trig_edge0[0] = 0;
 206         cfg->trig_edge1[0] = 0;
 207
 208         cfg->trig_logic0[0] = 0;
 209         cfg->trig_logic1[0] = 0;
 210
 211         cfg->trig_count[0] = 0;
 212
 213         cfg->trig_glb = 0;
 214
 215         for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
 216                 cfg->trig_mask0[i] = 0xff;
 217                 cfg->trig_mask1[i] = 0xff;
 218                 cfg->trig_value0[i] = 0;
 219                 cfg->trig_value1[i] = 0;
 220                 cfg->trig_edge0[i] = 0;
 221                 cfg->trig_edge1[i] = 0;
 222                 cfg->trig_logic0[i] = 2;
 223                 cfg->trig_logic1[i] = 2;
 224                 cfg->trig_count[i] = 0;
 225         }
 226
 227         cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
 228         sr_dbg("pos: %d", cfg->trig_pos);
 229
 230         sr_dbg("configuring trigger");
 231
 232         if (!(trigger = sr_session_trigger_get(sdi->session))) {
 233                 sr_dbg("No session trigger found");
 234                 return SR_OK;
 235         }
 236
 237         for (l = trigger->stages; l; l = l->next) {
 238                 stage = l->data;
 239                 for (m = stage->matches; m; m = m->next) {
 240                         match = m->data;
 241                         if (!match->channel->enabled)
 242                                 /* Ignore disabled channels with a trigger. */
 243                                 continue;
 244                         channelbit = 1 << (match->channel->index);
 245                         /* Simple trigger support (event). */
 246                         if (match->match == SR_TRIGGER_ONE) {
 247                                 cfg->trig_mask0[0] &= ~channelbit;
 248                                 cfg->trig_mask1[0] &= ~channelbit;
 249                                 cfg->trig_value0[0] |= channelbit;
 250                                 cfg->trig_value1[0] |= channelbit;
 251                         } else if (match->match == SR_TRIGGER_ZERO) {
 252                                 cfg->trig_mask0[0] &= ~channelbit;
 253                                 cfg->trig_mask1[0] &= ~channelbit;
 254                         } else if (match->match == SR_TRIGGER_FALLING) {
 255                                 cfg->trig_mask0[0] &= ~channelbit;
 256                                 cfg->trig_mask1[0] &= ~channelbit;
 257                                 cfg->trig_edge0[0] |= channelbit;
 258                                 cfg->trig_edge1[0] |= channelbit;
 259                         } else if (match->match == SR_TRIGGER_RISING) {
 260                                 cfg->trig_mask0[0] &= ~channelbit;
 261                                 cfg->trig_mask1[0] &= ~channelbit;
 262                                 cfg->trig_value0[0] |= channelbit;
 263                                 cfg->trig_value1[0] |= channelbit;
 264                                 cfg->trig_edge0[0] |= channelbit;
 265                                 cfg->trig_edge1[0] |= channelbit;
 266                         } else if (match->match == SR_TRIGGER_EDGE) {
 267                                 cfg->trig_edge0[0] |= channelbit;
 268                                 cfg->trig_edge1[0] |= channelbit;
 269                         }
 270                 }
 271         }
 272
 273         v16 = RL16(&cfg->mode);
 274         v16 |= 1 << 0;
 275         WL16(&cfg->mode, v16);
 276
 277         return SR_OK;
 278 }
 279
 280 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 281 {
 282         struct dev_context *devc;
 283         struct sr_usb_dev_inst *usb;
 284         uint8_t c[3];
 285         struct dslogic_fpga_config cfg;
 286         uint16_t v16;
 287         uint32_t v32;
 288         int transferred, len, ret;
 289
 290         sr_dbg("Configuring FPGA.");
 291
 292         usb = sdi->conn;
 293         devc = sdi->priv;
 294
 295         WL32(&cfg.sync, DS_CFG_START);
 296         WL16(&cfg.mode_header, DS_CFG_MODE);
 297         WL16(&cfg.divider_header, DS_CFG_DIVIDER);
 298         WL16(&cfg.count_header, DS_CFG_COUNT);
 299         WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
 300         WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
 301         WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
 302         WL16(&cfg.trig_header, DS_CFG_TRIG);
 303         WL32(&cfg.end_sync, DS_CFG_END);
 304
 305         /* Pass in the length of a fixed-size struct. Really. */
 306         len = sizeof(struct dslogic_fpga_config) / 2;
 307         c[0] = len & 0xff;
 308         c[1] = (len >> 8) & 0xff;
 309         c[2] = (len >> 16) & 0xff;
 310
 311         ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
 312                         LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
 313                         c, sizeof(c), USB_TIMEOUT);
 314         if (ret < 0) {
 315                 sr_err("Failed to send FPGA configure command: %s.",
 316                         libusb_error_name(ret));
 317                 return SR_ERR;
 318         }
 319
 320         v16 = 0x0000;
 321
 322         if (devc->mode == DS_OP_INTERNAL_TEST)
 323                 v16 = DS_MODE_INT_TEST;
 324         else if (devc->mode == DS_OP_EXTERNAL_TEST)
 325                 v16 = DS_MODE_EXT_TEST;
 326         else if (devc->mode == DS_OP_LOOPBACK_TEST)
 327                 v16 = DS_MODE_LPB_TEST;
 328         if (devc->continuous_mode)
 329                 v16 |= DS_MODE_STREAM_MODE;
 330         if (devc->external_clock) {
 331                 v16 |= DS_MODE_CLK_TYPE;
 332                 if (devc->clock_edge == DS_EDGE_FALLING)
 333                         v16 |= DS_MODE_CLK_EDGE;
 334         }
 335         if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
 336                 ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
 337                 && !devc->continuous_mode) {
 338                 /* Enable RLE for long captures.
 339                  * Without this, captured data present errors.
 340                  */
 341                 v16 |= DS_MODE_RLE_MODE;
 342         }
 343
 344         WL16(&cfg.mode, v16);
 345         v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
 346         WL32(&cfg.divider, v32);
 347         WL32(&cfg.count, devc->limit_samples);
 348
 349         dslogic_set_trigger(sdi, &cfg);
 350
 351         len = sizeof(struct dslogic_fpga_config);
 352         ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 353                         (unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
 354         if (ret < 0 || transferred != len) {
 355                 sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
 356                 return SR_ERR;
 357         }
 358
 359         return SR_OK;
 360 }
 361
 362 static int to_bytes_per_ms(struct dev_context *devc)
 363 {
 364         if (devc->cur_samplerate > SR_MHZ(100))
 365                 return SR_MHZ(100) / 1000 * 2;
 366         return devc->cur_samplerate / 1000 * 2;
 367 }
 368
 369 static size_t get_buffer_size(struct dev_context *devc)
 370 {
 371         size_t s;
 372
 373         /*
 374          * The buffer should be large enough to hold 10ms of data and
 375          * a multiple of 512.
 376          */
 377         s = 10 * to_bytes_per_ms(devc);
 378         // s = to_bytes_per_ms(devc->cur_samplerate);
 379         return (s + 511) & ~511;
 380 }
 381
 382 SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
 383 {
 384         unsigned int n;
 385
 386         /* Total buffer size should be able to hold about 100ms of data. */
 387         n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
 388         sr_info("New calculation: %d", n);
 389
 390         if (n > NUM_SIMUL_TRANSFERS)
 391                 return NUM_SIMUL_TRANSFERS;
 392
 393         return n;
 394 }