[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

#define FW_BUFSIZE (4 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *name)
{
	uint64_t sum;
	struct sr_resource bitstream;
	struct drv_context *drvc;
	struct sr_usb_dev_inst *usb;
	unsigned char *buf;
	ssize_t chunksize;
	int transferred;
	int result, ret;
	uint8_t cmd[3];

	drvc = sdi->driver->context;
	usb = sdi->conn;

	sr_dbg("Uploading FPGA firmware '%s'.", name);

	result = sr_resource_open(drvc->sr_ctx, &bitstream,
			SR_RESOURCE_FIRMWARE, name);
	if (result != SR_OK)
		return result;

	/* Tell the device firmware is coming. */
	memset(cmd, 0, sizeof(cmd));
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		sr_resource_close(drvc->sr_ctx, &bitstream);
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	buf = g_malloc(FW_BUFSIZE);
	sum = 0;
	result = SR_OK;
	while (1) {
		chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
				buf, FW_BUFSIZE);
		if (chunksize < 0)
			result = SR_ERR;
		if (chunksize <= 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
			sum, bitstream.size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	g_free(buf);
	sr_resource_close(drvc->sr_ctx, &bitstream);

	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	devc = sdi->priv;
	mode.flags = 0;
	mode.sample_delay_h = mode.sample_delay_l = 0;
	if (devc->sample_wide)
		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");
	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	WL32(&cfg.count_header, DS_CFG_COUNT);
	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			c, 3, USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	/*
	 * 15	1 = internal test mode
	 * 14	1 = external test mode
	 * 13	1 = loopback test mode
	 * 8-12	unused
	 * 7	1 = analog mode
	 * 6	1 = samplerate 400MHz
	 * 5	1 = samplerate 200MHz or analog mode
	 * 4	0 = logic, 1 = dso or analog
	 * 2-3	unused
	 * 1	0 = internal clock, 1 = external clock
	 * 0	1 = trigger enabled
	 */
	v16 = 0x0000;
	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
		v16 = 1 << 15;
	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
		v16 = 1 << 14;
	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
		v16 = 1 << 13;
	if (devc->dslogic_external_clock)
		v16 |= 1 << 2;
	WL16(&cfg.mode, v16);

	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <math.h>
	23	#include <glib.h>
	24	#include <glib/gstdio.h>
	25	#include "protocol.h"
	26	#include "dslogic.h"
	27
1a46cc62 UH	28	#define FW_BUFSIZE (4 * 1024)
1a46cc62 UH	29
4df5739a UH	30	#define FPGA_UPLOAD_DELAY (10 * 1000)
	31
	32	#define USB_TIMEOUT (3 * 1000)
	33
8e2d6c9d DE	34	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
8e2d6c9d DE	35	const char *name)
b9d53092	36	{
8e2d6c9d DE	37	uint64_t sum;
	38	struct sr_resource bitstream;
	39	struct drv_context *drvc;
b9d53092	40	struct sr_usb_dev_inst *usb;
b9d53092	41	unsigned char *buf;
8e2d6c9d DE	42	ssize_t chunksize;
	43	int transferred;
	44	int result, ret;
d93c1470	45	uint8_t cmd[3];
b9d53092	46
8e2d6c9d	47	drvc = sdi->driver->context;
b9d53092	48	usb = sdi->conn;
8e2d6c9d DE	49
	50	sr_dbg("Uploading FPGA firmware '%s'.", name);
	51
	52	result = sr_resource_open(drvc->sr_ctx, &bitstream,
	53	SR_RESOURCE_FIRMWARE, name);
	54	if (result != SR_OK)
	55	return result;
b9d53092 BV	56
b9d53092 BV	57	/* Tell the device firmware is coming. */
d93c1470	58	memset(cmd, 0, sizeof(cmd));
b9d53092 BV	59	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
b9d53092 BV	60	LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
d93c1470	61	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092	62	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
8e2d6c9d	63	sr_resource_close(drvc->sr_ctx, &bitstream);
b9d53092 BV	64	return SR_ERR;
	65	}
	66
	67	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	68	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092	69
8e2d6c9d	70	buf = g_malloc(FW_BUFSIZE);
b9d53092 BV	71	sum = 0;
	72	result = SR_OK;
	73	while (1) {
8e2d6c9d DE	74	chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
	75	buf, FW_BUFSIZE);
	76	if (chunksize < 0)
	77	result = SR_ERR;
	78	if (chunksize <= 0)
b9d53092 BV	79	break;
	80
	81	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	82	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	83	sr_err("Unable to configure FPGA firmware: %s.",
	84	libusb_error_name(ret));
	85	result = SR_ERR;
	86	break;
	87	}
	88	sum += transferred;
8e2d6c9d DE	89	sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
8e2d6c9d DE	90	sum, bitstream.size);
b9d53092 BV	91
	92	if (transferred != chunksize) {
	93	sr_err("Short transfer while uploading FPGA firmware.");
	94	result = SR_ERR;
	95	break;
	96	}
	97	}
b9d53092	98	g_free(buf);
8e2d6c9d DE	99	sr_resource_close(drvc->sr_ctx, &bitstream);
8e2d6c9d DE	100
b9d53092 BV	101	if (result == SR_OK)
	102	sr_dbg("FPGA firmware upload done.");
	103
	104	return result;
	105	}
	106
8e2d6c9d	107	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	108	{
	109	struct dev_context *devc;
	110	struct sr_usb_dev_inst *usb;
	111	struct dslogic_mode mode;
	112	int ret;
	113
	114	devc = sdi->priv;
	115	mode.flags = 0;
	116	mode.sample_delay_h = mode.sample_delay_l = 0;
	117	if (devc->sample_wide)
	118	mode.flags \|= DS_START_FLAGS_SAMPLE_WIDE;
	119
	120	usb = sdi->conn;
	121	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	122	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	123	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	124	if (ret < 0) {
	125	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	126	return SR_ERR;
	127	}
	128
	129	return SR_OK;
	130	}
	131
8e2d6c9d	132	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	133	{
	134	struct sr_usb_dev_inst *usb;
	135	struct dslogic_mode mode;
	136	int ret;
	137
	138	mode.flags = DS_START_FLAGS_STOP;
	139	mode.sample_delay_h = mode.sample_delay_l = 0;
	140
	141	usb = sdi->conn;
	142	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	143	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	144	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	145	if (ret < 0) {
	146	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	147	return SR_ERR;
	148	}
	149
	150	return SR_OK;
	151	}
	152
8e2d6c9d	153	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
b9d53092 BV	154	{
	155	struct dev_context *devc;
	156	struct sr_usb_dev_inst *usb;
	157	uint8_t c[3];
	158	struct dslogic_fpga_config cfg;
	159	uint16_t v16;
	160	uint32_t v32;
	161	int transferred, len, ret;
	162
	163	sr_dbg("Configuring FPGA.");
	164	usb = sdi->conn;
	165	devc = sdi->priv;
	166
	167	WL32(&cfg.sync, DS_CFG_START);
	168	WL16(&cfg.mode_header, DS_CFG_MODE);
	169	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	170	WL32(&cfg.count_header, DS_CFG_COUNT);
	171	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	172	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	173	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	174	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	175	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	176	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	177	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	178	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	179	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	180	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	181	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	182	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	183	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	184	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	185	WL32(&cfg.end_sync, DS_CFG_END);
	186
	187	/* Pass in the length of a fixed-size struct. Really. */
	188	len = sizeof(struct dslogic_fpga_config) / 2;
	189	c[0] = len & 0xff;
	190	c[1] = (len >> 8) & 0xff;
	191	c[2] = (len >> 16) & 0xff;
	192
	193	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	194	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
4df5739a	195	c, 3, USB_TIMEOUT);
b9d53092 BV	196	if (ret < 0) {
	197	sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
	198	return SR_ERR;
	199	}
	200
	201	/*
	202	* 15 1 = internal test mode
	203	* 14 1 = external test mode
	204	* 13 1 = loopback test mode
	205	* 8-12 unused
	206	* 7 1 = analog mode
	207	* 6 1 = samplerate 400MHz
	208	* 5 1 = samplerate 200MHz or analog mode
	209	* 4 0 = logic, 1 = dso or analog
	210	* 2-3 unused
	211	* 1 0 = internal clock, 1 = external clock
	212	* 0 1 = trigger enabled
	213	*/
	214	v16 = 0x0000;
	215	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
	216	v16 = 1 << 15;
	217	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
	218	v16 = 1 << 14;
	219	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
	220	v16 = 1 << 13;
	221	if (devc->dslogic_external_clock)
	222	v16 \|= 1 << 2;
	223	WL16(&cfg.mode, v16);
	224
	225	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	226	WL32(&cfg.divider, v32);
	227	WL32(&cfg.count, devc->limit_samples);
	228
	229	len = sizeof(struct dslogic_fpga_config);
	230	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	231	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	232	if (ret < 0 \|\| transferred != len) {
	233	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	234	return SR_ERR;
	235	}
	236
	237	return SR_OK;
	238	}