[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

#define FW_BUFSIZE 4096
int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *filename)
{
	FILE *fw;
	struct stat st;
	struct sr_usb_dev_inst *usb;
	int chunksize, result, ret;
	unsigned char *buf;
	int sum, transferred;

	sr_dbg("Uploading FPGA firmware at %s.", filename);

	usb = sdi->conn;
	if (stat(filename, &st) < 0) {
		sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
		return SR_ERR;
	}

	/* Tell the device firmware is coming. */
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
			NULL, 0, 3000)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		return SR_ERR;
	}
	buf = g_malloc(FW_BUFSIZE);

	if ((fw = g_fopen(filename, "rb")) == NULL) {
		sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(10 * 1000);

	sum = 0;
	result = SR_OK;
	while (1) {
		if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, 1000)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	fclose(fw);
	g_free(buf);
	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	devc = sdi->priv;
	mode.flags = 0;
	mode.sample_delay_h = mode.sample_delay_l = 0;
	if (devc->sample_wide)
		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), 3000);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");
	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	WL32(&cfg.count_header, DS_CFG_COUNT);
	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			c, 3, 100);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	/*
	 * 15	1 = internal test mode
	 * 14	1 = external test mode
	 * 13	1 = loopback test mode
	 * 8-12	unused
	 * 7	1 = analog mode
	 * 6	1 = samplerate 400MHz
	 * 5	1 = samplerate 200MHz or analog mode
	 * 4	0 = logic, 1 = dso or analog
	 * 2-3	unused
	 * 1	0 = internal clock, 1 = external clock
	 * 0	1 = trigger enabled
	 */
	v16 = 0x0000;
	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
		v16 = 1 << 15;
	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
		v16 = 1 << 14;
	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
		v16 = 1 << 13;
	if (devc->dslogic_external_clock)
		v16 |= 1 << 2;
	WL16(&cfg.mode, v16);

	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len,
			&transferred, 100);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <sys/types.h>
	22	#include <sys/stat.h>
	23	#include <unistd.h>
	24	#include <errno.h>
	25	#include <math.h>
	26	#include <glib.h>
	27	#include <glib/gstdio.h>
	28	#include "protocol.h"
	29	#include "dslogic.h"
	30
	31	#define FW_BUFSIZE 4096
	32	int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
	33	const char *filename)
	34	{
	35	FILE *fw;
	36	struct stat st;
	37	struct sr_usb_dev_inst *usb;
	38	int chunksize, result, ret;
	39	unsigned char *buf;
	40	int sum, transferred;
	41
	42	sr_dbg("Uploading FPGA firmware at %s.", filename);
	43
	44	usb = sdi->conn;
	45	if (stat(filename, &st) < 0) {
	46	sr_err("Unable to upload FPGA firmware: %s", strerror(errno));
	47	return SR_ERR;
	48	}
	49
	50	/* Tell the device firmware is coming. */
	51	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	52	LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
	53	NULL, 0, 3000)) < 0) {
	54	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
	55	return SR_ERR;
	56	}
	57	buf = g_malloc(FW_BUFSIZE);
	58
	59	if ((fw = g_fopen(filename, "rb")) == NULL) {
	60	sr_err("Unable to open %s for reading: %s.", filename, strerror(errno));
	61	return SR_ERR;
	62	}
	63
	64	/* Give the FX2 time to get ready for FPGA firmware upload. */
65	g_usleep(10 * 1000);
66
67	sum = 0;
68	result = SR_OK;
69	while (1) {
70	if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
71	break;
72
73	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
74	buf, chunksize, &transferred, 1000)) < 0) {
75	sr_err("Unable to configure FPGA firmware: %s.",
76	libusb_error_name(ret));
77	result = SR_ERR;
78	break;
79	}
80	sum += transferred;
81	sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
82
83	if (transferred != chunksize) {
84	sr_err("Short transfer while uploading FPGA firmware.");
85	result = SR_ERR;
86	break;
87	}
88	}
89	fclose(fw);
90	g_free(buf);
91	if (result == SR_OK)
92	sr_dbg("FPGA firmware upload done.");
93
94	return result;
95	}
96
97	int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
98	{
99	struct dev_context *devc;
100	struct sr_usb_dev_inst *usb;
101	struct dslogic_mode mode;
102	int ret;
103
104	devc = sdi->priv;
105	mode.flags = 0;
106	mode.sample_delay_h = mode.sample_delay_l = 0;
107	if (devc->sample_wide)
108	mode.flags \|= DS_START_FLAGS_SAMPLE_WIDE;
109
110	usb = sdi->conn;
111	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
112	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
113	(unsigned char *)&mode, sizeof(mode), 3000);
114	if (ret < 0) {
115	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
116	return SR_ERR;
117	}
118
119	return SR_OK;
120	}
121
122	int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
123	{
124	struct sr_usb_dev_inst *usb;
125	struct dslogic_mode mode;
126	int ret;
127
128	mode.flags = DS_START_FLAGS_STOP;
129	mode.sample_delay_h = mode.sample_delay_l = 0;
130
131	usb = sdi->conn;
132	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
133	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
134	(unsigned char *)&mode, sizeof(struct dslogic_mode), 3000);
135	if (ret < 0) {
136	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
137	return SR_ERR;
138	}
139
140	return SR_OK;
141	}
142
143	int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
144	{
145	struct dev_context *devc;
146	struct sr_usb_dev_inst *usb;
147	uint8_t c[3];
148	struct dslogic_fpga_config cfg;
149	uint16_t v16;
150	uint32_t v32;
151	int transferred, len, ret;
152
153	sr_dbg("Configuring FPGA.");
154	usb = sdi->conn;
155	devc = sdi->priv;
156
157	WL32(&cfg.sync, DS_CFG_START);
158	WL16(&cfg.mode_header, DS_CFG_MODE);
159	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
160	WL32(&cfg.count_header, DS_CFG_COUNT);
161	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
162	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
163	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
164	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
165	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
166	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
167	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
168	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
169	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
170	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
171	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
172	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
173	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
174	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
175	WL32(&cfg.end_sync, DS_CFG_END);
176
177	/* Pass in the length of a fixed-size struct. Really. */
178	len = sizeof(struct dslogic_fpga_config) / 2;
179	c[0] = len & 0xff;
180	c[1] = (len >> 8) & 0xff;
181	c[2] = (len >> 16) & 0xff;
182
183	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
184	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
185	c, 3, 100);
186	if (ret < 0) {
187	sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
188	return SR_ERR;
189	}
190
191	/*
192	* 15 1 = internal test mode
193	* 14 1 = external test mode
194	* 13 1 = loopback test mode
195	* 8-12 unused
196	* 7 1 = analog mode
197	* 6 1 = samplerate 400MHz
198	* 5 1 = samplerate 200MHz or analog mode
199	* 4 0 = logic, 1 = dso or analog
200	* 2-3 unused
201	* 1 0 = internal clock, 1 = external clock
202	* 0 1 = trigger enabled
203	*/
204	v16 = 0x0000;
205	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
206	v16 = 1 << 15;
207	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
208	v16 = 1 << 14;
209	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
210	v16 = 1 << 13;
211	if (devc->dslogic_external_clock)
212	v16 \|= 1 << 2;
213	WL16(&cfg.mode, v16);
214
215	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
216	WL32(&cfg.divider, v32);
217	WL32(&cfg.count, devc->limit_samples);
218
219	len = sizeof(struct dslogic_fpga_config);
220	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
221	(unsigned char *)&cfg, len,
222	&transferred, 100);
223	if (ret < 0 \|\| transferred != len) {
224	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
225	return SR_ERR;
226	}
227
228	return SR_OK;
229	}