[libsigrok.git] / src / hardware / dslogic / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

/*
 * This should be larger than the FPGA bitstream image so that it'll get
 * uploaded in one big operation. There seem to be issues when uploading
 * it in chunks.
 */
#define FW_BUFSIZE (1024 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
{
	struct sr_usb_dev_inst *usb;
	int ret;
	const uint8_t value = (vth / 5.0) * 255;
	const uint16_t cmd = value | (DS_ADDR_VTH << 8);

	usb = sdi->conn;

	/* Send the control command. */
	ret = libusb_control_transfer(usb->devhdl,
			LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
			DS_CMD_WR_REG, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), 3000);
	if (ret < 0) {
		sr_err("Unable to send VTH command: %s.",
		libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
{
	const char *name = NULL;
	uint64_t sum;
	struct sr_resource bitstream;
	struct drv_context *drvc;
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	unsigned char *buf;
	ssize_t chunksize;
	int transferred;
	int result, ret;
	const uint8_t cmd[3] = {0, 0, 0};

	drvc = sdi->driver->context;
	devc = sdi->priv;
	usb = sdi->conn;

	if (!strcmp(devc->profile->model, "DSLogic")) {
		if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
			name = DSLOGIC_FPGA_FIRMWARE_3V3;
		else
			name = DSLOGIC_FPGA_FIRMWARE_5V;
	} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
		name = DSLOGIC_PRO_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
		name = DSLOGIC_PLUS_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
		name = DSLOGIC_BASIC_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSCope")) {
		name = DSCOPE_FPGA_FIRMWARE;
	} else {
		sr_err("Failed to select FPGA firmware.");
		return SR_ERR;
	}

	sr_dbg("Uploading FPGA firmware '%s'.", name);

	result = sr_resource_open(drvc->sr_ctx, &bitstream,
			SR_RESOURCE_FIRMWARE, name);
	if (result != SR_OK)
		return result;

	/* Tell the device firmware is coming. */
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		sr_resource_close(drvc->sr_ctx, &bitstream);
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	buf = g_malloc(FW_BUFSIZE);
	sum = 0;
	result = SR_OK;
	while (1) {
		chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
				buf, FW_BUFSIZE);
		if (chunksize < 0)
			result = SR_ERR;
		if (chunksize <= 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
			sum, bitstream.size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	g_free(buf);
	sr_resource_close(drvc->sr_ctx, &bitstream);

	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

/*
 * Get the session trigger and configure the FPGA structure
 * accordingly.
 */
static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	struct dslogic_fpga_config *cfg)
{
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	struct dev_context *devc;
	const GSList *l, *m;
	int channelbit, i = 0;
	uint16_t v16;

	devc = sdi->priv;

	cfg->ch_en = 0;
	for (l = sdi->channels; l; l = l->next) {
		const struct sr_channel *const probe = (struct sr_channel *)l->data;
		cfg->ch_en |= probe->enabled << probe->index;
	}

	cfg->trig_mask0[0] = 0xffff;
	cfg->trig_mask1[0] = 0xffff;

	cfg->trig_value0[0] = 0;
	cfg->trig_value1[0] = 0;

	cfg->trig_edge0[0] = 0;
	cfg->trig_edge1[0] = 0;

	cfg->trig_logic0[0] = 0;
	cfg->trig_logic1[0] = 0;

	cfg->trig_count[0] = 0;

	cfg->trig_glb = 0;

	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
		cfg->trig_mask0[i] = 0xff;
		cfg->trig_mask1[i] = 0xff;
		cfg->trig_value0[i] = 0;
		cfg->trig_value1[i] = 0;
		cfg->trig_edge0[i] = 0;
		cfg->trig_edge1[i] = 0;
		cfg->trig_logic0[i] = 2;
		cfg->trig_logic1[i] = 2;
		cfg->trig_count[i] = 0;
	}

	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	sr_dbg("pos: %d", cfg->trig_pos);

	sr_dbg("configuring trigger");

	if (!(trigger = sr_session_trigger_get(sdi->session))) {
		sr_dbg("No session trigger found");
		return SR_OK;
	}

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channelbit = 1 << (match->channel->index);
			/* Simple trigger support (event). */
			if (match->match == SR_TRIGGER_ONE) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_ZERO) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
			} else if (match->match == SR_TRIGGER_FALLING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_RISING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_EDGE) {
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			}
		}
	}

	v16 = RL16(&cfg->mode);
	v16 |= 1 << 0;
	WL16(&cfg->mode, v16);

	return SR_OK;
}

SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");

	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	WL16(&cfg.count_header, DS_CFG_COUNT);
	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
	WL16(&cfg.trig_header, DS_CFG_TRIG);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
			c, sizeof(c), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.",
			libusb_error_name(ret));
		return SR_ERR;
	}

	v16 = 0x0000;

	if (devc->mode == DS_OP_INTERNAL_TEST)
		v16 = DS_MODE_INT_TEST;
	else if (devc->mode == DS_OP_EXTERNAL_TEST)
		v16 = DS_MODE_EXT_TEST;
	else if (devc->mode == DS_OP_LOOPBACK_TEST)
		v16 = DS_MODE_LPB_TEST;

	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
		v16 |= DS_MODE_HALF_MODE;
	else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
		v16 |= DS_MODE_QUAR_MODE;

	if (devc->continuous_mode)
		v16 |= DS_MODE_STREAM_MODE;
	if (devc->external_clock) {
		v16 |= DS_MODE_CLK_TYPE;
		if (devc->clock_edge == DS_EDGE_FALLING)
			v16 |= DS_MODE_CLK_EDGE;
	}
	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
		ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
		&& !devc->continuous_mode) {
		/* Enable RLE for long captures.
		 * Without this, captured data present errors.
		 */
		v16 |= DS_MODE_RLE_MODE;
	}

	WL16(&cfg.mode, v16);
	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	dslogic_set_trigger(sdi, &cfg);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

static int to_bytes_per_ms(struct dev_context *devc)
{
	if (devc->cur_samplerate > SR_MHZ(100))
		return SR_MHZ(100) / 1000 * 2;
	return devc->cur_samplerate / 1000 * 2;
}

static size_t get_buffer_size(struct dev_context *devc)
{
	size_t s;

	/*
	 * The buffer should be large enough to hold 10ms of data and
	 * a multiple of 512.
	 */
	s = 10 * to_bytes_per_ms(devc);
	// s = to_bytes_per_ms(devc->cur_samplerate);
	return (s + 511) & ~511;
}

SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
{
	unsigned int n;

	/* Total buffer size should be able to hold about 100ms of data. */
	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
	sr_info("New calculation: %d", n);

	if (n > NUM_SIMUL_TRANSFERS)
		return NUM_SIMUL_TRANSFERS;

	return n;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <math.h>
	23	#include <glib.h>
	24	#include <glib/gstdio.h>
	25	#include "protocol.h"
	26	#include "dslogic.h"
	27
3f0ff412 DA	28	/*
	29	* This should be larger than the FPGA bitstream image so that it'll get
	30	* uploaded in one big operation. There seem to be issues when uploading
	31	* it in chunks.
	32	*/
	33	#define FW_BUFSIZE (1024 * 1024)
1a46cc62	34
4df5739a UH	35	#define FPGA_UPLOAD_DELAY (10 * 1000)
	36
	37	#define USB_TIMEOUT (3 * 1000)
	38
3fc3fbe4 DA	39	SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
	40	{
	41	struct sr_usb_dev_inst *usb;
3fc3fbe4	42	int ret;
c2f35321 JH	43	const uint8_t value = (vth / 5.0) * 255;
c2f35321 JH	44	const uint16_t cmd = value \| (DS_ADDR_VTH << 8);
3fc3fbe4	45
9803346f UH	46	usb = sdi->conn;
9803346f UH	47
3fc3fbe4	48	/* Send the control command. */
c2f35321 JH	49	ret = libusb_control_transfer(usb->devhdl,
	50	LIBUSB_REQUEST_TYPE_VENDOR \| LIBUSB_ENDPOINT_OUT,
	51	DS_CMD_WR_REG, 0x0000, 0x0000,
9803346f	52	(unsigned char *)&cmd, sizeof(cmd), 3000);
3fc3fbe4 DA	53	if (ret < 0) {
	54	sr_err("Unable to send VTH command: %s.",
	55	libusb_error_name(ret));
	56	return SR_ERR;
	57	}
	58
	59	return SR_OK;
	60	}
	61
3566348b	62	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
b9d53092	63	{
3566348b	64	const char *name = NULL;
8e2d6c9d DE	65	uint64_t sum;
	66	struct sr_resource bitstream;
	67	struct drv_context *drvc;
3566348b	68	struct dev_context *devc;
b9d53092	69	struct sr_usb_dev_inst *usb;
b9d53092	70	unsigned char *buf;
8e2d6c9d DE	71	ssize_t chunksize;
	72	int transferred;
	73	int result, ret;
cd189a44	74	const uint8_t cmd[3] = {0, 0, 0};
b9d53092	75
8e2d6c9d	76	drvc = sdi->driver->context;
3566348b	77	devc = sdi->priv;
b9d53092	78	usb = sdi->conn;
8e2d6c9d	79
3566348b JH	80	if (!strcmp(devc->profile->model, "DSLogic")) {
	81	if (devc->voltage_threshold == DS_VOLTAGE_RANGE_18_33_V)
	82	name = DSLOGIC_FPGA_FIRMWARE_3V3;
	83	else
	84	name = DSLOGIC_FPGA_FIRMWARE_5V;
	85	} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
	86	name = DSLOGIC_PRO_FPGA_FIRMWARE;
	87	} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
	88	name = DSLOGIC_PLUS_FPGA_FIRMWARE;
	89	} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
	90	name = DSLOGIC_BASIC_FPGA_FIRMWARE;
	91	} else if (!strcmp(devc->profile->model, "DSCope")) {
	92	name = DSCOPE_FPGA_FIRMWARE;
	93	} else {
	94	sr_err("Failed to select FPGA firmware.");
	95	return SR_ERR;
	96	}
	97
8e2d6c9d DE	98	sr_dbg("Uploading FPGA firmware '%s'.", name);
	99
	100	result = sr_resource_open(drvc->sr_ctx, &bitstream,
	101	SR_RESOURCE_FIRMWARE, name);
	102	if (result != SR_OK)
	103	return result;
b9d53092 BV	104
	105	/* Tell the device firmware is coming. */
	106	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
9d71f815	107	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
d93c1470	108	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092	109	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
8e2d6c9d	110	sr_resource_close(drvc->sr_ctx, &bitstream);
b9d53092 BV	111	return SR_ERR;
	112	}
	113
	114	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	115	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092	116
8e2d6c9d	117	buf = g_malloc(FW_BUFSIZE);
b9d53092 BV	118	sum = 0;
	119	result = SR_OK;
	120	while (1) {
8e2d6c9d DE	121	chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
	122	buf, FW_BUFSIZE);
	123	if (chunksize < 0)
	124	result = SR_ERR;
	125	if (chunksize <= 0)
b9d53092 BV	126	break;
	127
	128	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	129	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	130	sr_err("Unable to configure FPGA firmware: %s.",
	131	libusb_error_name(ret));
	132	result = SR_ERR;
	133	break;
	134	}
	135	sum += transferred;
8e2d6c9d DE	136	sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
8e2d6c9d DE	137	sum, bitstream.size);
b9d53092 BV	138
	139	if (transferred != chunksize) {
	140	sr_err("Short transfer while uploading FPGA firmware.");
	141	result = SR_ERR;
	142	break;
	143	}
	144	}
b9d53092	145	g_free(buf);
8e2d6c9d DE	146	sr_resource_close(drvc->sr_ctx, &bitstream);
8e2d6c9d DE	147
b9d53092 BV	148	if (result == SR_OK)
	149	sr_dbg("FPGA firmware upload done.");
	150
	151	return result;
	152	}
	153
8e2d6c9d	154	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
b9d53092	155	{
b9d53092 BV	156	struct sr_usb_dev_inst *usb;
	157	struct dslogic_mode mode;
	158	int ret;
	159
adcb9951	160	mode.flags = DS_START_FLAGS_MODE_LA \| DS_START_FLAGS_SAMPLE_WIDE;
b9d53092	161	mode.sample_delay_h = mode.sample_delay_l = 0;
b9d53092 BV	162
	163	usb = sdi->conn;
	164	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	165	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	166	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	167	if (ret < 0) {
	168	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	169	return SR_ERR;
	170	}
	171
	172	return SR_OK;
	173	}
	174
8e2d6c9d	175	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	176	{
	177	struct sr_usb_dev_inst *usb;
	178	struct dslogic_mode mode;
	179	int ret;
	180
	181	mode.flags = DS_START_FLAGS_STOP;
	182	mode.sample_delay_h = mode.sample_delay_l = 0;
	183
	184	usb = sdi->conn;
	185	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	186	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	187	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	188	if (ret < 0) {
	189	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	190	return SR_ERR;
	191	}
	192
	193	return SR_OK;
	194	}
	195
3db03efa DA	196	/*
	197	* Get the session trigger and configure the FPGA structure
	198	* accordingly.
	199	*/
	200	static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	201	struct dslogic_fpga_config *cfg)
	202	{
	203	struct sr_trigger *trigger;
	204	struct sr_trigger_stage *stage;
	205	struct sr_trigger_match *match;
	206	struct dev_context *devc;
	207	const GSList l, m;
	208	int channelbit, i = 0;
	209	uint16_t v16;
	210
9803346f UH	211	devc = sdi->priv;
9803346f UH	212
e40ee26b JH	213	cfg->ch_en = 0;
	214	for (l = sdi->channels; l; l = l->next) {
	215	const struct sr_channel const probe = (struct sr_channel )l->data;
	216	cfg->ch_en \|= probe->enabled << probe->index;
	217	}
	218
3db03efa DA	219	cfg->trig_mask0[0] = 0xffff;
	220	cfg->trig_mask1[0] = 0xffff;
	221
	222	cfg->trig_value0[0] = 0;
	223	cfg->trig_value1[0] = 0;
	224
	225	cfg->trig_edge0[0] = 0;
	226	cfg->trig_edge1[0] = 0;
	227
	228	cfg->trig_logic0[0] = 0;
	229	cfg->trig_logic1[0] = 0;
	230
e40ee26b	231	cfg->trig_count[0] = 0;
3db03efa	232
4237fbca	233	cfg->trig_glb = 0;
4237fbca	234
adcb9951	235	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
4237fbca DA	236	cfg->trig_mask0[i] = 0xff;
	237	cfg->trig_mask1[i] = 0xff;
	238	cfg->trig_value0[i] = 0;
	239	cfg->trig_value1[i] = 0;
	240	cfg->trig_edge0[i] = 0;
	241	cfg->trig_edge1[i] = 0;
4237fbca DA	242	cfg->trig_logic0[i] = 2;
4237fbca DA	243	cfg->trig_logic1[i] = 2;
e40ee26b	244	cfg->trig_count[i] = 0;
4237fbca DA	245	}
	246
	247	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	248	sr_dbg("pos: %d", cfg->trig_pos);
	249
	250	sr_dbg("configuring trigger");
	251
9803346f	252	if (!(trigger = sr_session_trigger_get(sdi->session))) {
4237fbca	253	sr_dbg("No session trigger found");
3db03efa	254	return SR_OK;
4237fbca	255	}
3db03efa DA	256
	257	for (l = trigger->stages; l; l = l->next) {
	258	stage = l->data;
	259	for (m = stage->matches; m; m = m->next) {
	260	match = m->data;
	261	if (!match->channel->enabled)
	262	/* Ignore disabled channels with a trigger. */
	263	continue;
	264	channelbit = 1 << (match->channel->index);
3db03efa DA	265	/* Simple trigger support (event). */
	266	if (match->match == SR_TRIGGER_ONE) {
	267	cfg->trig_mask0[0] &= ~channelbit;
	268	cfg->trig_mask1[0] &= ~channelbit;
	269	cfg->trig_value0[0] \|= channelbit;
	270	cfg->trig_value1[0] \|= channelbit;
	271	} else if (match->match == SR_TRIGGER_ZERO) {
	272	cfg->trig_mask0[0] &= ~channelbit;
	273	cfg->trig_mask1[0] &= ~channelbit;
	274	} else if (match->match == SR_TRIGGER_FALLING) {
	275	cfg->trig_mask0[0] &= ~channelbit;
	276	cfg->trig_mask1[0] &= ~channelbit;
	277	cfg->trig_edge0[0] \|= channelbit;
	278	cfg->trig_edge1[0] \|= channelbit;
	279	} else if (match->match == SR_TRIGGER_RISING) {
	280	cfg->trig_mask0[0] &= ~channelbit;
	281	cfg->trig_mask1[0] &= ~channelbit;
	282	cfg->trig_value0[0] \|= channelbit;
	283	cfg->trig_value1[0] \|= channelbit;
	284	cfg->trig_edge0[0] \|= channelbit;
	285	cfg->trig_edge1[0] \|= channelbit;
9803346f	286	} else if (match->match == SR_TRIGGER_EDGE) {
3db03efa DA	287	cfg->trig_edge0[0] \|= channelbit;
	288	cfg->trig_edge1[0] \|= channelbit;
	289	}
	290	}
	291	}
9803346f	292
4237fbca DA	293	v16 = RL16(&cfg->mode);
	294	v16 \|= 1 << 0;
	295	WL16(&cfg->mode, v16);
9803346f	296
3db03efa DA	297	return SR_OK;
	298	}
	299
8e2d6c9d	300	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
b9d53092 BV	301	{
	302	struct dev_context *devc;
	303	struct sr_usb_dev_inst *usb;
	304	uint8_t c[3];
	305	struct dslogic_fpga_config cfg;
	306	uint16_t v16;
	307	uint32_t v32;
	308	int transferred, len, ret;
	309
	310	sr_dbg("Configuring FPGA.");
9803346f	311
b9d53092 BV	312	usb = sdi->conn;
	313	devc = sdi->priv;
	314
	315	WL32(&cfg.sync, DS_CFG_START);
	316	WL16(&cfg.mode_header, DS_CFG_MODE);
e40ee26b JH	317	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	318	WL16(&cfg.count_header, DS_CFG_COUNT);
	319	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
b9d53092	320	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
e40ee26b JH	321	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
e40ee26b JH	322	WL16(&cfg.trig_header, DS_CFG_TRIG);
b9d53092 BV	323	WL32(&cfg.end_sync, DS_CFG_END);
	324
	325	/* Pass in the length of a fixed-size struct. Really. */
	326	len = sizeof(struct dslogic_fpga_config) / 2;
	327	c[0] = len & 0xff;
	328	c[1] = (len >> 8) & 0xff;
	329	c[2] = (len >> 16) & 0xff;
	330
	331	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
e40ee26b JH	332	LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
e40ee26b JH	333	c, sizeof(c), USB_TIMEOUT);
b9d53092	334	if (ret < 0) {
9803346f UH	335	sr_err("Failed to send FPGA configure command: %s.",
9803346f UH	336	libusb_error_name(ret));
b9d53092 BV	337	return SR_ERR;
	338	}
	339
b9d53092	340	v16 = 0x0000;
e40ee26b	341
adcb9951	342	if (devc->mode == DS_OP_INTERNAL_TEST)
cf398cc0	343	v16 = DS_MODE_INT_TEST;
adcb9951	344	else if (devc->mode == DS_OP_EXTERNAL_TEST)
cf398cc0	345	v16 = DS_MODE_EXT_TEST;
adcb9951	346	else if (devc->mode == DS_OP_LOOPBACK_TEST)
cf398cc0	347	v16 = DS_MODE_LPB_TEST;
780c5e24 JH	348
	349	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
	350	v16 \|= DS_MODE_HALF_MODE;
	351	else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
	352	v16 \|= DS_MODE_QUAR_MODE;
	353
adcb9951	354	if (devc->continuous_mode)
cf398cc0	355	v16 \|= DS_MODE_STREAM_MODE;
adcb9951	356	if (devc->external_clock) {
cf398cc0	357	v16 \|= DS_MODE_CLK_TYPE;
adcb9951	358	if (devc->clock_edge == DS_EDGE_FALLING)
cf398cc0	359	v16 \|= DS_MODE_CLK_EDGE;
d9a58763	360	}
9803346f	361	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
176d785d	362	ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
adcb9951	363	&& !devc->continuous_mode) {
9803346f UH	364	/* Enable RLE for long captures.
	365	* Without this, captured data present errors.
	366	*/
cf398cc0	367	v16 \|= DS_MODE_RLE_MODE;
a9a9bfaa	368	}
3fc3fbe4	369
b9d53092	370	WL16(&cfg.mode, v16);
a04b28ce	371	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
b9d53092 BV	372	WL32(&cfg.divider, v32);
	373	WL32(&cfg.count, devc->limit_samples);
	374
3db03efa DA	375	dslogic_set_trigger(sdi, &cfg);
3db03efa DA	376
b9d53092 BV	377	len = sizeof(struct dslogic_fpga_config);
b9d53092 BV	378	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	379	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	380	if (ret < 0 \|\| transferred != len) {
	381	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	382	return SR_ERR;
	383	}
	384
	385	return SR_OK;
	386	}
a04b28ce	387
9803346f UH	388	static int to_bytes_per_ms(struct dev_context *devc)
9803346f UH	389	{
a04b28ce	390	if (devc->cur_samplerate > SR_MHZ(100))
adcb9951 JH	391	return SR_MHZ(100) / 1000 * 2;
adcb9951 JH	392	return devc->cur_samplerate / 1000 * 2;
a04b28ce DA	393	}
	394
	395	static size_t get_buffer_size(struct dev_context *devc)
	396	{
9803346f UH	397	size_t s;
	398
	399	/*
	400	* The buffer should be large enough to hold 10ms of data and
	401	* a multiple of 512.
	402	*/
	403	s = 10 * to_bytes_per_ms(devc);
	404	// s = to_bytes_per_ms(devc->cur_samplerate);
	405	return (s + 511) & ~511;
a04b28ce DA	406	}
a04b28ce DA	407
9803346f UH	408	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
9803346f UH	409	{
a04b28ce	410	unsigned int n;
9803346f	411
a04b28ce	412	/* Total buffer size should be able to hold about 100ms of data. */
9803346f	413	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
a04b28ce DA	414	sr_info("New calculation: %d", n);
	415
	416	if (n > NUM_SIMUL_TRANSFERS)
	417	return NUM_SIMUL_TRANSFERS;
	418
	419	return n;
	420	}