[libsigrok.git] / src / hardware / dslogic / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

/*
 * This should be larger than the FPGA bitstream image so that it'll get
 * uploaded in one big operation. There seem to be issues when uploading
 * it in chunks.
 */
#define FW_BUFSIZE (1024 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
{
	const char *name = NULL;
	uint64_t sum;
	struct sr_resource bitstream;
	struct drv_context *drvc;
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	unsigned char *buf;
	ssize_t chunksize;
	int transferred;
	int result, ret;
	const uint8_t cmd[3] = {0, 0, 0};

	drvc = sdi->driver->context;
	devc = sdi->priv;
	usb = sdi->conn;

	if (!strcmp(devc->profile->model, "DSLogic")) {
		if (devc->cur_threshold < 1.40)
			name = DSLOGIC_FPGA_FIRMWARE_3V3;
		else
			name = DSLOGIC_FPGA_FIRMWARE_5V;
	} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
		name = DSLOGIC_PRO_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
		name = DSLOGIC_PLUS_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
		name = DSLOGIC_BASIC_FPGA_FIRMWARE;
	} else if (!strcmp(devc->profile->model, "DSCope")) {
		name = DSCOPE_FPGA_FIRMWARE;
	} else {
		sr_err("Failed to select FPGA firmware.");
		return SR_ERR;
	}

	sr_dbg("Uploading FPGA firmware '%s'.", name);

	result = sr_resource_open(drvc->sr_ctx, &bitstream,
			SR_RESOURCE_FIRMWARE, name);
	if (result != SR_OK)
		return result;

	/* Tell the device firmware is coming. */
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		sr_resource_close(drvc->sr_ctx, &bitstream);
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	buf = g_malloc(FW_BUFSIZE);
	sum = 0;
	result = SR_OK;
	while (1) {
		chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
				buf, FW_BUFSIZE);
		if (chunksize < 0)
			result = SR_ERR;
		if (chunksize <= 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
			sum, bitstream.size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	g_free(buf);
	sr_resource_close(drvc->sr_ctx, &bitstream);

	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_MODE_LA | DS_START_FLAGS_SAMPLE_WIDE;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

/*
 * Get the session trigger and configure the FPGA structure
 * accordingly.
 */
static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	struct dslogic_fpga_config *cfg)
{
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	struct dev_context *devc;
	const GSList *l, *m;
	int channelbit, i = 0;
	uint16_t v16;

	devc = sdi->priv;

	cfg->ch_en = 0;
	for (l = sdi->channels; l; l = l->next) {
		const struct sr_channel *const probe = (struct sr_channel *)l->data;
		cfg->ch_en |= probe->enabled << probe->index;
	}

	cfg->trig_mask0[0] = 0xffff;
	cfg->trig_mask1[0] = 0xffff;

	cfg->trig_value0[0] = 0;
	cfg->trig_value1[0] = 0;

	cfg->trig_edge0[0] = 0;
	cfg->trig_edge1[0] = 0;

	cfg->trig_logic0[0] = 0;
	cfg->trig_logic1[0] = 0;

	cfg->trig_count[0] = 0;

	cfg->trig_glb = 0;

	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
		cfg->trig_mask0[i] = 0xff;
		cfg->trig_mask1[i] = 0xff;
		cfg->trig_value0[i] = 0;
		cfg->trig_value1[i] = 0;
		cfg->trig_edge0[i] = 0;
		cfg->trig_edge1[i] = 0;
		cfg->trig_logic0[i] = 2;
		cfg->trig_logic1[i] = 2;
		cfg->trig_count[i] = 0;
	}

	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	sr_dbg("pos: %d", cfg->trig_pos);

	sr_dbg("configuring trigger");

	if (!(trigger = sr_session_trigger_get(sdi->session))) {
		sr_dbg("No session trigger found");
		return SR_OK;
	}

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channelbit = 1 << (match->channel->index);
			/* Simple trigger support (event). */
			if (match->match == SR_TRIGGER_ONE) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_ZERO) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
			} else if (match->match == SR_TRIGGER_FALLING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_RISING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_EDGE) {
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			}
		}
	}

	v16 = RL16(&cfg->mode);
	v16 |= 1 << 0;
	WL16(&cfg->mode, v16);

	return SR_OK;
}

SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");

	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	WL16(&cfg.count_header, DS_CFG_COUNT);
	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
	WL16(&cfg.trig_header, DS_CFG_TRIG);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
			c, sizeof(c), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.",
			libusb_error_name(ret));
		return SR_ERR;
	}

	v16 = 0x0000;

	if (devc->mode == DS_OP_INTERNAL_TEST)
		v16 = DS_MODE_INT_TEST;
	else if (devc->mode == DS_OP_EXTERNAL_TEST)
		v16 = DS_MODE_EXT_TEST;
	else if (devc->mode == DS_OP_LOOPBACK_TEST)
		v16 = DS_MODE_LPB_TEST;

	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
		v16 |= DS_MODE_HALF_MODE;
	else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
		v16 |= DS_MODE_QUAR_MODE;

	if (devc->continuous_mode)
		v16 |= DS_MODE_STREAM_MODE;
	if (devc->external_clock) {
		v16 |= DS_MODE_CLK_TYPE;
		if (devc->clock_edge == DS_EDGE_FALLING)
			v16 |= DS_MODE_CLK_EDGE;
	}
	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
		ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
		&& !devc->continuous_mode) {
		/* Enable RLE for long captures.
		 * Without this, captured data present errors.
		 */
		v16 |= DS_MODE_RLE_MODE;
	}

	WL16(&cfg.mode, v16);
	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	dslogic_set_trigger(sdi, &cfg);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

static int to_bytes_per_ms(struct dev_context *devc)
{
	if (devc->cur_samplerate > SR_MHZ(100))
		return SR_MHZ(100) / 1000 * 2;
	return devc->cur_samplerate / 1000 * 2;
}

static size_t get_buffer_size(struct dev_context *devc)
{
	size_t s;

	/*
	 * The buffer should be large enough to hold 10ms of data and
	 * a multiple of 512.
	 */
	s = 10 * to_bytes_per_ms(devc);
	// s = to_bytes_per_ms(devc->cur_samplerate);
	return (s + 511) & ~511;
}

SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
{
	unsigned int n;

	/* Total buffer size should be able to hold about 100ms of data. */
	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
	sr_info("New calculation: %d", n);

	if (n > NUM_SIMUL_TRANSFERS)
		return NUM_SIMUL_TRANSFERS;

	return n;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <math.h>
	23	#include <glib.h>
	24	#include <glib/gstdio.h>
	25	#include "protocol.h"
	26	#include "dslogic.h"
	27
3f0ff412 DA	28	/*
	29	* This should be larger than the FPGA bitstream image so that it'll get
	30	* uploaded in one big operation. There seem to be issues when uploading
	31	* it in chunks.
	32	*/
	33	#define FW_BUFSIZE (1024 * 1024)
1a46cc62	34
4df5739a UH	35	#define FPGA_UPLOAD_DELAY (10 * 1000)
	36
	37	#define USB_TIMEOUT (3 * 1000)
	38
3566348b	39	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
b9d53092	40	{
3566348b	41	const char *name = NULL;
8e2d6c9d DE	42	uint64_t sum;
	43	struct sr_resource bitstream;
	44	struct drv_context *drvc;
3566348b	45	struct dev_context *devc;
b9d53092	46	struct sr_usb_dev_inst *usb;
b9d53092	47	unsigned char *buf;
8e2d6c9d DE	48	ssize_t chunksize;
	49	int transferred;
	50	int result, ret;
cd189a44	51	const uint8_t cmd[3] = {0, 0, 0};
b9d53092	52
8e2d6c9d	53	drvc = sdi->driver->context;
3566348b	54	devc = sdi->priv;
b9d53092	55	usb = sdi->conn;
8e2d6c9d	56
3566348b	57	if (!strcmp(devc->profile->model, "DSLogic")) {
1ee70746	58	if (devc->cur_threshold < 1.40)
3566348b JH	59	name = DSLOGIC_FPGA_FIRMWARE_3V3;
	60	else
	61	name = DSLOGIC_FPGA_FIRMWARE_5V;
	62	} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
	63	name = DSLOGIC_PRO_FPGA_FIRMWARE;
	64	} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
	65	name = DSLOGIC_PLUS_FPGA_FIRMWARE;
	66	} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
	67	name = DSLOGIC_BASIC_FPGA_FIRMWARE;
	68	} else if (!strcmp(devc->profile->model, "DSCope")) {
	69	name = DSCOPE_FPGA_FIRMWARE;
	70	} else {
	71	sr_err("Failed to select FPGA firmware.");
	72	return SR_ERR;
	73	}
	74
8e2d6c9d DE	75	sr_dbg("Uploading FPGA firmware '%s'.", name);
	76
	77	result = sr_resource_open(drvc->sr_ctx, &bitstream,
	78	SR_RESOURCE_FIRMWARE, name);
	79	if (result != SR_OK)
	80	return result;
b9d53092 BV	81
	82	/* Tell the device firmware is coming. */
	83	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
9d71f815	84	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
d93c1470	85	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092	86	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
8e2d6c9d	87	sr_resource_close(drvc->sr_ctx, &bitstream);
b9d53092 BV	88	return SR_ERR;
	89	}
	90
	91	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	92	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092	93
8e2d6c9d	94	buf = g_malloc(FW_BUFSIZE);
b9d53092 BV	95	sum = 0;
	96	result = SR_OK;
	97	while (1) {
8e2d6c9d DE	98	chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
	99	buf, FW_BUFSIZE);
	100	if (chunksize < 0)
	101	result = SR_ERR;
	102	if (chunksize <= 0)
b9d53092 BV	103	break;
	104
	105	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	106	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	107	sr_err("Unable to configure FPGA firmware: %s.",
	108	libusb_error_name(ret));
	109	result = SR_ERR;
	110	break;
	111	}
	112	sum += transferred;
8e2d6c9d DE	113	sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
8e2d6c9d DE	114	sum, bitstream.size);
b9d53092 BV	115
	116	if (transferred != chunksize) {
	117	sr_err("Short transfer while uploading FPGA firmware.");
	118	result = SR_ERR;
	119	break;
	120	}
	121	}
b9d53092	122	g_free(buf);
8e2d6c9d DE	123	sr_resource_close(drvc->sr_ctx, &bitstream);
8e2d6c9d DE	124
b9d53092 BV	125	if (result == SR_OK)
	126	sr_dbg("FPGA firmware upload done.");
	127
	128	return result;
	129	}
	130
8e2d6c9d	131	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
b9d53092	132	{
b9d53092 BV	133	struct sr_usb_dev_inst *usb;
	134	struct dslogic_mode mode;
	135	int ret;
	136
adcb9951	137	mode.flags = DS_START_FLAGS_MODE_LA \| DS_START_FLAGS_SAMPLE_WIDE;
b9d53092	138	mode.sample_delay_h = mode.sample_delay_l = 0;
b9d53092 BV	139
	140	usb = sdi->conn;
	141	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	142	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	143	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	144	if (ret < 0) {
	145	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	146	return SR_ERR;
	147	}
	148
	149	return SR_OK;
	150	}
	151
8e2d6c9d	152	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	153	{
	154	struct sr_usb_dev_inst *usb;
	155	struct dslogic_mode mode;
	156	int ret;
	157
	158	mode.flags = DS_START_FLAGS_STOP;
	159	mode.sample_delay_h = mode.sample_delay_l = 0;
	160
	161	usb = sdi->conn;
	162	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	163	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	164	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	165	if (ret < 0) {
	166	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	167	return SR_ERR;
	168	}
	169
	170	return SR_OK;
	171	}
	172
3db03efa DA	173	/*
	174	* Get the session trigger and configure the FPGA structure
	175	* accordingly.
	176	*/
	177	static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	178	struct dslogic_fpga_config *cfg)
	179	{
	180	struct sr_trigger *trigger;
	181	struct sr_trigger_stage *stage;
	182	struct sr_trigger_match *match;
	183	struct dev_context *devc;
	184	const GSList l, m;
	185	int channelbit, i = 0;
	186	uint16_t v16;
	187
9803346f UH	188	devc = sdi->priv;
9803346f UH	189
e40ee26b JH	190	cfg->ch_en = 0;
	191	for (l = sdi->channels; l; l = l->next) {
	192	const struct sr_channel const probe = (struct sr_channel )l->data;
	193	cfg->ch_en \|= probe->enabled << probe->index;
	194	}
	195
3db03efa DA	196	cfg->trig_mask0[0] = 0xffff;
	197	cfg->trig_mask1[0] = 0xffff;
	198
	199	cfg->trig_value0[0] = 0;
	200	cfg->trig_value1[0] = 0;
	201
	202	cfg->trig_edge0[0] = 0;
	203	cfg->trig_edge1[0] = 0;
	204
	205	cfg->trig_logic0[0] = 0;
	206	cfg->trig_logic1[0] = 0;
	207
e40ee26b	208	cfg->trig_count[0] = 0;
3db03efa	209
4237fbca	210	cfg->trig_glb = 0;
4237fbca	211
adcb9951	212	for (i = 1; i < NUM_TRIGGER_STAGES; i++) {
4237fbca DA	213	cfg->trig_mask0[i] = 0xff;
	214	cfg->trig_mask1[i] = 0xff;
	215	cfg->trig_value0[i] = 0;
	216	cfg->trig_value1[i] = 0;
	217	cfg->trig_edge0[i] = 0;
	218	cfg->trig_edge1[i] = 0;
4237fbca DA	219	cfg->trig_logic0[i] = 2;
4237fbca DA	220	cfg->trig_logic1[i] = 2;
e40ee26b	221	cfg->trig_count[i] = 0;
4237fbca DA	222	}
	223
	224	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	225	sr_dbg("pos: %d", cfg->trig_pos);
	226
	227	sr_dbg("configuring trigger");
	228
9803346f	229	if (!(trigger = sr_session_trigger_get(sdi->session))) {
4237fbca	230	sr_dbg("No session trigger found");
3db03efa	231	return SR_OK;
4237fbca	232	}
3db03efa DA	233
	234	for (l = trigger->stages; l; l = l->next) {
	235	stage = l->data;
	236	for (m = stage->matches; m; m = m->next) {
	237	match = m->data;
	238	if (!match->channel->enabled)
	239	/* Ignore disabled channels with a trigger. */
	240	continue;
	241	channelbit = 1 << (match->channel->index);
3db03efa DA	242	/* Simple trigger support (event). */
	243	if (match->match == SR_TRIGGER_ONE) {
	244	cfg->trig_mask0[0] &= ~channelbit;
	245	cfg->trig_mask1[0] &= ~channelbit;
	246	cfg->trig_value0[0] \|= channelbit;
	247	cfg->trig_value1[0] \|= channelbit;
	248	} else if (match->match == SR_TRIGGER_ZERO) {
	249	cfg->trig_mask0[0] &= ~channelbit;
	250	cfg->trig_mask1[0] &= ~channelbit;
	251	} else if (match->match == SR_TRIGGER_FALLING) {
	252	cfg->trig_mask0[0] &= ~channelbit;
	253	cfg->trig_mask1[0] &= ~channelbit;
	254	cfg->trig_edge0[0] \|= channelbit;
	255	cfg->trig_edge1[0] \|= channelbit;
	256	} else if (match->match == SR_TRIGGER_RISING) {
	257	cfg->trig_mask0[0] &= ~channelbit;
	258	cfg->trig_mask1[0] &= ~channelbit;
	259	cfg->trig_value0[0] \|= channelbit;
	260	cfg->trig_value1[0] \|= channelbit;
	261	cfg->trig_edge0[0] \|= channelbit;
	262	cfg->trig_edge1[0] \|= channelbit;
9803346f	263	} else if (match->match == SR_TRIGGER_EDGE) {
3db03efa DA	264	cfg->trig_edge0[0] \|= channelbit;
	265	cfg->trig_edge1[0] \|= channelbit;
	266	}
	267	}
	268	}
9803346f	269
4237fbca DA	270	v16 = RL16(&cfg->mode);
	271	v16 \|= 1 << 0;
	272	WL16(&cfg->mode, v16);
9803346f	273
3db03efa DA	274	return SR_OK;
	275	}
	276
8e2d6c9d	277	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
b9d53092 BV	278	{
	279	struct dev_context *devc;
	280	struct sr_usb_dev_inst *usb;
	281	uint8_t c[3];
	282	struct dslogic_fpga_config cfg;
	283	uint16_t v16;
	284	uint32_t v32;
	285	int transferred, len, ret;
	286
	287	sr_dbg("Configuring FPGA.");
9803346f	288
b9d53092 BV	289	usb = sdi->conn;
	290	devc = sdi->priv;
	291
	292	WL32(&cfg.sync, DS_CFG_START);
	293	WL16(&cfg.mode_header, DS_CFG_MODE);
e40ee26b JH	294	WL16(&cfg.divider_header, DS_CFG_DIVIDER);
	295	WL16(&cfg.count_header, DS_CFG_COUNT);
	296	WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
b9d53092	297	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
e40ee26b JH	298	WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
e40ee26b JH	299	WL16(&cfg.trig_header, DS_CFG_TRIG);
b9d53092 BV	300	WL32(&cfg.end_sync, DS_CFG_END);
	301
	302	/* Pass in the length of a fixed-size struct. Really. */
	303	len = sizeof(struct dslogic_fpga_config) / 2;
	304	c[0] = len & 0xff;
	305	c[1] = (len >> 8) & 0xff;
	306	c[2] = (len >> 16) & 0xff;
	307
	308	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
e40ee26b JH	309	LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
e40ee26b JH	310	c, sizeof(c), USB_TIMEOUT);
b9d53092	311	if (ret < 0) {
9803346f UH	312	sr_err("Failed to send FPGA configure command: %s.",
9803346f UH	313	libusb_error_name(ret));
b9d53092 BV	314	return SR_ERR;
	315	}
	316
b9d53092	317	v16 = 0x0000;
e40ee26b	318
adcb9951	319	if (devc->mode == DS_OP_INTERNAL_TEST)
cf398cc0	320	v16 = DS_MODE_INT_TEST;
adcb9951	321	else if (devc->mode == DS_OP_EXTERNAL_TEST)
cf398cc0	322	v16 = DS_MODE_EXT_TEST;
adcb9951	323	else if (devc->mode == DS_OP_LOOPBACK_TEST)
cf398cc0	324	v16 = DS_MODE_LPB_TEST;
780c5e24 JH	325
	326	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
	327	v16 \|= DS_MODE_HALF_MODE;
	328	else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
	329	v16 \|= DS_MODE_QUAR_MODE;
	330
adcb9951	331	if (devc->continuous_mode)
cf398cc0	332	v16 \|= DS_MODE_STREAM_MODE;
adcb9951	333	if (devc->external_clock) {
cf398cc0	334	v16 \|= DS_MODE_CLK_TYPE;
adcb9951	335	if (devc->clock_edge == DS_EDGE_FALLING)
cf398cc0	336	v16 \|= DS_MODE_CLK_EDGE;
d9a58763	337	}
9803346f	338	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
176d785d	339	ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
adcb9951	340	&& !devc->continuous_mode) {
9803346f UH	341	/* Enable RLE for long captures.
	342	* Without this, captured data present errors.
	343	*/
cf398cc0	344	v16 \|= DS_MODE_RLE_MODE;
a9a9bfaa	345	}
3fc3fbe4	346
b9d53092	347	WL16(&cfg.mode, v16);
a04b28ce	348	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
b9d53092 BV	349	WL32(&cfg.divider, v32);
	350	WL32(&cfg.count, devc->limit_samples);
	351
3db03efa DA	352	dslogic_set_trigger(sdi, &cfg);
3db03efa DA	353
b9d53092 BV	354	len = sizeof(struct dslogic_fpga_config);
b9d53092 BV	355	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	356	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	357	if (ret < 0 \|\| transferred != len) {
	358	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	359	return SR_ERR;
	360	}
	361
	362	return SR_OK;
	363	}
a04b28ce	364
9803346f UH	365	static int to_bytes_per_ms(struct dev_context *devc)
9803346f UH	366	{
a04b28ce	367	if (devc->cur_samplerate > SR_MHZ(100))
adcb9951 JH	368	return SR_MHZ(100) / 1000 * 2;
adcb9951 JH	369	return devc->cur_samplerate / 1000 * 2;
a04b28ce DA	370	}
	371
	372	static size_t get_buffer_size(struct dev_context *devc)
	373	{
9803346f UH	374	size_t s;
	375
	376	/*
	377	* The buffer should be large enough to hold 10ms of data and
	378	* a multiple of 512.
	379	*/
	380	s = 10 * to_bytes_per_ms(devc);
	381	// s = to_bytes_per_ms(devc->cur_samplerate);
	382	return (s + 511) & ~511;
a04b28ce DA	383	}
a04b28ce DA	384
9803346f UH	385	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
9803346f UH	386	{
a04b28ce	387	unsigned int n;
9803346f	388
a04b28ce	389	/* Total buffer size should be able to hold about 100ms of data. */
9803346f	390	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
a04b28ce DA	391	sr_info("New calculation: %d", n);
	392
	393	if (n > NUM_SIMUL_TRANSFERS)
	394	return NUM_SIMUL_TRANSFERS;
	395
	396	return n;
	397	}