]> sigrok.org Git - libsigrok.git/blame - hardware/openbench-logic-sniffer/ols.c
Consistently use 'di' as variable name.
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
fe1c50fb
BV
45#define SERIALCOMM "115200/8n1"
46
915f7cc8 47static const int hwcaps[] = {
5a2326a7
UH
48 SR_HWCAP_LOGIC_ANALYZER,
49 SR_HWCAP_SAMPLERATE,
50 SR_HWCAP_CAPTURE_RATIO,
51 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 52 SR_HWCAP_RLE,
43fc7885 53 0,
a1bb33af
UH
54};
55
d261dbbf 56/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 57static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
58 "0",
59 "1",
60 "2",
61 "3",
62 "4",
63 "5",
64 "6",
65 "7",
66 "8",
67 "9",
68 "10",
69 "11",
70 "12",
71 "13",
72 "14",
73 "15",
74 "16",
75 "17",
76 "18",
77 "19",
78 "20",
79 "21",
80 "22",
81 "23",
82 "24",
83 "25",
84 "26",
85 "27",
86 "28",
87 "29",
88 "30",
89 "31",
90 NULL,
91};
92
4fe9a6da 93/* default supported samplerates, can be overridden by device metadata */
a533743d 94static const struct sr_samplerates samplerates = {
c9140419 95 SR_HZ(10),
59df0c77 96 SR_MHZ(200),
c9140419
UH
97 SR_HZ(1),
98 NULL,
a1bb33af
UH
99};
100
e5e81856 101SR_PRIV struct sr_dev_driver ols_driver_info;
a873c594 102static struct sr_dev_driver *di = &ols_driver_info;
a1bb33af 103
530f201e
BV
104static int send_shortcommand(struct sr_serial_dev_inst *serial,
105 uint8_t command)
a1bb33af
UH
106{
107 char buf[1];
108
b08024a8 109 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 110 buf[0] = command;
530f201e 111 if (serial_write(serial, buf, 1) != 1)
e46b8fb1 112 return SR_ERR;
a1bb33af 113
e46b8fb1 114 return SR_OK;
a1bb33af
UH
115}
116
530f201e
BV
117static int send_longcommand(struct sr_serial_dev_inst *serial,
118 uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
530f201e 128 if (serial_write(serial, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
014359e3 134static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 135{
014359e3 136 struct dev_context *devc;
1b79df2f
JH
137 const struct sr_probe *probe;
138 const GSList *l;
6937bb75 139 int probe_bit, stage, i;
a1bb33af
UH
140 char *tc;
141
014359e3
BV
142 devc = sdi->priv;
143
fefc4b85 144 devc->probe_mask = 0;
43fc7885 145 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
146 devc->trigger_mask[i] = 0;
147 devc->trigger_value[i] = 0;
a1bb33af
UH
148 }
149
fefc4b85 150 devc->num_stages = 0;
014359e3 151 for (l = sdi->probes; l; l = l->next) {
1b79df2f 152 probe = (const struct sr_probe *)l->data;
43fc7885 153 if (!probe->enabled)
6937bb75
BV
154 continue;
155
43fc7885
UH
156 /*
157 * Set up the probe mask for later configuration into the
158 * flag register.
159 */
b35c8293 160 probe_bit = 1 << (probe->index);
fefc4b85 161 devc->probe_mask |= probe_bit;
6937bb75 162
a803c0db 163 if (!probe->trigger)
6937bb75
BV
164 continue;
165
43fc7885 166 /* Configure trigger mask and value. */
6937bb75 167 stage = 0;
43fc7885 168 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 169 devc->trigger_mask[stage] |= probe_bit;
43fc7885 170 if (*tc == '1')
fefc4b85 171 devc->trigger_value[stage] |= probe_bit;
6937bb75 172 stage++;
43fc7885
UH
173 if (stage > 3)
174 /*
175 * TODO: Only supporting parallel mode, with
176 * up to 4 stages.
177 */
e46b8fb1 178 return SR_ERR;
a1bb33af 179 }
fefc4b85
BV
180 if (stage > devc->num_stages)
181 devc->num_stages = stage;
a1bb33af
UH
182 }
183
e46b8fb1 184 return SR_OK;
a1bb33af
UH
185}
186
a803c0db 187static uint32_t reverse16(uint32_t in)
6937bb75
BV
188{
189 uint32_t out;
190
a803c0db
BV
191 out = (in & 0xff) << 8;
192 out |= (in & 0xff00) >> 8;
193 out |= (in & 0xff0000) << 8;
194 out |= (in & 0xff000000) >> 8;
195
196 return out;
197}
198
199static uint32_t reverse32(uint32_t in)
200{
201 uint32_t out;
202
203 out = (in & 0xff) << 24;
204 out |= (in & 0xff00) << 8;
205 out |= (in & 0xff0000) >> 8;
206 out |= (in & 0xff000000) >> 24;
207
208 return out;
6937bb75
BV
209}
210
fefc4b85 211static struct dev_context *ols_dev_new(void)
4fe9a6da 212{
fefc4b85 213 struct dev_context *devc;
4fe9a6da 214
fefc4b85
BV
215 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
216 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
217 return NULL;
218 }
219
fefc4b85
BV
220 devc->trigger_at = -1;
221 devc->probe_mask = 0xffffffff;
222 devc->cur_samplerate = SR_KHZ(200);
223 devc->serial = NULL;
4fe9a6da 224
fefc4b85 225 return devc;
4fe9a6da
BV
226}
227
530f201e 228static struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial)
4fe9a6da 229{
d68e2d1a 230 struct sr_dev_inst *sdi;
fefc4b85 231 struct dev_context *devc;
10e5cbed
BV
232 struct sr_probe *probe;
233 uint32_t tmp_int, ui;
4fe9a6da 234 uint8_t key, type, token;
bb7ef793 235 GString *tmp_str, *devname, *version;
10e5cbed 236 guchar tmp_c;
4fe9a6da 237
d3683c42 238 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
a873c594 239 sdi->driver = di;
fefc4b85
BV
240 devc = ols_dev_new();
241 sdi->priv = devc;
4fe9a6da 242
bb7ef793 243 devname = g_string_new("");
4fe9a6da
BV
244 version = g_string_new("");
245
246 key = 0xff;
247 while (key) {
530f201e 248 if (serial_read(serial, &key, 1) != 1 || key == 0x00)
4fe9a6da
BV
249 break;
250 type = key >> 5;
251 token = key & 0x1f;
252 switch (type) {
253 case 0:
254 /* NULL-terminated string */
255 tmp_str = g_string_new("");
530f201e 256 while (serial_read(serial, &tmp_c, 1) == 1 && tmp_c != '\0')
4fe9a6da 257 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
258 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
259 key, tmp_str->str);
4fe9a6da
BV
260 switch (token) {
261 case 0x01:
262 /* Device name */
bb7ef793 263 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
264 break;
265 case 0x02:
266 /* FPGA firmware version */
267 if (version->len)
268 g_string_append(version, ", ");
269 g_string_append(version, "FPGA version ");
270 g_string_append(version, tmp_str->str);
271 break;
272 case 0x03:
273 /* Ancillary version */
274 if (version->len)
275 g_string_append(version, ", ");
276 g_string_append(version, "Ancillary version ");
277 g_string_append(version, tmp_str->str);
278 break;
279 default:
b08024a8
UH
280 sr_info("ols: unknown token 0x%.2x: '%s'",
281 token, tmp_str->str);
4fe9a6da
BV
282 break;
283 }
284 g_string_free(tmp_str, TRUE);
285 break;
286 case 1:
287 /* 32-bit unsigned integer */
530f201e 288 if (serial_read(serial, &tmp_int, 4) != 4)
4fe9a6da
BV
289 break;
290 tmp_int = reverse32(tmp_int);
b08024a8
UH
291 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
292 key, tmp_int);
4fe9a6da
BV
293 switch (token) {
294 case 0x00:
295 /* Number of usable probes */
10e5cbed
BV
296 for (ui = 0; ui < tmp_int; ui++) {
297 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
298 probe_names[ui])))
299 return 0;
300 sdi->probes = g_slist_append(sdi->probes, probe);
301 }
4fe9a6da
BV
302 break;
303 case 0x01:
304 /* Amount of sample memory available (bytes) */
fefc4b85 305 devc->max_samples = tmp_int;
4fe9a6da
BV
306 break;
307 case 0x02:
308 /* Amount of dynamic memory available (bytes) */
309 /* what is this for? */
310 break;
311 case 0x03:
312 /* Maximum sample rate (hz) */
fefc4b85 313 devc->max_samplerate = tmp_int;
4fe9a6da
BV
314 break;
315 case 0x04:
316 /* protocol version */
fefc4b85 317 devc->protocol_version = tmp_int;
4fe9a6da
BV
318 break;
319 default:
b08024a8
UH
320 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
321 token, tmp_int);
4fe9a6da
BV
322 break;
323 }
324 break;
325 case 2:
326 /* 8-bit unsigned integer */
530f201e 327 if (serial_read(serial, &tmp_c, 1) != 1)
4fe9a6da 328 break;
b08024a8
UH
329 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
330 key, tmp_c);
4fe9a6da
BV
331 switch (token) {
332 case 0x00:
333 /* Number of usable probes */
10e5cbed
BV
334 for (ui = 0; ui < tmp_c; ui++) {
335 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
336 probe_names[ui])))
337 return 0;
338 sdi->probes = g_slist_append(sdi->probes, probe);
339 }
4fe9a6da
BV
340 break;
341 case 0x01:
342 /* protocol version */
fefc4b85 343 devc->protocol_version = tmp_c;
4fe9a6da
BV
344 break;
345 default:
b08024a8
UH
346 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
347 token, tmp_c);
4fe9a6da
BV
348 break;
349 }
350 break;
351 default:
352 /* unknown type */
353 break;
354 }
355 }
356
bb7ef793 357 sdi->model = devname->str;
4fe9a6da 358 sdi->version = version->str;
bb7ef793 359 g_string_free(devname, FALSE);
4fe9a6da
BV
360 g_string_free(version, FALSE);
361
362 return sdi;
363}
364
34f06b90 365static int hw_init(struct sr_context *sr_ctx)
61136ea6 366{
fefc4b85 367 struct drv_context *drvc;
61136ea6 368
fefc4b85
BV
369 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
370 sr_err("ols: driver context malloc failed.");
886a52b6 371 return SR_ERR_MALLOC;
fefc4b85 372 }
1ebe4b4e 373 drvc->sr_ctx = sr_ctx;
a873c594 374 di->priv = drvc;
61136ea6
BV
375
376 return SR_OK;
377}
378
10e5cbed 379static GSList *hw_scan(GSList *options)
a1bb33af 380{
a99e0d2a 381 struct sr_hwopt *opt;
d68e2d1a 382 struct sr_dev_inst *sdi;
fefc4b85
BV
383 struct drv_context *drvc;
384 struct dev_context *devc;
10e5cbed 385 struct sr_probe *probe;
530f201e 386 struct sr_serial_dev_inst *serial;
a99e0d2a 387 GPollFD probefd;
fe1c50fb 388 GSList *l, *devices;
530f201e 389 int ret, i;
fe1c50fb 390 const char *conn, *serialcomm;
a99e0d2a 391 char buf[8];
a1bb33af 392
10e5cbed 393 (void)options;
a873c594 394 drvc = di->priv;
10e5cbed 395 devices = NULL;
c0a4b971 396
a99e0d2a
AG
397 conn = serialcomm = NULL;
398 for (l = options; l; l = l->next) {
399 opt = l->data;
400 switch (opt->hwopt) {
401 case SR_HWOPT_CONN:
402 conn = opt->value;
403 break;
404 case SR_HWOPT_SERIALCOMM:
405 serialcomm = opt->value;
406 break;
407 }
408 }
90165efe 409 if (!conn)
a99e0d2a 410 return NULL;
c0a4b971 411
fe1c50fb 412 if (serialcomm == NULL)
530f201e
BV
413 serialcomm = SERIALCOMM;
414
415 if (!(serial = sr_serial_dev_inst_new(conn, serialcomm)))
416 return NULL;
c0a4b971 417
a99e0d2a
AG
418 /* The discovery procedure is like this: first send the Reset
419 * command (0x00) 5 times, since the device could be anywhere
420 * in a 5-byte command. Then send the ID command (0x02).
421 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
422 * have a match.
a99e0d2a
AG
423 */
424 sr_info("ols: probing %s .", conn);
a54dd31e 425 if (serial_open(serial, SERIAL_RDWR | SERIAL_NONBLOCK) != SR_OK)
a99e0d2a 426 return NULL;
c0a4b971 427
a99e0d2a
AG
428 ret = SR_OK;
429 for (i = 0; i < 5; i++) {
530f201e 430 if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
a99e0d2a 431 sr_err("ols: port %s is not writable.", conn);
fe1c50fb 432 break;
a1bb33af
UH
433 }
434 }
a99e0d2a 435 if (ret != SR_OK) {
530f201e 436 serial_close(serial);
a99e0d2a
AG
437 sr_err("ols: Could not use port %s. Quitting.", conn);
438 return NULL;
439 }
530f201e 440 send_shortcommand(serial, CMD_ID);
a1bb33af 441
fe1c50fb 442 /* Wait 10ms for a response. */
5b15b41e 443 usleep(10000);
a1bb33af 444
530f201e 445 probefd.fd = serial->fd;
fe1c50fb
BV
446 probefd.events = G_IO_IN;
447 g_poll(&probefd, 1, 1);
4fe9a6da 448
a99e0d2a
AG
449 if (probefd.revents != G_IO_IN)
450 return NULL;
530f201e 451 if (serial_read(serial, buf, 4) != 4)
a99e0d2a
AG
452 return NULL;
453 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
454 return NULL;
4fe9a6da 455
fe1c50fb
BV
456 /* Definitely using the OLS protocol, check if it supports
457 * the metadata command.
a99e0d2a 458 */
530f201e 459 send_shortcommand(serial, CMD_METADATA);
a99e0d2a 460 if (g_poll(&probefd, 1, 10) > 0) {
fe1c50fb 461 /* Got metadata. */
530f201e 462 sdi = get_metadata(serial);
fe1c50fb 463 sdi->index = 0;
a99e0d2a
AG
464 devc = sdi->priv;
465 } else {
fe1c50fb
BV
466 /* Not an OLS -- some other board that uses the sump protocol. */
467 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE,
a99e0d2a 468 "Sump", "Logic Analyzer", "v1.0");
a873c594 469 sdi->driver = di;
a99e0d2a
AG
470 devc = ols_dev_new();
471 for (i = 0; i < 32; i++) {
472 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
473 probe_names[i])))
474 return 0;
475 sdi->probes = g_slist_append(sdi->probes, probe);
a1bb33af 476 }
a99e0d2a 477 sdi->priv = devc;
4fe9a6da 478 }
530f201e 479 devc->serial = serial;
a99e0d2a
AG
480 drvc->instances = g_slist_append(drvc->instances, sdi);
481 devices = g_slist_append(devices, sdi);
482
530f201e 483 serial_close(serial);
a1bb33af 484
10e5cbed 485 return devices;
a1bb33af
UH
486}
487
811deee4
BV
488static GSList *hw_dev_list(void)
489{
490 struct drv_context *drvc;
491
a873c594 492 drvc = di->priv;
811deee4
BV
493
494 return drvc->instances;
495}
496
25a0f108 497static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 498{
fefc4b85 499 struct dev_context *devc;
a1bb33af 500
fefc4b85 501 devc = sdi->priv;
69890f73 502
a54dd31e 503 if (serial_open(devc->serial, SERIAL_RDWR) != SR_OK)
e46b8fb1 504 return SR_ERR;
a1bb33af 505
5a2326a7 506 sdi->status = SR_ST_ACTIVE;
a1bb33af 507
e46b8fb1 508 return SR_OK;
a1bb33af
UH
509}
510
25a0f108 511static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 512{
fefc4b85 513 struct dev_context *devc;
a1bb33af 514
fefc4b85 515 devc = sdi->priv;
69890f73 516
530f201e
BV
517 if (devc->serial && devc->serial->fd != -1) {
518 serial_close(devc->serial);
5a2326a7 519 sdi->status = SR_ST_INACTIVE;
a1bb33af 520 }
697785d1
UH
521
522 return SR_OK;
a1bb33af
UH
523}
524
57ab7d9f 525static int hw_cleanup(void)
a1bb33af
UH
526{
527 GSList *l;
d68e2d1a 528 struct sr_dev_inst *sdi;
fefc4b85
BV
529 struct drv_context *drvc;
530 struct dev_context *devc;
57ab7d9f 531 int ret = SR_OK;
a1bb33af 532
a873c594 533 if (!(drvc = di->priv))
fefc4b85
BV
534 return SR_OK;
535
8722c31e 536 /* Properly close and free all devices. */
fefc4b85 537 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
538 if (!(sdi = l->data)) {
539 /* Log error, but continue cleaning up the rest. */
540 sr_err("ols: %s: sdi was NULL, continuing", __func__);
541 ret = SR_ERR_BUG;
542 continue;
543 }
fefc4b85 544 if (!(devc = sdi->priv)) {
57ab7d9f
UH
545 /* Log error, but continue cleaning up the rest. */
546 sr_err("ols: %s: sdi->priv was NULL, continuing",
547 __func__);
548 ret = SR_ERR_BUG;
549 continue;
550 }
530f201e 551 hw_dev_close(sdi);
fefc4b85 552 sr_serial_dev_inst_free(devc->serial);
d3683c42 553 sr_dev_inst_free(sdi);
a1bb33af 554 }
fefc4b85
BV
555 g_slist_free(drvc->instances);
556 drvc->instances = NULL;
57ab7d9f
UH
557
558 return ret;
a1bb33af
UH
559}
560
dddfb3db
BV
561static int hw_info_get(int info_id, const void **data,
562 const struct sr_dev_inst *sdi)
a1bb33af 563{
fefc4b85 564 struct dev_context *devc;
a1bb33af 565
dddfb3db 566 switch (info_id) {
2ca4465b
BV
567 case SR_DI_HWCAPS:
568 *data = hwcaps;
569 break;
5a2326a7 570 case SR_DI_NUM_PROBES:
dddfb3db 571 *data = GINT_TO_POINTER(1);
a1bb33af 572 break;
464d12c7 573 case SR_DI_PROBE_NAMES:
dddfb3db 574 *data = probe_names;
464d12c7 575 break;
5a2326a7 576 case SR_DI_SAMPLERATES:
dddfb3db 577 *data = &samplerates;
a1bb33af 578 break;
5a2326a7 579 case SR_DI_TRIGGER_TYPES:
dddfb3db 580 *data = (char *)TRIGGER_TYPES;
a1bb33af 581 break;
5a2326a7 582 case SR_DI_CUR_SAMPLERATE:
dddfb3db 583 if (sdi) {
fefc4b85
BV
584 devc = sdi->priv;
585 *data = &devc->cur_samplerate;
dddfb3db
BV
586 } else
587 return SR_ERR;
a1bb33af 588 break;
dddfb3db
BV
589 default:
590 return SR_ERR_ARG;
a1bb33af
UH
591 }
592
dddfb3db 593 return SR_OK;
a1bb33af
UH
594}
595
6f4b1868 596static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 597{
fefc4b85 598 struct dev_context *devc;
a1bb33af 599
fefc4b85
BV
600 devc = sdi->priv;
601 if (devc->max_samplerate) {
602 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
603 return SR_ERR_SAMPLERATE;
604 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 605 return SR_ERR_SAMPLERATE;
a1bb33af 606
43fc7885 607 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
608 devc->flag_reg |= FLAG_DEMUX;
609 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 610 } else {
fefc4b85
BV
611 devc->flag_reg &= ~FLAG_DEMUX;
612 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 613 }
a1bb33af 614
7583b99d
GM
615 /* Calculate actual samplerate used and complain if it is different
616 * from the requested.
617 */
fefc4b85
BV
618 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
619 if (devc->flag_reg & FLAG_DEMUX)
620 devc->cur_samplerate *= 2;
621 if (devc->cur_samplerate != samplerate)
133a37bf 622 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 623 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 624
e46b8fb1 625 return SR_OK;
a1bb33af
UH
626}
627
6f4b1868
BV
628static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
629 const void *value)
a1bb33af 630{
fefc4b85 631 struct dev_context *devc;
a1bb33af 632 int ret;
1b79df2f 633 const uint64_t *tmp_u64;
a1bb33af 634
fefc4b85 635 devc = sdi->priv;
a1bb33af 636
5a2326a7 637 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 638 return SR_ERR;
a1bb33af 639
ffedd0bf 640 switch (hwcap) {
5a2326a7 641 case SR_HWCAP_SAMPLERATE:
1b79df2f 642 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 643 break;
5a2326a7 644 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 645 tmp_u64 = value;
574ce498 646 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 647 return SR_ERR;
fefc4b85 648 if (*tmp_u64 > devc->max_samples)
133a37bf 649 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
650 devc->limit_samples = *tmp_u64;
651 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 652 ret = SR_OK;
a803c0db 653 break;
5a2326a7 654 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
655 devc->capture_ratio = *(const uint64_t *)value;
656 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
657 devc->capture_ratio = 0;
e46b8fb1 658 ret = SR_ERR;
43fc7885 659 } else
e46b8fb1 660 ret = SR_OK;
a803c0db 661 break;
3a4d09c0 662 case SR_HWCAP_RLE:
4d436e71 663 if (GPOINTER_TO_INT(value)) {
3a4d09c0 664 sr_info("ols: enabling RLE");
fefc4b85 665 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
666 }
667 ret = SR_OK;
668 break;
a803c0db 669 default:
e46b8fb1 670 ret = SR_ERR;
43fc7885 671 }
a1bb33af
UH
672
673 return ret;
674}
675
26bf9d56
BV
676static void abort_acquisition(const struct sr_dev_inst *sdi)
677{
678 struct sr_datafeed_packet packet;
679 struct dev_context *devc;
680
681 devc = sdi->priv;
682 sr_source_remove(devc->serial->fd);
683
684 /* Terminate session */
685 packet.type = SR_DF_END;
686 sr_session_send(sdi, &packet);
687
688}
689
690
691
1f9813eb 692static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 693{
b9c735a2 694 struct sr_datafeed_packet packet;
9c939c51 695 struct sr_datafeed_logic logic;
d68e2d1a 696 struct sr_dev_inst *sdi;
fefc4b85
BV
697 struct drv_context *drvc;
698 struct dev_context *devc;
4fe9a6da 699 GSList *l;
3a4d09c0
GM
700 int num_channels, offset, i, j;
701 unsigned char byte;
a1bb33af 702
a873c594 703 drvc = di->priv;
fefc4b85
BV
704
705 /* Find this device's devc struct by its fd. */
706 devc = NULL;
707 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 708 sdi = l->data;
fefc4b85 709 devc = sdi->priv;
530f201e 710 if (devc->serial->fd == fd)
4fe9a6da 711 break;
fefc4b85 712 devc = NULL;
4fe9a6da 713 }
fefc4b85 714 if (!devc)
ea9cfed7 715 /* Shouldn't happen. */
4fe9a6da
BV
716 return TRUE;
717
fefc4b85 718 if (devc->num_transfers++ == 0) {
43fc7885
UH
719 /*
720 * First time round, means the device started sending data,
721 * and will not stop until done. If it stops sending for
722 * longer than it takes to send a byte, that means it's
723 * finished. We'll double that to 30ms to be sure...
a1bb33af 724 */
6f1be0a2 725 sr_source_remove(fd);
1f9813eb 726 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
886a52b6 727 /* TODO: Check malloc return code. */
fefc4b85
BV
728 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
729 if (!devc->raw_sample_buf) {
730 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
731 __func__);
732 return FALSE;
733 }
a803c0db 734 /* fill with 1010... for debugging */
fefc4b85 735 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
736 }
737
6937bb75 738 num_channels = 0;
43fc7885 739 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 740 if ((devc->flag_reg & i) == 0)
6937bb75 741 num_channels++;
43fc7885 742 }
6937bb75 743
3a4d09c0 744 if (revents == G_IO_IN) {
530f201e 745 if (serial_read(devc->serial, &byte, 1) != 1)
a1bb33af
UH
746 return FALSE;
747
baf1d714 748 /* Ignore it if we've read enough. */
fefc4b85 749 if (devc->num_samples >= devc->limit_samples)
baf1d714 750 return TRUE;
3a4d09c0 751
fefc4b85 752 devc->sample[devc->num_bytes++] = byte;
b08024a8 753 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 754 if (devc->num_bytes == num_channels) {
43fc7885 755 /* Got a full sample. */
b08024a8 756 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
757 devc->num_bytes * 2, *(int *)devc->sample);
758 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
759 /*
760 * In RLE mode -1 should never come in as a
761 * sample, because bit 31 is the "count" flag.
43fc7885 762 */
fefc4b85
BV
763 if (devc->sample[devc->num_bytes - 1] & 0x80) {
764 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
765 /*
766 * FIXME: This will only work on
767 * little-endian systems.
a1bb33af 768 */
fefc4b85
BV
769 devc->rle_count = *(int *)(devc->sample);
770 sr_dbg("ols: RLE count = %d", devc->rle_count);
771 devc->num_bytes = 0;
3a4d09c0 772 return TRUE;
baf1d714 773 }
3a4d09c0 774 }
fefc4b85
BV
775 devc->num_samples += devc->rle_count + 1;
776 if (devc->num_samples > devc->limit_samples) {
baf1d714 777 /* Save us from overrunning the buffer. */
fefc4b85
BV
778 devc->rle_count -= devc->num_samples - devc->limit_samples;
779 devc->num_samples = devc->limit_samples;
a1bb33af
UH
780 }
781
43fc7885
UH
782 if (num_channels < 4) {
783 /*
784 * Some channel groups may have been turned
785 * off, to speed up transfer between the
786 * hardware and the PC. Expand that here before
787 * submitting it over the session bus --
788 * whatever is listening on the bus will be
789 * expecting a full 32-bit sample, based on
790 * the number of probes.
6937bb75
BV
791 */
792 j = 0;
fefc4b85 793 memset(devc->tmp_sample, 0, 4);
43fc7885 794 for (i = 0; i < 4; i++) {
fefc4b85 795 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
796 /*
797 * This channel group was
798 * enabled, copy from received
799 * sample.
800 */
fefc4b85 801 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
802 }
803 }
fefc4b85
BV
804 memcpy(devc->sample, devc->tmp_sample, 4);
805 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
806 }
807
a803c0db
BV
808 /* the OLS sends its sample buffer backwards.
809 * store it in reverse order here, so we can dump
810 * this on the session bus later.
811 */
fefc4b85
BV
812 offset = (devc->limit_samples - devc->num_samples) * 4;
813 for (i = 0; i <= devc->rle_count; i++) {
814 memcpy(devc->raw_sample_buf + offset + (i * 4),
815 devc->sample, 4);
baf1d714 816 }
fefc4b85
BV
817 memset(devc->sample, 0, 4);
818 devc->num_bytes = 0;
819 devc->rle_count = 0;
a1bb33af 820 }
43fc7885
UH
821 } else {
822 /*
823 * This is the main loop telling us a timeout was reached, or
824 * we've acquired all the samples we asked for -- we're done.
a803c0db 825 * Send the (properly-ordered) buffer to the frontend.
43fc7885 826 */
fefc4b85 827 if (devc->trigger_at != -1) {
a803c0db
BV
828 /* a trigger was set up, so we need to tell the frontend
829 * about it.
830 */
fefc4b85 831 if (devc->trigger_at > 0) {
a803c0db 832 /* there are pre-trigger samples, send those first */
5a2326a7 833 packet.type = SR_DF_LOGIC;
9c939c51 834 packet.payload = &logic;
fefc4b85 835 logic.length = devc->trigger_at * 4;
9c939c51 836 logic.unitsize = 4;
fefc4b85
BV
837 logic.data = devc->raw_sample_buf +
838 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 839 sr_session_send(cb_data, &packet);
a803c0db
BV
840 }
841
9c939c51 842 /* send the trigger */
5a2326a7 843 packet.type = SR_DF_TRIGGER;
1f9813eb 844 sr_session_send(cb_data, &packet);
a803c0db 845
9c939c51 846 /* send post-trigger samples */
5a2326a7 847 packet.type = SR_DF_LOGIC;
9c939c51 848 packet.payload = &logic;
fefc4b85 849 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 850 logic.unitsize = 4;
fefc4b85
BV
851 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
852 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 853 sr_session_send(cb_data, &packet);
a803c0db 854 } else {
9c939c51 855 /* no trigger was used */
5a2326a7 856 packet.type = SR_DF_LOGIC;
9c939c51 857 packet.payload = &logic;
fefc4b85 858 logic.length = devc->num_samples * 4;
9c939c51 859 logic.unitsize = 4;
fefc4b85
BV
860 logic.data = devc->raw_sample_buf +
861 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 862 sr_session_send(cb_data, &packet);
a803c0db 863 }
fefc4b85 864 g_free(devc->raw_sample_buf);
a803c0db 865
530f201e 866 serial_flush(devc->serial);
26bf9d56 867 abort_acquisition(sdi);
530f201e 868 serial_close(devc->serial);
a1bb33af
UH
869 }
870
871 return TRUE;
872}
873
5d9ed643
BV
874static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
875 void *cb_data)
a1bb33af 876{
b9c735a2
UH
877 struct sr_datafeed_packet *packet;
878 struct sr_datafeed_header *header;
f366e86c 879 struct sr_datafeed_meta_logic meta;
fefc4b85 880 struct dev_context *devc;
a803c0db 881 uint32_t trigger_config[4];
a1bb33af 882 uint32_t data;
6937bb75
BV
883 uint16_t readcount, delaycount;
884 uint8_t changrp_mask;
22130421 885 int num_channels;
4fe9a6da 886 int i;
a1bb33af 887
fefc4b85 888 devc = sdi->priv;
a1bb33af 889
5a2326a7 890 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 891 return SR_ERR;
a1bb33af 892
014359e3
BV
893 if (configure_probes(sdi) != SR_OK) {
894 sr_err("ols: failed to configured probes");
895 return SR_ERR;
896 }
897
22130421
GM
898 /*
899 * Enable/disable channel groups in the flag register according to the
baf1d714 900 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
901 * to limit readcount.
902 */
903 changrp_mask = 0;
904 num_channels = 0;
905 for (i = 0; i < 4; i++) {
fefc4b85 906 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
907 changrp_mask |= (1 << i);
908 num_channels++;
909 }
910 }
911
baf1d714
UH
912 /*
913 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
914 * buffer.
915 */
fefc4b85 916 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
917
918 memset(trigger_config, 0, 16);
fefc4b85
BV
919 trigger_config[devc->num_stages - 1] |= 0x08;
920 if (devc->trigger_mask[0]) {
921 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
922 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 923
530f201e 924 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 925 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 926 return SR_ERR;
530f201e 927 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 928 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 929 return SR_ERR;
530f201e 930 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
931 trigger_config[0]) != SR_OK)
932 return SR_ERR;
6937bb75 933
530f201e 934 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_1,
fefc4b85 935 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 936 return SR_ERR;
530f201e 937 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_1,
fefc4b85 938 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 939 return SR_ERR;
530f201e 940 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
941 trigger_config[1]) != SR_OK)
942 return SR_ERR;
6937bb75 943
530f201e 944 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_2,
fefc4b85 945 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 946 return SR_ERR;
530f201e 947 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_2,
fefc4b85 948 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 949 return SR_ERR;
530f201e 950 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
951 trigger_config[2]) != SR_OK)
952 return SR_ERR;
a803c0db 953
530f201e 954 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_3,
fefc4b85 955 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 956 return SR_ERR;
530f201e 957 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_3,
fefc4b85 958 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 959 return SR_ERR;
530f201e 960 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
961 trigger_config[3]) != SR_OK)
962 return SR_ERR;
6937bb75 963 } else {
530f201e 964 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 965 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 966 return SR_ERR;
530f201e 967 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 968 devc->trigger_value[0]) != SR_OK)
e46b8fb1 969 return SR_ERR;
530f201e 970 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
971 0x00000008) != SR_OK)
972 return SR_ERR;
a803c0db 973 delaycount = readcount;
6937bb75 974 }
a1bb33af 975
b08024a8 976 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
977 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
978 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
530f201e 979 if (send_longcommand(devc->serial, CMD_SET_DIVIDER,
fefc4b85 980 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 981 return SR_ERR;
a1bb33af 982
43fc7885 983 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
984 data = ((readcount - 1) & 0xffff) << 16;
985 data |= (delaycount - 1) & 0xffff;
530f201e 986 if (send_longcommand(devc->serial, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 987 return SR_ERR;
a1bb33af 988
43fc7885 989 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
990 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
991 devc->flag_reg |= FLAG_FILTER;
992 devc->rle_count = 0;
993 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
530f201e 994 if (send_longcommand(devc->serial, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 995 return SR_ERR;
a1bb33af 996
43fc7885 997 /* Start acquisition on the device. */
530f201e 998 if (send_shortcommand(devc->serial, CMD_RUN) != SR_OK)
e46b8fb1 999 return SR_ERR;
a1bb33af 1000
fefc4b85 1001 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1002 cb_data);
a1bb33af 1003
b53738ba
UH
1004 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1005 sr_err("ols: %s: packet malloc failed", __func__);
1006 return SR_ERR_MALLOC;
1007 }
1008
1009 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1010 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1011 g_free(packet);
b53738ba
UH
1012 return SR_ERR_MALLOC;
1013 }
1014
43fc7885 1015 /* Send header packet to the session bus. */
5a2326a7 1016 packet->type = SR_DF_HEADER;
43fc7885 1017 packet->payload = (unsigned char *)header;
a1bb33af
UH
1018 header->feed_version = 1;
1019 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1020 sr_session_send(cb_data, packet);
1021
1022 /* Send metadata about the SR_DF_LOGIC packets to come. */
1023 packet->type = SR_DF_META_LOGIC;
1024 packet->payload = &meta;
fefc4b85 1025 meta.samplerate = devc->cur_samplerate;
f366e86c 1026 meta.num_probes = NUM_PROBES;
3cd3a20b 1027 sr_session_send(cb_data, packet);
c0a4b971 1028
a1bb33af
UH
1029 g_free(header);
1030 g_free(packet);
1031
e46b8fb1 1032 return SR_OK;
a1bb33af
UH
1033}
1034
3cd3a20b 1035/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
69b07d14 1036static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
a1bb33af 1037{
17e1afcb 1038 /* Avoid compiler warnings. */
26bf9d56 1039 (void)cb_data;
afc8e4de 1040
26bf9d56 1041 abort_acquisition(sdi);
3010f21c
UH
1042
1043 return SR_OK;
a1bb33af
UH
1044}
1045
c09f0b57 1046SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1047 .name = "ols",
1048 .longname = "Openbench Logic Sniffer",
1049 .api_version = 1,
1050 .init = hw_init,
1051 .cleanup = hw_cleanup,
61136ea6 1052 .scan = hw_scan,
811deee4
BV
1053 .dev_list = hw_dev_list,
1054 .dev_clear = hw_cleanup,
e7eb703f
UH
1055 .dev_open = hw_dev_open,
1056 .dev_close = hw_dev_close,
dddfb3db 1057 .info_get = hw_info_get,
a9a245b4 1058 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1059 .dev_acquisition_start = hw_dev_acquisition_start,
1060 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1061 .priv = NULL,
a1bb33af 1062};