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sr/drivers: obsolete SR_HWCAP_PROBECONFIG
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
915f7cc8 49static const int hwcaps[] = {
5a2326a7
UH
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 54 SR_HWCAP_RLE,
43fc7885 55 0,
a1bb33af
UH
56};
57
d261dbbf 58/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 59static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
4fe9a6da 95/* default supported samplerates, can be overridden by device metadata */
a533743d 96static const struct sr_samplerates samplerates = {
c9140419 97 SR_HZ(10),
59df0c77 98 SR_MHZ(200),
c9140419
UH
99 SR_HZ(1),
100 NULL,
a1bb33af
UH
101};
102
e5e81856
BV
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 105
6937bb75 106static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
107{
108 char buf[1];
109
b08024a8 110 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 111 buf[0] = command;
2119ab03 112 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 113 return SR_ERR;
a1bb33af 114
e46b8fb1 115 return SR_OK;
a1bb33af
UH
116}
117
6937bb75 118static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
2119ab03 128 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
014359e3 134static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 135{
014359e3 136 struct dev_context *devc;
1b79df2f
JH
137 const struct sr_probe *probe;
138 const GSList *l;
6937bb75 139 int probe_bit, stage, i;
a1bb33af
UH
140 char *tc;
141
014359e3
BV
142 devc = sdi->priv;
143
fefc4b85 144 devc->probe_mask = 0;
43fc7885 145 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
146 devc->trigger_mask[i] = 0;
147 devc->trigger_value[i] = 0;
a1bb33af
UH
148 }
149
fefc4b85 150 devc->num_stages = 0;
014359e3 151 for (l = sdi->probes; l; l = l->next) {
1b79df2f 152 probe = (const struct sr_probe *)l->data;
43fc7885 153 if (!probe->enabled)
6937bb75
BV
154 continue;
155
43fc7885
UH
156 /*
157 * Set up the probe mask for later configuration into the
158 * flag register.
159 */
b35c8293 160 probe_bit = 1 << (probe->index);
fefc4b85 161 devc->probe_mask |= probe_bit;
6937bb75 162
a803c0db 163 if (!probe->trigger)
6937bb75
BV
164 continue;
165
43fc7885 166 /* Configure trigger mask and value. */
6937bb75 167 stage = 0;
43fc7885 168 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 169 devc->trigger_mask[stage] |= probe_bit;
43fc7885 170 if (*tc == '1')
fefc4b85 171 devc->trigger_value[stage] |= probe_bit;
6937bb75 172 stage++;
43fc7885
UH
173 if (stage > 3)
174 /*
175 * TODO: Only supporting parallel mode, with
176 * up to 4 stages.
177 */
e46b8fb1 178 return SR_ERR;
a1bb33af 179 }
fefc4b85
BV
180 if (stage > devc->num_stages)
181 devc->num_stages = stage;
a1bb33af
UH
182 }
183
e46b8fb1 184 return SR_OK;
a1bb33af
UH
185}
186
a803c0db 187static uint32_t reverse16(uint32_t in)
6937bb75
BV
188{
189 uint32_t out;
190
a803c0db
BV
191 out = (in & 0xff) << 8;
192 out |= (in & 0xff00) >> 8;
193 out |= (in & 0xff0000) << 8;
194 out |= (in & 0xff000000) >> 8;
195
196 return out;
197}
198
199static uint32_t reverse32(uint32_t in)
200{
201 uint32_t out;
202
203 out = (in & 0xff) << 24;
204 out |= (in & 0xff00) << 8;
205 out |= (in & 0xff0000) >> 8;
206 out |= (in & 0xff000000) >> 24;
207
208 return out;
6937bb75
BV
209}
210
fefc4b85 211static struct dev_context *ols_dev_new(void)
4fe9a6da 212{
fefc4b85 213 struct dev_context *devc;
4fe9a6da 214
fefc4b85
BV
215 /* TODO: Is 'devc' ever g_free()'d? */
216 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
217 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
218 return NULL;
219 }
220
fefc4b85
BV
221 devc->trigger_at = -1;
222 devc->probe_mask = 0xffffffff;
223 devc->cur_samplerate = SR_KHZ(200);
224 devc->serial = NULL;
4fe9a6da 225
fefc4b85 226 return devc;
4fe9a6da
BV
227}
228
d68e2d1a 229static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 230{
d68e2d1a 231 struct sr_dev_inst *sdi;
fefc4b85 232 struct dev_context *devc;
10e5cbed
BV
233 struct sr_probe *probe;
234 uint32_t tmp_int, ui;
4fe9a6da 235 uint8_t key, type, token;
bb7ef793 236 GString *tmp_str, *devname, *version;
10e5cbed 237 guchar tmp_c;
4fe9a6da 238
d3683c42 239 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 240 sdi->driver = odi;
fefc4b85
BV
241 devc = ols_dev_new();
242 sdi->priv = devc;
4fe9a6da 243
bb7ef793 244 devname = g_string_new("");
4fe9a6da
BV
245 version = g_string_new("");
246
247 key = 0xff;
248 while (key) {
249 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
250 break;
251 type = key >> 5;
252 token = key & 0x1f;
253 switch (type) {
254 case 0:
255 /* NULL-terminated string */
256 tmp_str = g_string_new("");
257 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
258 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
259 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
260 key, tmp_str->str);
4fe9a6da
BV
261 switch (token) {
262 case 0x01:
263 /* Device name */
bb7ef793 264 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
265 break;
266 case 0x02:
267 /* FPGA firmware version */
268 if (version->len)
269 g_string_append(version, ", ");
270 g_string_append(version, "FPGA version ");
271 g_string_append(version, tmp_str->str);
272 break;
273 case 0x03:
274 /* Ancillary version */
275 if (version->len)
276 g_string_append(version, ", ");
277 g_string_append(version, "Ancillary version ");
278 g_string_append(version, tmp_str->str);
279 break;
280 default:
b08024a8
UH
281 sr_info("ols: unknown token 0x%.2x: '%s'",
282 token, tmp_str->str);
4fe9a6da
BV
283 break;
284 }
285 g_string_free(tmp_str, TRUE);
286 break;
287 case 1:
288 /* 32-bit unsigned integer */
289 if (serial_read(fd, &tmp_int, 4) != 4)
290 break;
291 tmp_int = reverse32(tmp_int);
b08024a8
UH
292 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
293 key, tmp_int);
4fe9a6da
BV
294 switch (token) {
295 case 0x00:
296 /* Number of usable probes */
10e5cbed
BV
297 for (ui = 0; ui < tmp_int; ui++) {
298 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
299 probe_names[ui])))
300 return 0;
301 sdi->probes = g_slist_append(sdi->probes, probe);
302 }
4fe9a6da
BV
303 break;
304 case 0x01:
305 /* Amount of sample memory available (bytes) */
fefc4b85 306 devc->max_samples = tmp_int;
4fe9a6da
BV
307 break;
308 case 0x02:
309 /* Amount of dynamic memory available (bytes) */
310 /* what is this for? */
311 break;
312 case 0x03:
313 /* Maximum sample rate (hz) */
fefc4b85 314 devc->max_samplerate = tmp_int;
4fe9a6da
BV
315 break;
316 case 0x04:
317 /* protocol version */
fefc4b85 318 devc->protocol_version = tmp_int;
4fe9a6da
BV
319 break;
320 default:
b08024a8
UH
321 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
322 token, tmp_int);
4fe9a6da
BV
323 break;
324 }
325 break;
326 case 2:
327 /* 8-bit unsigned integer */
328 if (serial_read(fd, &tmp_c, 1) != 1)
329 break;
b08024a8
UH
330 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
331 key, tmp_c);
4fe9a6da
BV
332 switch (token) {
333 case 0x00:
334 /* Number of usable probes */
10e5cbed
BV
335 for (ui = 0; ui < tmp_c; ui++) {
336 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
337 probe_names[ui])))
338 return 0;
339 sdi->probes = g_slist_append(sdi->probes, probe);
340 }
4fe9a6da
BV
341 break;
342 case 0x01:
343 /* protocol version */
fefc4b85 344 devc->protocol_version = tmp_c;
4fe9a6da
BV
345 break;
346 default:
b08024a8
UH
347 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
348 token, tmp_c);
4fe9a6da
BV
349 break;
350 }
351 break;
352 default:
353 /* unknown type */
354 break;
355 }
356 }
357
bb7ef793 358 sdi->model = devname->str;
4fe9a6da 359 sdi->version = version->str;
bb7ef793 360 g_string_free(devname, FALSE);
4fe9a6da
BV
361 g_string_free(version, FALSE);
362
363 return sdi;
364}
365
40dda2c3 366static int hw_init(void)
61136ea6 367{
fefc4b85 368 struct drv_context *drvc;
61136ea6 369
fefc4b85
BV
370 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
371 sr_err("ols: driver context malloc failed.");
372 return SR_ERR;
373 }
374 odi->priv = drvc;
61136ea6
BV
375
376 return SR_OK;
377}
378
10e5cbed 379static GSList *hw_scan(GSList *options)
a1bb33af 380{
d68e2d1a 381 struct sr_dev_inst *sdi;
fefc4b85
BV
382 struct drv_context *drvc;
383 struct dev_context *devc;
10e5cbed
BV
384 struct sr_probe *probe;
385 GSList *devices, *ports, *l;
4fe9a6da 386 GPollFD *fds, probefd;
10e5cbed 387 int devcnt, final_devcnt, num_ports, fd, ret, i, j;
bb7ef793 388 char buf[8], **dev_names, **serial_params;
a1bb33af 389
10e5cbed 390 (void)options;
fefc4b85 391 drvc = odi->priv;
c0a4b971 392 final_devcnt = 0;
10e5cbed 393 devices = NULL;
c0a4b971 394
40dda2c3
BV
395 /* Scan all serial ports. */
396 ports = list_serial_ports();
a1bb33af 397 num_ports = g_slist_length(ports);
c0a4b971
UH
398
399 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
400 sr_err("ols: %s: fds malloc failed", __func__);
401 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
402 }
403
bb7ef793
UH
404 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
405 sr_err("ols: %s: dev_names malloc failed", __func__);
c0a4b971
UH
406 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
407 }
408
409 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
410 sr_err("ols: %s: serial_params malloc failed", __func__);
bb7ef793 411 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
c0a4b971
UH
412 }
413
a1bb33af 414 devcnt = 0;
43fc7885
UH
415 for (l = ports; l; l = l->next) {
416 /* The discovery procedure is like this: first send the Reset
417 * command (0x00) 5 times, since the device could be anywhere
418 * in a 5-byte command. Then send the ID command (0x02).
419 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
420 * have a match.
421 *
422 * Since it may take the device a while to respond at 115Kb/s,
423 * we do all the sending first, then wait for all of them to
424 * respond with g_poll().
a1bb33af 425 */
b08024a8 426 sr_info("ols: probing %s...", (char *)l->data);
d02a535e 427 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
43fc7885 428 if (fd != -1) {
d02a535e 429 serial_params[devcnt] = serial_backup_params(fd);
f8c1fcda 430 serial_set_params(fd, 115200, 8, SERIAL_PARITY_NONE, 1, 2);
e46b8fb1 431 ret = SR_OK;
43fc7885
UH
432 for (i = 0; i < 5; i++) {
433 if ((ret = send_shortcommand(fd,
e46b8fb1 434 CMD_RESET)) != SR_OK) {
43fc7885 435 /* Serial port is not writable. */
6937bb75
BV
436 break;
437 }
a1bb33af 438 }
e46b8fb1 439 if (ret != SR_OK) {
43fc7885
UH
440 serial_restore_params(fd,
441 serial_params[devcnt]);
d02a535e 442 serial_close(fd);
6937bb75 443 continue;
d02a535e 444 }
6937bb75
BV
445 send_shortcommand(fd, CMD_ID);
446 fds[devcnt].fd = fd;
447 fds[devcnt].events = G_IO_IN;
bb7ef793 448 dev_names[devcnt] = g_strdup(l->data);
6937bb75 449 devcnt++;
a1bb33af 450 }
133a37bf 451 g_free(l->data);
a1bb33af
UH
452 }
453
5b15b41e
PS
454 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
455 usleep(10000);
a1bb33af 456
a1bb33af 457 g_poll(fds, devcnt, 1);
4fe9a6da 458
43fc7885 459 for (i = 0; i < devcnt; i++) {
4fe9a6da
BV
460 if (fds[i].revents != G_IO_IN)
461 continue;
462 if (serial_read(fds[i].fd, buf, 4) != 4)
463 continue;
464 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
465 continue;
466
467 /* definitely using the OLS protocol, check if it supports
468 * the metadata command
469 */
470 send_shortcommand(fds[i].fd, CMD_METADATA);
471 probefd.fd = fds[i].fd;
472 probefd.events = G_IO_IN;
473 if (g_poll(&probefd, 1, 10) > 0) {
474 /* got metadata */
475 sdi = get_metadata(fds[i].fd);
476 sdi->index = final_devcnt;
fefc4b85 477 devc = sdi->priv;
4fe9a6da
BV
478 } else {
479 /* not an OLS -- some other board that uses the sump protocol */
d3683c42 480 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
4fe9a6da 481 "Sump", "Logic Analyzer", "v1.0");
2efc5948 482 sdi->driver = odi;
fefc4b85 483 devc = ols_dev_new();
10e5cbed
BV
484 for (j = 0; j < 32; j++) {
485 if (!(probe = sr_probe_new(j, SR_PROBE_LOGIC, TRUE,
486 probe_names[j])))
487 return 0;
488 sdi->probes = g_slist_append(sdi->probes, probe);
489 }
fefc4b85 490 sdi->priv = devc;
a1bb33af 491 }
fefc4b85
BV
492 devc->serial = sr_serial_dev_inst_new(dev_names[i], -1);
493 drvc->instances = g_slist_append(drvc->instances, sdi);
e5e81856
BV
494 devices = g_slist_append(devices, sdi);
495
4fe9a6da
BV
496 final_devcnt++;
497 serial_close(fds[i].fd);
498 fds[i].fd = 0;
4fe9a6da
BV
499 }
500
501 /* clean up after all the probing */
502 for (i = 0; i < devcnt; i++) {
43fc7885 503 if (fds[i].fd != 0) {
d02a535e
BV
504 serial_restore_params(fds[i].fd, serial_params[i]);
505 serial_close(fds[i].fd);
6937bb75 506 }
133a37bf 507 g_free(serial_params[i]);
bb7ef793 508 g_free(dev_names[i]);
a1bb33af
UH
509 }
510
c0a4b971 511 g_free(serial_params);
bb7ef793
UH
512hw_init_free_dev_names:
513 g_free(dev_names);
c0a4b971
UH
514hw_init_free_fds:
515 g_free(fds);
516hw_init_free_ports:
a1bb33af
UH
517 g_slist_free(ports);
518
10e5cbed 519 return devices;
a1bb33af
UH
520}
521
25a0f108 522static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 523{
fefc4b85 524 struct dev_context *devc;
a1bb33af 525
fefc4b85 526 devc = sdi->priv;
69890f73 527
fefc4b85
BV
528 devc->serial->fd = serial_open(devc->serial->port, O_RDWR);
529 if (devc->serial->fd == -1)
e46b8fb1 530 return SR_ERR;
a1bb33af 531
5a2326a7 532 sdi->status = SR_ST_ACTIVE;
a1bb33af 533
e46b8fb1 534 return SR_OK;
a1bb33af
UH
535}
536
25a0f108 537static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 538{
fefc4b85 539 struct dev_context *devc;
a1bb33af 540
fefc4b85 541 devc = sdi->priv;
69890f73 542
fefc4b85
BV
543 if (devc->serial->fd != -1) {
544 serial_close(devc->serial->fd);
545 devc->serial->fd = -1;
5a2326a7 546 sdi->status = SR_ST_INACTIVE;
a1bb33af 547 }
697785d1
UH
548
549 return SR_OK;
a1bb33af
UH
550}
551
57ab7d9f 552static int hw_cleanup(void)
a1bb33af
UH
553{
554 GSList *l;
d68e2d1a 555 struct sr_dev_inst *sdi;
fefc4b85
BV
556 struct drv_context *drvc;
557 struct dev_context *devc;
57ab7d9f 558 int ret = SR_OK;
a1bb33af 559
fefc4b85
BV
560 if (!(drvc = odi->priv))
561 return SR_OK;
562
8722c31e 563 /* Properly close and free all devices. */
fefc4b85 564 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
565 if (!(sdi = l->data)) {
566 /* Log error, but continue cleaning up the rest. */
567 sr_err("ols: %s: sdi was NULL, continuing", __func__);
568 ret = SR_ERR_BUG;
569 continue;
570 }
fefc4b85 571 if (!(devc = sdi->priv)) {
57ab7d9f
UH
572 /* Log error, but continue cleaning up the rest. */
573 sr_err("ols: %s: sdi->priv was NULL, continuing",
574 __func__);
575 ret = SR_ERR_BUG;
576 continue;
577 }
578 /* TODO: Check for serial != NULL. */
fefc4b85
BV
579 if (devc->serial->fd != -1)
580 serial_close(devc->serial->fd);
581 sr_serial_dev_inst_free(devc->serial);
d3683c42 582 sr_dev_inst_free(sdi);
a1bb33af 583 }
fefc4b85
BV
584 g_slist_free(drvc->instances);
585 drvc->instances = NULL;
57ab7d9f
UH
586
587 return ret;
a1bb33af
UH
588}
589
dddfb3db
BV
590static int hw_info_get(int info_id, const void **data,
591 const struct sr_dev_inst *sdi)
a1bb33af 592{
fefc4b85 593 struct dev_context *devc;
a1bb33af 594
dddfb3db 595 switch (info_id) {
2ca4465b
BV
596 case SR_DI_HWCAPS:
597 *data = hwcaps;
598 break;
5a2326a7 599 case SR_DI_NUM_PROBES:
dddfb3db 600 *data = GINT_TO_POINTER(1);
a1bb33af 601 break;
464d12c7 602 case SR_DI_PROBE_NAMES:
dddfb3db 603 *data = probe_names;
464d12c7 604 break;
5a2326a7 605 case SR_DI_SAMPLERATES:
dddfb3db 606 *data = &samplerates;
a1bb33af 607 break;
5a2326a7 608 case SR_DI_TRIGGER_TYPES:
dddfb3db 609 *data = (char *)TRIGGER_TYPES;
a1bb33af 610 break;
5a2326a7 611 case SR_DI_CUR_SAMPLERATE:
dddfb3db 612 if (sdi) {
fefc4b85
BV
613 devc = sdi->priv;
614 *data = &devc->cur_samplerate;
dddfb3db
BV
615 } else
616 return SR_ERR;
a1bb33af 617 break;
dddfb3db
BV
618 default:
619 return SR_ERR_ARG;
a1bb33af
UH
620 }
621
dddfb3db 622 return SR_OK;
a1bb33af
UH
623}
624
6f4b1868 625static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 626{
fefc4b85 627 struct dev_context *devc;
a1bb33af 628
fefc4b85
BV
629 devc = sdi->priv;
630 if (devc->max_samplerate) {
631 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
632 return SR_ERR_SAMPLERATE;
633 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 634 return SR_ERR_SAMPLERATE;
a1bb33af 635
43fc7885 636 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
637 devc->flag_reg |= FLAG_DEMUX;
638 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 639 } else {
fefc4b85
BV
640 devc->flag_reg &= ~FLAG_DEMUX;
641 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 642 }
a1bb33af 643
7583b99d
GM
644 /* Calculate actual samplerate used and complain if it is different
645 * from the requested.
646 */
fefc4b85
BV
647 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
648 if (devc->flag_reg & FLAG_DEMUX)
649 devc->cur_samplerate *= 2;
650 if (devc->cur_samplerate != samplerate)
133a37bf 651 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 652 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 653
e46b8fb1 654 return SR_OK;
a1bb33af
UH
655}
656
6f4b1868
BV
657static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
658 const void *value)
a1bb33af 659{
fefc4b85 660 struct dev_context *devc;
a1bb33af 661 int ret;
1b79df2f 662 const uint64_t *tmp_u64;
a1bb33af 663
fefc4b85 664 devc = sdi->priv;
a1bb33af 665
5a2326a7 666 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 667 return SR_ERR;
a1bb33af 668
ffedd0bf 669 switch (hwcap) {
5a2326a7 670 case SR_HWCAP_SAMPLERATE:
1b79df2f 671 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 672 break;
5a2326a7 673 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 674 tmp_u64 = value;
574ce498 675 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 676 return SR_ERR;
fefc4b85 677 if (*tmp_u64 > devc->max_samples)
133a37bf 678 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
679 devc->limit_samples = *tmp_u64;
680 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 681 ret = SR_OK;
a803c0db 682 break;
5a2326a7 683 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
684 devc->capture_ratio = *(const uint64_t *)value;
685 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
686 devc->capture_ratio = 0;
e46b8fb1 687 ret = SR_ERR;
43fc7885 688 } else
e46b8fb1 689 ret = SR_OK;
a803c0db 690 break;
3a4d09c0 691 case SR_HWCAP_RLE:
4d436e71 692 if (GPOINTER_TO_INT(value)) {
3a4d09c0 693 sr_info("ols: enabling RLE");
fefc4b85 694 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
695 }
696 ret = SR_OK;
697 break;
a803c0db 698 default:
e46b8fb1 699 ret = SR_ERR;
43fc7885 700 }
a1bb33af
UH
701
702 return ret;
703}
704
26bf9d56
BV
705static void abort_acquisition(const struct sr_dev_inst *sdi)
706{
707 struct sr_datafeed_packet packet;
708 struct dev_context *devc;
709
710 devc = sdi->priv;
711 sr_source_remove(devc->serial->fd);
712
713 /* Terminate session */
714 packet.type = SR_DF_END;
715 sr_session_send(sdi, &packet);
716
717}
718
719
720
1f9813eb 721static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 722{
b9c735a2 723 struct sr_datafeed_packet packet;
9c939c51 724 struct sr_datafeed_logic logic;
d68e2d1a 725 struct sr_dev_inst *sdi;
fefc4b85
BV
726 struct drv_context *drvc;
727 struct dev_context *devc;
4fe9a6da 728 GSList *l;
3a4d09c0
GM
729 int num_channels, offset, i, j;
730 unsigned char byte;
a1bb33af 731
fefc4b85
BV
732 drvc = odi->priv;
733
734 /* Find this device's devc struct by its fd. */
735 devc = NULL;
736 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 737 sdi = l->data;
fefc4b85
BV
738 devc = sdi->priv;
739 if (devc->serial->fd == fd) {
4fe9a6da
BV
740 break;
741 }
fefc4b85 742 devc = NULL;
4fe9a6da 743 }
fefc4b85 744 if (!devc)
ea9cfed7 745 /* Shouldn't happen. */
4fe9a6da
BV
746 return TRUE;
747
fefc4b85 748 if (devc->num_transfers++ == 0) {
43fc7885
UH
749 /*
750 * First time round, means the device started sending data,
751 * and will not stop until done. If it stops sending for
752 * longer than it takes to send a byte, that means it's
753 * finished. We'll double that to 30ms to be sure...
a1bb33af 754 */
6f1be0a2 755 sr_source_remove(fd);
1f9813eb 756 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
fefc4b85
BV
757 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
758 if (!devc->raw_sample_buf) {
759 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
760 __func__);
761 return FALSE;
762 }
a803c0db 763 /* fill with 1010... for debugging */
fefc4b85 764 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
765 }
766
6937bb75 767 num_channels = 0;
43fc7885 768 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 769 if ((devc->flag_reg & i) == 0)
6937bb75 770 num_channels++;
43fc7885 771 }
6937bb75 772
3a4d09c0 773 if (revents == G_IO_IN) {
2119ab03 774 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
775 return FALSE;
776
baf1d714 777 /* Ignore it if we've read enough. */
fefc4b85 778 if (devc->num_samples >= devc->limit_samples)
baf1d714 779 return TRUE;
3a4d09c0 780
fefc4b85 781 devc->sample[devc->num_bytes++] = byte;
b08024a8 782 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 783 if (devc->num_bytes == num_channels) {
43fc7885 784 /* Got a full sample. */
b08024a8 785 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
786 devc->num_bytes * 2, *(int *)devc->sample);
787 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
788 /*
789 * In RLE mode -1 should never come in as a
790 * sample, because bit 31 is the "count" flag.
43fc7885 791 */
fefc4b85
BV
792 if (devc->sample[devc->num_bytes - 1] & 0x80) {
793 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
794 /*
795 * FIXME: This will only work on
796 * little-endian systems.
a1bb33af 797 */
fefc4b85
BV
798 devc->rle_count = *(int *)(devc->sample);
799 sr_dbg("ols: RLE count = %d", devc->rle_count);
800 devc->num_bytes = 0;
3a4d09c0 801 return TRUE;
baf1d714 802 }
3a4d09c0 803 }
fefc4b85
BV
804 devc->num_samples += devc->rle_count + 1;
805 if (devc->num_samples > devc->limit_samples) {
baf1d714 806 /* Save us from overrunning the buffer. */
fefc4b85
BV
807 devc->rle_count -= devc->num_samples - devc->limit_samples;
808 devc->num_samples = devc->limit_samples;
a1bb33af
UH
809 }
810
43fc7885
UH
811 if (num_channels < 4) {
812 /*
813 * Some channel groups may have been turned
814 * off, to speed up transfer between the
815 * hardware and the PC. Expand that here before
816 * submitting it over the session bus --
817 * whatever is listening on the bus will be
818 * expecting a full 32-bit sample, based on
819 * the number of probes.
6937bb75
BV
820 */
821 j = 0;
fefc4b85 822 memset(devc->tmp_sample, 0, 4);
43fc7885 823 for (i = 0; i < 4; i++) {
fefc4b85 824 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
825 /*
826 * This channel group was
827 * enabled, copy from received
828 * sample.
829 */
fefc4b85 830 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
831 }
832 }
fefc4b85
BV
833 memcpy(devc->sample, devc->tmp_sample, 4);
834 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
835 }
836
a803c0db
BV
837 /* the OLS sends its sample buffer backwards.
838 * store it in reverse order here, so we can dump
839 * this on the session bus later.
840 */
fefc4b85
BV
841 offset = (devc->limit_samples - devc->num_samples) * 4;
842 for (i = 0; i <= devc->rle_count; i++) {
843 memcpy(devc->raw_sample_buf + offset + (i * 4),
844 devc->sample, 4);
baf1d714 845 }
fefc4b85
BV
846 memset(devc->sample, 0, 4);
847 devc->num_bytes = 0;
848 devc->rle_count = 0;
a1bb33af 849 }
43fc7885
UH
850 } else {
851 /*
852 * This is the main loop telling us a timeout was reached, or
853 * we've acquired all the samples we asked for -- we're done.
a803c0db 854 * Send the (properly-ordered) buffer to the frontend.
43fc7885 855 */
fefc4b85 856 if (devc->trigger_at != -1) {
a803c0db
BV
857 /* a trigger was set up, so we need to tell the frontend
858 * about it.
859 */
fefc4b85 860 if (devc->trigger_at > 0) {
a803c0db 861 /* there are pre-trigger samples, send those first */
5a2326a7 862 packet.type = SR_DF_LOGIC;
9c939c51 863 packet.payload = &logic;
fefc4b85 864 logic.length = devc->trigger_at * 4;
9c939c51 865 logic.unitsize = 4;
fefc4b85
BV
866 logic.data = devc->raw_sample_buf +
867 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 868 sr_session_send(cb_data, &packet);
a803c0db
BV
869 }
870
9c939c51 871 /* send the trigger */
5a2326a7 872 packet.type = SR_DF_TRIGGER;
1f9813eb 873 sr_session_send(cb_data, &packet);
a803c0db 874
9c939c51 875 /* send post-trigger samples */
5a2326a7 876 packet.type = SR_DF_LOGIC;
9c939c51 877 packet.payload = &logic;
fefc4b85 878 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 879 logic.unitsize = 4;
fefc4b85
BV
880 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
881 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 882 sr_session_send(cb_data, &packet);
a803c0db 883 } else {
9c939c51 884 /* no trigger was used */
5a2326a7 885 packet.type = SR_DF_LOGIC;
9c939c51 886 packet.payload = &logic;
fefc4b85 887 logic.length = devc->num_samples * 4;
9c939c51 888 logic.unitsize = 4;
fefc4b85
BV
889 logic.data = devc->raw_sample_buf +
890 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 891 sr_session_send(cb_data, &packet);
a803c0db 892 }
fefc4b85 893 g_free(devc->raw_sample_buf);
a803c0db 894
06d64eb8 895 serial_flush(fd);
d02a535e 896 serial_close(fd);
26bf9d56
BV
897
898 abort_acquisition(sdi);
a1bb33af
UH
899 }
900
901 return TRUE;
902}
903
5d9ed643
BV
904static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
905 void *cb_data)
a1bb33af 906{
b9c735a2
UH
907 struct sr_datafeed_packet *packet;
908 struct sr_datafeed_header *header;
f366e86c 909 struct sr_datafeed_meta_logic meta;
fefc4b85 910 struct dev_context *devc;
a803c0db 911 uint32_t trigger_config[4];
a1bb33af 912 uint32_t data;
6937bb75
BV
913 uint16_t readcount, delaycount;
914 uint8_t changrp_mask;
22130421 915 int num_channels;
4fe9a6da 916 int i;
a1bb33af 917
fefc4b85 918 devc = sdi->priv;
a1bb33af 919
5a2326a7 920 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 921 return SR_ERR;
a1bb33af 922
014359e3
BV
923 if (configure_probes(sdi) != SR_OK) {
924 sr_err("ols: failed to configured probes");
925 return SR_ERR;
926 }
927
22130421
GM
928 /*
929 * Enable/disable channel groups in the flag register according to the
baf1d714 930 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
931 * to limit readcount.
932 */
933 changrp_mask = 0;
934 num_channels = 0;
935 for (i = 0; i < 4; i++) {
fefc4b85 936 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
937 changrp_mask |= (1 << i);
938 num_channels++;
939 }
940 }
941
baf1d714
UH
942 /*
943 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
944 * buffer.
945 */
fefc4b85 946 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
947
948 memset(trigger_config, 0, 16);
fefc4b85
BV
949 trigger_config[devc->num_stages - 1] |= 0x08;
950 if (devc->trigger_mask[0]) {
951 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
952 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 953
fefc4b85
BV
954 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
955 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 956 return SR_ERR;
fefc4b85
BV
957 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
958 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 959 return SR_ERR;
fefc4b85 960 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
961 trigger_config[0]) != SR_OK)
962 return SR_ERR;
6937bb75 963
fefc4b85
BV
964 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_1,
965 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 966 return SR_ERR;
fefc4b85
BV
967 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_1,
968 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 969 return SR_ERR;
fefc4b85 970 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
971 trigger_config[1]) != SR_OK)
972 return SR_ERR;
6937bb75 973
fefc4b85
BV
974 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_2,
975 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 976 return SR_ERR;
fefc4b85
BV
977 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_2,
978 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 979 return SR_ERR;
fefc4b85 980 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
981 trigger_config[2]) != SR_OK)
982 return SR_ERR;
a803c0db 983
fefc4b85
BV
984 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_3,
985 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 986 return SR_ERR;
fefc4b85
BV
987 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_3,
988 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 989 return SR_ERR;
fefc4b85 990 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
991 trigger_config[3]) != SR_OK)
992 return SR_ERR;
6937bb75 993 } else {
fefc4b85
BV
994 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
995 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 996 return SR_ERR;
fefc4b85
BV
997 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
998 devc->trigger_value[0]) != SR_OK)
e46b8fb1 999 return SR_ERR;
fefc4b85 1000 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
1001 0x00000008) != SR_OK)
1002 return SR_ERR;
a803c0db 1003 delaycount = readcount;
6937bb75 1004 }
a1bb33af 1005
b08024a8 1006 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
1007 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
1008 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
1009 if (send_longcommand(devc->serial->fd, CMD_SET_DIVIDER,
1010 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 1011 return SR_ERR;
a1bb33af 1012
43fc7885 1013 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
1014 data = ((readcount - 1) & 0xffff) << 16;
1015 data |= (delaycount - 1) & 0xffff;
fefc4b85 1016 if (send_longcommand(devc->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 1017 return SR_ERR;
a1bb33af 1018
43fc7885 1019 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
1020 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1021 devc->flag_reg |= FLAG_FILTER;
1022 devc->rle_count = 0;
1023 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
1024 if (send_longcommand(devc->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 1025 return SR_ERR;
a1bb33af 1026
43fc7885 1027 /* Start acquisition on the device. */
fefc4b85 1028 if (send_shortcommand(devc->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 1029 return SR_ERR;
a1bb33af 1030
fefc4b85 1031 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1032 cb_data);
a1bb33af 1033
b53738ba
UH
1034 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1035 sr_err("ols: %s: packet malloc failed", __func__);
1036 return SR_ERR_MALLOC;
1037 }
1038
1039 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1040 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1041 g_free(packet);
b53738ba
UH
1042 return SR_ERR_MALLOC;
1043 }
1044
43fc7885 1045 /* Send header packet to the session bus. */
5a2326a7 1046 packet->type = SR_DF_HEADER;
43fc7885 1047 packet->payload = (unsigned char *)header;
a1bb33af
UH
1048 header->feed_version = 1;
1049 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1050 sr_session_send(cb_data, packet);
1051
1052 /* Send metadata about the SR_DF_LOGIC packets to come. */
1053 packet->type = SR_DF_META_LOGIC;
1054 packet->payload = &meta;
fefc4b85 1055 meta.samplerate = devc->cur_samplerate;
f366e86c 1056 meta.num_probes = NUM_PROBES;
3cd3a20b 1057 sr_session_send(cb_data, packet);
c0a4b971 1058
a1bb33af
UH
1059 g_free(header);
1060 g_free(packet);
1061
e46b8fb1 1062 return SR_OK;
a1bb33af
UH
1063}
1064
3cd3a20b 1065/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
5d9ed643
BV
1066static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1067 void *cb_data)
a1bb33af 1068{
a1bb33af 1069
17e1afcb 1070 /* Avoid compiler warnings. */
26bf9d56 1071 (void)cb_data;
afc8e4de 1072
26bf9d56 1073 abort_acquisition(sdi);
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1074
1075 return SR_OK;
a1bb33af
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1076}
1077
c09f0b57 1078SR_PRIV struct sr_dev_driver ols_driver_info = {
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1079 .name = "ols",
1080 .longname = "Openbench Logic Sniffer",
1081 .api_version = 1,
1082 .init = hw_init,
1083 .cleanup = hw_cleanup,
61136ea6 1084 .scan = hw_scan,
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1085 .dev_open = hw_dev_open,
1086 .dev_close = hw_dev_close,
dddfb3db 1087 .info_get = hw_info_get,
a9a245b4 1088 .dev_config_set = hw_dev_config_set,
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1089 .dev_acquisition_start = hw_dev_acquisition_start,
1090 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1091 .priv = NULL,
a1bb33af 1092};