]> sigrok.org Git - libsigrok.git/blame - hardware/openbench-logic-sniffer/ols.c
Add a struct sr_context * parameter to hw_init()
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
fe1c50fb
BV
45#define SERIALCOMM "115200/8n1"
46
915f7cc8 47static const int hwcaps[] = {
5a2326a7
UH
48 SR_HWCAP_LOGIC_ANALYZER,
49 SR_HWCAP_SAMPLERATE,
50 SR_HWCAP_CAPTURE_RATIO,
51 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 52 SR_HWCAP_RLE,
43fc7885 53 0,
a1bb33af
UH
54};
55
d261dbbf 56/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 57static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
58 "0",
59 "1",
60 "2",
61 "3",
62 "4",
63 "5",
64 "6",
65 "7",
66 "8",
67 "9",
68 "10",
69 "11",
70 "12",
71 "13",
72 "14",
73 "15",
74 "16",
75 "17",
76 "18",
77 "19",
78 "20",
79 "21",
80 "22",
81 "23",
82 "24",
83 "25",
84 "26",
85 "27",
86 "28",
87 "29",
88 "30",
89 "31",
90 NULL,
91};
92
4fe9a6da 93/* default supported samplerates, can be overridden by device metadata */
a533743d 94static const struct sr_samplerates samplerates = {
c9140419 95 SR_HZ(10),
59df0c77 96 SR_MHZ(200),
c9140419
UH
97 SR_HZ(1),
98 NULL,
a1bb33af
UH
99};
100
e5e81856
BV
101SR_PRIV struct sr_dev_driver ols_driver_info;
102static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 103
530f201e
BV
104static int send_shortcommand(struct sr_serial_dev_inst *serial,
105 uint8_t command)
a1bb33af
UH
106{
107 char buf[1];
108
b08024a8 109 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 110 buf[0] = command;
530f201e 111 if (serial_write(serial, buf, 1) != 1)
e46b8fb1 112 return SR_ERR;
a1bb33af 113
e46b8fb1 114 return SR_OK;
a1bb33af
UH
115}
116
530f201e
BV
117static int send_longcommand(struct sr_serial_dev_inst *serial,
118 uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
530f201e 128 if (serial_write(serial, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
014359e3 134static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 135{
014359e3 136 struct dev_context *devc;
1b79df2f
JH
137 const struct sr_probe *probe;
138 const GSList *l;
6937bb75 139 int probe_bit, stage, i;
a1bb33af
UH
140 char *tc;
141
014359e3
BV
142 devc = sdi->priv;
143
fefc4b85 144 devc->probe_mask = 0;
43fc7885 145 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
146 devc->trigger_mask[i] = 0;
147 devc->trigger_value[i] = 0;
a1bb33af
UH
148 }
149
fefc4b85 150 devc->num_stages = 0;
014359e3 151 for (l = sdi->probes; l; l = l->next) {
1b79df2f 152 probe = (const struct sr_probe *)l->data;
43fc7885 153 if (!probe->enabled)
6937bb75
BV
154 continue;
155
43fc7885
UH
156 /*
157 * Set up the probe mask for later configuration into the
158 * flag register.
159 */
b35c8293 160 probe_bit = 1 << (probe->index);
fefc4b85 161 devc->probe_mask |= probe_bit;
6937bb75 162
a803c0db 163 if (!probe->trigger)
6937bb75
BV
164 continue;
165
43fc7885 166 /* Configure trigger mask and value. */
6937bb75 167 stage = 0;
43fc7885 168 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 169 devc->trigger_mask[stage] |= probe_bit;
43fc7885 170 if (*tc == '1')
fefc4b85 171 devc->trigger_value[stage] |= probe_bit;
6937bb75 172 stage++;
43fc7885
UH
173 if (stage > 3)
174 /*
175 * TODO: Only supporting parallel mode, with
176 * up to 4 stages.
177 */
e46b8fb1 178 return SR_ERR;
a1bb33af 179 }
fefc4b85
BV
180 if (stage > devc->num_stages)
181 devc->num_stages = stage;
a1bb33af
UH
182 }
183
e46b8fb1 184 return SR_OK;
a1bb33af
UH
185}
186
a803c0db 187static uint32_t reverse16(uint32_t in)
6937bb75
BV
188{
189 uint32_t out;
190
a803c0db
BV
191 out = (in & 0xff) << 8;
192 out |= (in & 0xff00) >> 8;
193 out |= (in & 0xff0000) << 8;
194 out |= (in & 0xff000000) >> 8;
195
196 return out;
197}
198
199static uint32_t reverse32(uint32_t in)
200{
201 uint32_t out;
202
203 out = (in & 0xff) << 24;
204 out |= (in & 0xff00) << 8;
205 out |= (in & 0xff0000) >> 8;
206 out |= (in & 0xff000000) >> 24;
207
208 return out;
6937bb75
BV
209}
210
fefc4b85 211static struct dev_context *ols_dev_new(void)
4fe9a6da 212{
fefc4b85 213 struct dev_context *devc;
4fe9a6da 214
fefc4b85
BV
215 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
216 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
217 return NULL;
218 }
219
fefc4b85
BV
220 devc->trigger_at = -1;
221 devc->probe_mask = 0xffffffff;
222 devc->cur_samplerate = SR_KHZ(200);
223 devc->serial = NULL;
4fe9a6da 224
fefc4b85 225 return devc;
4fe9a6da
BV
226}
227
530f201e 228static struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial)
4fe9a6da 229{
d68e2d1a 230 struct sr_dev_inst *sdi;
fefc4b85 231 struct dev_context *devc;
10e5cbed
BV
232 struct sr_probe *probe;
233 uint32_t tmp_int, ui;
4fe9a6da 234 uint8_t key, type, token;
bb7ef793 235 GString *tmp_str, *devname, *version;
10e5cbed 236 guchar tmp_c;
4fe9a6da 237
d3683c42 238 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 239 sdi->driver = odi;
fefc4b85
BV
240 devc = ols_dev_new();
241 sdi->priv = devc;
4fe9a6da 242
bb7ef793 243 devname = g_string_new("");
4fe9a6da
BV
244 version = g_string_new("");
245
246 key = 0xff;
247 while (key) {
530f201e 248 if (serial_read(serial, &key, 1) != 1 || key == 0x00)
4fe9a6da
BV
249 break;
250 type = key >> 5;
251 token = key & 0x1f;
252 switch (type) {
253 case 0:
254 /* NULL-terminated string */
255 tmp_str = g_string_new("");
530f201e 256 while (serial_read(serial, &tmp_c, 1) == 1 && tmp_c != '\0')
4fe9a6da 257 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
258 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
259 key, tmp_str->str);
4fe9a6da
BV
260 switch (token) {
261 case 0x01:
262 /* Device name */
bb7ef793 263 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
264 break;
265 case 0x02:
266 /* FPGA firmware version */
267 if (version->len)
268 g_string_append(version, ", ");
269 g_string_append(version, "FPGA version ");
270 g_string_append(version, tmp_str->str);
271 break;
272 case 0x03:
273 /* Ancillary version */
274 if (version->len)
275 g_string_append(version, ", ");
276 g_string_append(version, "Ancillary version ");
277 g_string_append(version, tmp_str->str);
278 break;
279 default:
b08024a8
UH
280 sr_info("ols: unknown token 0x%.2x: '%s'",
281 token, tmp_str->str);
4fe9a6da
BV
282 break;
283 }
284 g_string_free(tmp_str, TRUE);
285 break;
286 case 1:
287 /* 32-bit unsigned integer */
530f201e 288 if (serial_read(serial, &tmp_int, 4) != 4)
4fe9a6da
BV
289 break;
290 tmp_int = reverse32(tmp_int);
b08024a8
UH
291 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
292 key, tmp_int);
4fe9a6da
BV
293 switch (token) {
294 case 0x00:
295 /* Number of usable probes */
10e5cbed
BV
296 for (ui = 0; ui < tmp_int; ui++) {
297 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
298 probe_names[ui])))
299 return 0;
300 sdi->probes = g_slist_append(sdi->probes, probe);
301 }
4fe9a6da
BV
302 break;
303 case 0x01:
304 /* Amount of sample memory available (bytes) */
fefc4b85 305 devc->max_samples = tmp_int;
4fe9a6da
BV
306 break;
307 case 0x02:
308 /* Amount of dynamic memory available (bytes) */
309 /* what is this for? */
310 break;
311 case 0x03:
312 /* Maximum sample rate (hz) */
fefc4b85 313 devc->max_samplerate = tmp_int;
4fe9a6da
BV
314 break;
315 case 0x04:
316 /* protocol version */
fefc4b85 317 devc->protocol_version = tmp_int;
4fe9a6da
BV
318 break;
319 default:
b08024a8
UH
320 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
321 token, tmp_int);
4fe9a6da
BV
322 break;
323 }
324 break;
325 case 2:
326 /* 8-bit unsigned integer */
530f201e 327 if (serial_read(serial, &tmp_c, 1) != 1)
4fe9a6da 328 break;
b08024a8
UH
329 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
330 key, tmp_c);
4fe9a6da
BV
331 switch (token) {
332 case 0x00:
333 /* Number of usable probes */
10e5cbed
BV
334 for (ui = 0; ui < tmp_c; ui++) {
335 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
336 probe_names[ui])))
337 return 0;
338 sdi->probes = g_slist_append(sdi->probes, probe);
339 }
4fe9a6da
BV
340 break;
341 case 0x01:
342 /* protocol version */
fefc4b85 343 devc->protocol_version = tmp_c;
4fe9a6da
BV
344 break;
345 default:
b08024a8
UH
346 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
347 token, tmp_c);
4fe9a6da
BV
348 break;
349 }
350 break;
351 default:
352 /* unknown type */
353 break;
354 }
355 }
356
bb7ef793 357 sdi->model = devname->str;
4fe9a6da 358 sdi->version = version->str;
bb7ef793 359 g_string_free(devname, FALSE);
4fe9a6da
BV
360 g_string_free(version, FALSE);
361
362 return sdi;
363}
364
34f06b90 365static int hw_init(struct sr_context *sr_ctx)
61136ea6 366{
fefc4b85 367 struct drv_context *drvc;
61136ea6 368
fefc4b85
BV
369 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
370 sr_err("ols: driver context malloc failed.");
886a52b6 371 return SR_ERR_MALLOC;
fefc4b85
BV
372 }
373 odi->priv = drvc;
61136ea6
BV
374
375 return SR_OK;
376}
377
10e5cbed 378static GSList *hw_scan(GSList *options)
a1bb33af 379{
a99e0d2a 380 struct sr_hwopt *opt;
d68e2d1a 381 struct sr_dev_inst *sdi;
fefc4b85
BV
382 struct drv_context *drvc;
383 struct dev_context *devc;
10e5cbed 384 struct sr_probe *probe;
530f201e 385 struct sr_serial_dev_inst *serial;
a99e0d2a 386 GPollFD probefd;
fe1c50fb 387 GSList *l, *devices;
530f201e 388 int ret, i;
fe1c50fb 389 const char *conn, *serialcomm;
a99e0d2a 390 char buf[8];
a1bb33af 391
10e5cbed 392 (void)options;
fefc4b85 393 drvc = odi->priv;
10e5cbed 394 devices = NULL;
c0a4b971 395
a99e0d2a
AG
396 conn = serialcomm = NULL;
397 for (l = options; l; l = l->next) {
398 opt = l->data;
399 switch (opt->hwopt) {
400 case SR_HWOPT_CONN:
401 conn = opt->value;
402 break;
403 case SR_HWOPT_SERIALCOMM:
404 serialcomm = opt->value;
405 break;
406 }
407 }
90165efe 408 if (!conn)
a99e0d2a 409 return NULL;
c0a4b971 410
fe1c50fb 411 if (serialcomm == NULL)
530f201e
BV
412 serialcomm = SERIALCOMM;
413
414 if (!(serial = sr_serial_dev_inst_new(conn, serialcomm)))
415 return NULL;
c0a4b971 416
a99e0d2a
AG
417 /* The discovery procedure is like this: first send the Reset
418 * command (0x00) 5 times, since the device could be anywhere
419 * in a 5-byte command. Then send the ID command (0x02).
420 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
421 * have a match.
a99e0d2a
AG
422 */
423 sr_info("ols: probing %s .", conn);
a54dd31e 424 if (serial_open(serial, SERIAL_RDWR | SERIAL_NONBLOCK) != SR_OK)
a99e0d2a 425 return NULL;
c0a4b971 426
a99e0d2a
AG
427 ret = SR_OK;
428 for (i = 0; i < 5; i++) {
530f201e 429 if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
a99e0d2a 430 sr_err("ols: port %s is not writable.", conn);
fe1c50fb 431 break;
a1bb33af
UH
432 }
433 }
a99e0d2a 434 if (ret != SR_OK) {
530f201e 435 serial_close(serial);
a99e0d2a
AG
436 sr_err("ols: Could not use port %s. Quitting.", conn);
437 return NULL;
438 }
530f201e 439 send_shortcommand(serial, CMD_ID);
a1bb33af 440
fe1c50fb 441 /* Wait 10ms for a response. */
5b15b41e 442 usleep(10000);
a1bb33af 443
530f201e 444 probefd.fd = serial->fd;
fe1c50fb
BV
445 probefd.events = G_IO_IN;
446 g_poll(&probefd, 1, 1);
4fe9a6da 447
a99e0d2a
AG
448 if (probefd.revents != G_IO_IN)
449 return NULL;
530f201e 450 if (serial_read(serial, buf, 4) != 4)
a99e0d2a
AG
451 return NULL;
452 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
453 return NULL;
4fe9a6da 454
fe1c50fb
BV
455 /* Definitely using the OLS protocol, check if it supports
456 * the metadata command.
a99e0d2a 457 */
530f201e 458 send_shortcommand(serial, CMD_METADATA);
a99e0d2a 459 if (g_poll(&probefd, 1, 10) > 0) {
fe1c50fb 460 /* Got metadata. */
530f201e 461 sdi = get_metadata(serial);
fe1c50fb 462 sdi->index = 0;
a99e0d2a
AG
463 devc = sdi->priv;
464 } else {
fe1c50fb
BV
465 /* Not an OLS -- some other board that uses the sump protocol. */
466 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE,
a99e0d2a
AG
467 "Sump", "Logic Analyzer", "v1.0");
468 sdi->driver = odi;
469 devc = ols_dev_new();
470 for (i = 0; i < 32; i++) {
471 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
472 probe_names[i])))
473 return 0;
474 sdi->probes = g_slist_append(sdi->probes, probe);
a1bb33af 475 }
a99e0d2a 476 sdi->priv = devc;
4fe9a6da 477 }
530f201e 478 devc->serial = serial;
a99e0d2a
AG
479 drvc->instances = g_slist_append(drvc->instances, sdi);
480 devices = g_slist_append(devices, sdi);
481
530f201e 482 serial_close(serial);
a1bb33af 483
10e5cbed 484 return devices;
a1bb33af
UH
485}
486
811deee4
BV
487static GSList *hw_dev_list(void)
488{
489 struct drv_context *drvc;
490
491 drvc = odi->priv;
492
493 return drvc->instances;
494}
495
25a0f108 496static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 497{
fefc4b85 498 struct dev_context *devc;
a1bb33af 499
fefc4b85 500 devc = sdi->priv;
69890f73 501
a54dd31e 502 if (serial_open(devc->serial, SERIAL_RDWR) != SR_OK)
e46b8fb1 503 return SR_ERR;
a1bb33af 504
5a2326a7 505 sdi->status = SR_ST_ACTIVE;
a1bb33af 506
e46b8fb1 507 return SR_OK;
a1bb33af
UH
508}
509
25a0f108 510static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 511{
fefc4b85 512 struct dev_context *devc;
a1bb33af 513
fefc4b85 514 devc = sdi->priv;
69890f73 515
530f201e
BV
516 if (devc->serial && devc->serial->fd != -1) {
517 serial_close(devc->serial);
5a2326a7 518 sdi->status = SR_ST_INACTIVE;
a1bb33af 519 }
697785d1
UH
520
521 return SR_OK;
a1bb33af
UH
522}
523
57ab7d9f 524static int hw_cleanup(void)
a1bb33af
UH
525{
526 GSList *l;
d68e2d1a 527 struct sr_dev_inst *sdi;
fefc4b85
BV
528 struct drv_context *drvc;
529 struct dev_context *devc;
57ab7d9f 530 int ret = SR_OK;
a1bb33af 531
fefc4b85
BV
532 if (!(drvc = odi->priv))
533 return SR_OK;
534
8722c31e 535 /* Properly close and free all devices. */
fefc4b85 536 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
537 if (!(sdi = l->data)) {
538 /* Log error, but continue cleaning up the rest. */
539 sr_err("ols: %s: sdi was NULL, continuing", __func__);
540 ret = SR_ERR_BUG;
541 continue;
542 }
fefc4b85 543 if (!(devc = sdi->priv)) {
57ab7d9f
UH
544 /* Log error, but continue cleaning up the rest. */
545 sr_err("ols: %s: sdi->priv was NULL, continuing",
546 __func__);
547 ret = SR_ERR_BUG;
548 continue;
549 }
530f201e 550 hw_dev_close(sdi);
fefc4b85 551 sr_serial_dev_inst_free(devc->serial);
d3683c42 552 sr_dev_inst_free(sdi);
a1bb33af 553 }
fefc4b85
BV
554 g_slist_free(drvc->instances);
555 drvc->instances = NULL;
57ab7d9f
UH
556
557 return ret;
a1bb33af
UH
558}
559
dddfb3db
BV
560static int hw_info_get(int info_id, const void **data,
561 const struct sr_dev_inst *sdi)
a1bb33af 562{
fefc4b85 563 struct dev_context *devc;
a1bb33af 564
dddfb3db 565 switch (info_id) {
2ca4465b
BV
566 case SR_DI_HWCAPS:
567 *data = hwcaps;
568 break;
5a2326a7 569 case SR_DI_NUM_PROBES:
dddfb3db 570 *data = GINT_TO_POINTER(1);
a1bb33af 571 break;
464d12c7 572 case SR_DI_PROBE_NAMES:
dddfb3db 573 *data = probe_names;
464d12c7 574 break;
5a2326a7 575 case SR_DI_SAMPLERATES:
dddfb3db 576 *data = &samplerates;
a1bb33af 577 break;
5a2326a7 578 case SR_DI_TRIGGER_TYPES:
dddfb3db 579 *data = (char *)TRIGGER_TYPES;
a1bb33af 580 break;
5a2326a7 581 case SR_DI_CUR_SAMPLERATE:
dddfb3db 582 if (sdi) {
fefc4b85
BV
583 devc = sdi->priv;
584 *data = &devc->cur_samplerate;
dddfb3db
BV
585 } else
586 return SR_ERR;
a1bb33af 587 break;
dddfb3db
BV
588 default:
589 return SR_ERR_ARG;
a1bb33af
UH
590 }
591
dddfb3db 592 return SR_OK;
a1bb33af
UH
593}
594
6f4b1868 595static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 596{
fefc4b85 597 struct dev_context *devc;
a1bb33af 598
fefc4b85
BV
599 devc = sdi->priv;
600 if (devc->max_samplerate) {
601 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
602 return SR_ERR_SAMPLERATE;
603 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 604 return SR_ERR_SAMPLERATE;
a1bb33af 605
43fc7885 606 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
607 devc->flag_reg |= FLAG_DEMUX;
608 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 609 } else {
fefc4b85
BV
610 devc->flag_reg &= ~FLAG_DEMUX;
611 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 612 }
a1bb33af 613
7583b99d
GM
614 /* Calculate actual samplerate used and complain if it is different
615 * from the requested.
616 */
fefc4b85
BV
617 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
618 if (devc->flag_reg & FLAG_DEMUX)
619 devc->cur_samplerate *= 2;
620 if (devc->cur_samplerate != samplerate)
133a37bf 621 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 622 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 623
e46b8fb1 624 return SR_OK;
a1bb33af
UH
625}
626
6f4b1868
BV
627static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
628 const void *value)
a1bb33af 629{
fefc4b85 630 struct dev_context *devc;
a1bb33af 631 int ret;
1b79df2f 632 const uint64_t *tmp_u64;
a1bb33af 633
fefc4b85 634 devc = sdi->priv;
a1bb33af 635
5a2326a7 636 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 637 return SR_ERR;
a1bb33af 638
ffedd0bf 639 switch (hwcap) {
5a2326a7 640 case SR_HWCAP_SAMPLERATE:
1b79df2f 641 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 642 break;
5a2326a7 643 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 644 tmp_u64 = value;
574ce498 645 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 646 return SR_ERR;
fefc4b85 647 if (*tmp_u64 > devc->max_samples)
133a37bf 648 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
649 devc->limit_samples = *tmp_u64;
650 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 651 ret = SR_OK;
a803c0db 652 break;
5a2326a7 653 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
654 devc->capture_ratio = *(const uint64_t *)value;
655 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
656 devc->capture_ratio = 0;
e46b8fb1 657 ret = SR_ERR;
43fc7885 658 } else
e46b8fb1 659 ret = SR_OK;
a803c0db 660 break;
3a4d09c0 661 case SR_HWCAP_RLE:
4d436e71 662 if (GPOINTER_TO_INT(value)) {
3a4d09c0 663 sr_info("ols: enabling RLE");
fefc4b85 664 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
665 }
666 ret = SR_OK;
667 break;
a803c0db 668 default:
e46b8fb1 669 ret = SR_ERR;
43fc7885 670 }
a1bb33af
UH
671
672 return ret;
673}
674
26bf9d56
BV
675static void abort_acquisition(const struct sr_dev_inst *sdi)
676{
677 struct sr_datafeed_packet packet;
678 struct dev_context *devc;
679
680 devc = sdi->priv;
681 sr_source_remove(devc->serial->fd);
682
683 /* Terminate session */
684 packet.type = SR_DF_END;
685 sr_session_send(sdi, &packet);
686
687}
688
689
690
1f9813eb 691static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 692{
b9c735a2 693 struct sr_datafeed_packet packet;
9c939c51 694 struct sr_datafeed_logic logic;
d68e2d1a 695 struct sr_dev_inst *sdi;
fefc4b85
BV
696 struct drv_context *drvc;
697 struct dev_context *devc;
4fe9a6da 698 GSList *l;
3a4d09c0
GM
699 int num_channels, offset, i, j;
700 unsigned char byte;
a1bb33af 701
fefc4b85
BV
702 drvc = odi->priv;
703
704 /* Find this device's devc struct by its fd. */
705 devc = NULL;
706 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 707 sdi = l->data;
fefc4b85 708 devc = sdi->priv;
530f201e 709 if (devc->serial->fd == fd)
4fe9a6da 710 break;
fefc4b85 711 devc = NULL;
4fe9a6da 712 }
fefc4b85 713 if (!devc)
ea9cfed7 714 /* Shouldn't happen. */
4fe9a6da
BV
715 return TRUE;
716
fefc4b85 717 if (devc->num_transfers++ == 0) {
43fc7885
UH
718 /*
719 * First time round, means the device started sending data,
720 * and will not stop until done. If it stops sending for
721 * longer than it takes to send a byte, that means it's
722 * finished. We'll double that to 30ms to be sure...
a1bb33af 723 */
6f1be0a2 724 sr_source_remove(fd);
1f9813eb 725 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
886a52b6 726 /* TODO: Check malloc return code. */
fefc4b85
BV
727 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
728 if (!devc->raw_sample_buf) {
729 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
730 __func__);
731 return FALSE;
732 }
a803c0db 733 /* fill with 1010... for debugging */
fefc4b85 734 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
735 }
736
6937bb75 737 num_channels = 0;
43fc7885 738 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 739 if ((devc->flag_reg & i) == 0)
6937bb75 740 num_channels++;
43fc7885 741 }
6937bb75 742
3a4d09c0 743 if (revents == G_IO_IN) {
530f201e 744 if (serial_read(devc->serial, &byte, 1) != 1)
a1bb33af
UH
745 return FALSE;
746
baf1d714 747 /* Ignore it if we've read enough. */
fefc4b85 748 if (devc->num_samples >= devc->limit_samples)
baf1d714 749 return TRUE;
3a4d09c0 750
fefc4b85 751 devc->sample[devc->num_bytes++] = byte;
b08024a8 752 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 753 if (devc->num_bytes == num_channels) {
43fc7885 754 /* Got a full sample. */
b08024a8 755 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
756 devc->num_bytes * 2, *(int *)devc->sample);
757 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
758 /*
759 * In RLE mode -1 should never come in as a
760 * sample, because bit 31 is the "count" flag.
43fc7885 761 */
fefc4b85
BV
762 if (devc->sample[devc->num_bytes - 1] & 0x80) {
763 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
764 /*
765 * FIXME: This will only work on
766 * little-endian systems.
a1bb33af 767 */
fefc4b85
BV
768 devc->rle_count = *(int *)(devc->sample);
769 sr_dbg("ols: RLE count = %d", devc->rle_count);
770 devc->num_bytes = 0;
3a4d09c0 771 return TRUE;
baf1d714 772 }
3a4d09c0 773 }
fefc4b85
BV
774 devc->num_samples += devc->rle_count + 1;
775 if (devc->num_samples > devc->limit_samples) {
baf1d714 776 /* Save us from overrunning the buffer. */
fefc4b85
BV
777 devc->rle_count -= devc->num_samples - devc->limit_samples;
778 devc->num_samples = devc->limit_samples;
a1bb33af
UH
779 }
780
43fc7885
UH
781 if (num_channels < 4) {
782 /*
783 * Some channel groups may have been turned
784 * off, to speed up transfer between the
785 * hardware and the PC. Expand that here before
786 * submitting it over the session bus --
787 * whatever is listening on the bus will be
788 * expecting a full 32-bit sample, based on
789 * the number of probes.
6937bb75
BV
790 */
791 j = 0;
fefc4b85 792 memset(devc->tmp_sample, 0, 4);
43fc7885 793 for (i = 0; i < 4; i++) {
fefc4b85 794 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
795 /*
796 * This channel group was
797 * enabled, copy from received
798 * sample.
799 */
fefc4b85 800 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
801 }
802 }
fefc4b85
BV
803 memcpy(devc->sample, devc->tmp_sample, 4);
804 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
805 }
806
a803c0db
BV
807 /* the OLS sends its sample buffer backwards.
808 * store it in reverse order here, so we can dump
809 * this on the session bus later.
810 */
fefc4b85
BV
811 offset = (devc->limit_samples - devc->num_samples) * 4;
812 for (i = 0; i <= devc->rle_count; i++) {
813 memcpy(devc->raw_sample_buf + offset + (i * 4),
814 devc->sample, 4);
baf1d714 815 }
fefc4b85
BV
816 memset(devc->sample, 0, 4);
817 devc->num_bytes = 0;
818 devc->rle_count = 0;
a1bb33af 819 }
43fc7885
UH
820 } else {
821 /*
822 * This is the main loop telling us a timeout was reached, or
823 * we've acquired all the samples we asked for -- we're done.
a803c0db 824 * Send the (properly-ordered) buffer to the frontend.
43fc7885 825 */
fefc4b85 826 if (devc->trigger_at != -1) {
a803c0db
BV
827 /* a trigger was set up, so we need to tell the frontend
828 * about it.
829 */
fefc4b85 830 if (devc->trigger_at > 0) {
a803c0db 831 /* there are pre-trigger samples, send those first */
5a2326a7 832 packet.type = SR_DF_LOGIC;
9c939c51 833 packet.payload = &logic;
fefc4b85 834 logic.length = devc->trigger_at * 4;
9c939c51 835 logic.unitsize = 4;
fefc4b85
BV
836 logic.data = devc->raw_sample_buf +
837 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 838 sr_session_send(cb_data, &packet);
a803c0db
BV
839 }
840
9c939c51 841 /* send the trigger */
5a2326a7 842 packet.type = SR_DF_TRIGGER;
1f9813eb 843 sr_session_send(cb_data, &packet);
a803c0db 844
9c939c51 845 /* send post-trigger samples */
5a2326a7 846 packet.type = SR_DF_LOGIC;
9c939c51 847 packet.payload = &logic;
fefc4b85 848 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 849 logic.unitsize = 4;
fefc4b85
BV
850 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
851 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 852 sr_session_send(cb_data, &packet);
a803c0db 853 } else {
9c939c51 854 /* no trigger was used */
5a2326a7 855 packet.type = SR_DF_LOGIC;
9c939c51 856 packet.payload = &logic;
fefc4b85 857 logic.length = devc->num_samples * 4;
9c939c51 858 logic.unitsize = 4;
fefc4b85
BV
859 logic.data = devc->raw_sample_buf +
860 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 861 sr_session_send(cb_data, &packet);
a803c0db 862 }
fefc4b85 863 g_free(devc->raw_sample_buf);
a803c0db 864
530f201e 865 serial_flush(devc->serial);
26bf9d56 866 abort_acquisition(sdi);
530f201e 867 serial_close(devc->serial);
a1bb33af
UH
868 }
869
870 return TRUE;
871}
872
5d9ed643
BV
873static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
874 void *cb_data)
a1bb33af 875{
b9c735a2
UH
876 struct sr_datafeed_packet *packet;
877 struct sr_datafeed_header *header;
f366e86c 878 struct sr_datafeed_meta_logic meta;
fefc4b85 879 struct dev_context *devc;
a803c0db 880 uint32_t trigger_config[4];
a1bb33af 881 uint32_t data;
6937bb75
BV
882 uint16_t readcount, delaycount;
883 uint8_t changrp_mask;
22130421 884 int num_channels;
4fe9a6da 885 int i;
a1bb33af 886
fefc4b85 887 devc = sdi->priv;
a1bb33af 888
5a2326a7 889 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 890 return SR_ERR;
a1bb33af 891
014359e3
BV
892 if (configure_probes(sdi) != SR_OK) {
893 sr_err("ols: failed to configured probes");
894 return SR_ERR;
895 }
896
22130421
GM
897 /*
898 * Enable/disable channel groups in the flag register according to the
baf1d714 899 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
900 * to limit readcount.
901 */
902 changrp_mask = 0;
903 num_channels = 0;
904 for (i = 0; i < 4; i++) {
fefc4b85 905 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
906 changrp_mask |= (1 << i);
907 num_channels++;
908 }
909 }
910
baf1d714
UH
911 /*
912 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
913 * buffer.
914 */
fefc4b85 915 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
916
917 memset(trigger_config, 0, 16);
fefc4b85
BV
918 trigger_config[devc->num_stages - 1] |= 0x08;
919 if (devc->trigger_mask[0]) {
920 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
921 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 922
530f201e 923 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 924 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 925 return SR_ERR;
530f201e 926 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 927 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 928 return SR_ERR;
530f201e 929 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
930 trigger_config[0]) != SR_OK)
931 return SR_ERR;
6937bb75 932
530f201e 933 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_1,
fefc4b85 934 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 935 return SR_ERR;
530f201e 936 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_1,
fefc4b85 937 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 938 return SR_ERR;
530f201e 939 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
940 trigger_config[1]) != SR_OK)
941 return SR_ERR;
6937bb75 942
530f201e 943 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_2,
fefc4b85 944 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 945 return SR_ERR;
530f201e 946 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_2,
fefc4b85 947 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 948 return SR_ERR;
530f201e 949 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
950 trigger_config[2]) != SR_OK)
951 return SR_ERR;
a803c0db 952
530f201e 953 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_3,
fefc4b85 954 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 955 return SR_ERR;
530f201e 956 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_3,
fefc4b85 957 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 958 return SR_ERR;
530f201e 959 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
960 trigger_config[3]) != SR_OK)
961 return SR_ERR;
6937bb75 962 } else {
530f201e 963 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 964 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 965 return SR_ERR;
530f201e 966 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 967 devc->trigger_value[0]) != SR_OK)
e46b8fb1 968 return SR_ERR;
530f201e 969 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
970 0x00000008) != SR_OK)
971 return SR_ERR;
a803c0db 972 delaycount = readcount;
6937bb75 973 }
a1bb33af 974
b08024a8 975 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
976 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
977 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
530f201e 978 if (send_longcommand(devc->serial, CMD_SET_DIVIDER,
fefc4b85 979 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 980 return SR_ERR;
a1bb33af 981
43fc7885 982 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
983 data = ((readcount - 1) & 0xffff) << 16;
984 data |= (delaycount - 1) & 0xffff;
530f201e 985 if (send_longcommand(devc->serial, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 986 return SR_ERR;
a1bb33af 987
43fc7885 988 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
989 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
990 devc->flag_reg |= FLAG_FILTER;
991 devc->rle_count = 0;
992 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
530f201e 993 if (send_longcommand(devc->serial, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 994 return SR_ERR;
a1bb33af 995
43fc7885 996 /* Start acquisition on the device. */
530f201e 997 if (send_shortcommand(devc->serial, CMD_RUN) != SR_OK)
e46b8fb1 998 return SR_ERR;
a1bb33af 999
fefc4b85 1000 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1001 cb_data);
a1bb33af 1002
b53738ba
UH
1003 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1004 sr_err("ols: %s: packet malloc failed", __func__);
1005 return SR_ERR_MALLOC;
1006 }
1007
1008 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1009 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1010 g_free(packet);
b53738ba
UH
1011 return SR_ERR_MALLOC;
1012 }
1013
43fc7885 1014 /* Send header packet to the session bus. */
5a2326a7 1015 packet->type = SR_DF_HEADER;
43fc7885 1016 packet->payload = (unsigned char *)header;
a1bb33af
UH
1017 header->feed_version = 1;
1018 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1019 sr_session_send(cb_data, packet);
1020
1021 /* Send metadata about the SR_DF_LOGIC packets to come. */
1022 packet->type = SR_DF_META_LOGIC;
1023 packet->payload = &meta;
fefc4b85 1024 meta.samplerate = devc->cur_samplerate;
f366e86c 1025 meta.num_probes = NUM_PROBES;
3cd3a20b 1026 sr_session_send(cb_data, packet);
c0a4b971 1027
a1bb33af
UH
1028 g_free(header);
1029 g_free(packet);
1030
e46b8fb1 1031 return SR_OK;
a1bb33af
UH
1032}
1033
3cd3a20b 1034/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
69b07d14 1035static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
a1bb33af 1036{
17e1afcb 1037 /* Avoid compiler warnings. */
26bf9d56 1038 (void)cb_data;
afc8e4de 1039
26bf9d56 1040 abort_acquisition(sdi);
3010f21c
UH
1041
1042 return SR_OK;
a1bb33af
UH
1043}
1044
c09f0b57 1045SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1046 .name = "ols",
1047 .longname = "Openbench Logic Sniffer",
1048 .api_version = 1,
1049 .init = hw_init,
1050 .cleanup = hw_cleanup,
61136ea6 1051 .scan = hw_scan,
811deee4
BV
1052 .dev_list = hw_dev_list,
1053 .dev_clear = hw_cleanup,
e7eb703f
UH
1054 .dev_open = hw_dev_open,
1055 .dev_close = hw_dev_close,
dddfb3db 1056 .info_get = hw_info_get,
a9a245b4 1057 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1058 .dev_acquisition_start = hw_dev_acquisition_start,
1059 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1060 .priv = NULL,
a1bb33af 1061};