2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
39 static GSList *device_instances = NULL;
41 // XXX These should be per device
42 static struct ftdi_context ftdic;
43 static uint64_t cur_samplerate = 0;
44 static uint32_t limit_msec = 0;
45 static struct timeval start_tv;
46 static int cur_firmware = -1;
47 static int num_probes = 0;
48 static int samples_per_event = 0;
50 static uint64_t supported_samplerates[] = {
61 static struct samplerates samplerates = {
65 supported_samplerates,
68 static int capabilities[] = {
72 /* These are really implemented in the driver, not the hardware. */
77 /* Force the FPGA to reboot. */
78 static uint8_t suicide[] = {
79 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
82 /* Prepare to upload firmware (FPGA specific). */
83 static uint8_t init[] = {
84 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
87 /* Initialize the logic analyzer mode. */
88 static uint8_t logic_mode_start[] = {
89 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
90 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
93 static const char *firmware_files[] =
95 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
96 "asix-sigma-100.fw", /* 100 MHz */
97 "asix-sigma-200.fw", /* 200 MHz */
98 "asix-sigma-50sync.fw", /* Asynchronous sampling */
99 "asix-sigma-phasor.fw", /* Frequency counter */
102 static int sigma_read(void* buf, size_t size)
106 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
108 g_warning("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&ftdic));
115 static int sigma_write(void *buf, size_t size)
119 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
121 g_warning("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&ftdic));
123 } else if ((size_t) ret != size) {
124 g_warning("ftdi_write_data did not complete write\n");
130 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
133 uint8_t buf[len + 2];
136 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
137 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
139 for (i = 0; i < len; ++i) {
140 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
141 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
144 return sigma_write(buf, idx);
147 static int sigma_set_register(uint8_t reg, uint8_t value)
149 return sigma_write_register(reg, &value, 1);
152 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
156 buf[0] = REG_ADDR_LOW | (reg & 0xf);
157 buf[1] = REG_ADDR_HIGH | (reg >> 4);
158 buf[2] = REG_READ_ADDR;
160 sigma_write(buf, sizeof(buf));
162 return sigma_read(data, len);
165 static uint8_t sigma_get_register(uint8_t reg)
169 if (1 != sigma_read_register(reg, &value, 1)) {
170 g_warning("Sigma_get_register: 1 byte expected");
177 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
180 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
182 REG_READ_ADDR | NEXT_REG,
183 REG_READ_ADDR | NEXT_REG,
184 REG_READ_ADDR | NEXT_REG,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
191 sigma_write(buf, sizeof(buf));
193 sigma_read(result, sizeof(result));
195 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
196 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
207 /* Send the startchunk. Index start with 1. */
208 buf[0] = startchunk >> 8;
209 buf[1] = startchunk & 0xff;
210 sigma_write_register(WRITE_MEMROW, buf, 2);
213 buf[idx++] = REG_DRAM_BLOCK;
214 buf[idx++] = REG_DRAM_WAIT_ACK;
216 for (i = 0; i < numchunks; ++i) {
217 /* Alternate bit to copy from DRAM to cache. */
218 if (i != (numchunks - 1))
219 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
221 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
223 if (i != (numchunks - 1))
224 buf[idx++] = REG_DRAM_WAIT_ACK;
227 sigma_write(buf, idx);
229 return sigma_read(data, numchunks * CHUNK_SIZE);
232 /* Generate the bitbang stream for programming the FPGA. */
233 static int bin2bitbang(const char *filename,
234 unsigned char **buf, size_t *buf_size)
238 unsigned long offset = 0;
240 uint8_t *compressed_buf, *firmware;
241 uLongf csize, fwsize;
242 const int buffer_size = 65536;
245 uint32_t imm = 0x3f6df2ab;
247 f = fopen(filename, "r");
249 g_warning("fopen(\"%s\", \"r\")", filename);
253 if (-1 == fseek(f, 0, SEEK_END)) {
254 g_warning("fseek on %s failed", filename);
259 file_size = ftell(f);
261 fseek(f, 0, SEEK_SET);
263 compressed_buf = g_malloc(file_size);
264 firmware = g_malloc(buffer_size);
266 if (!compressed_buf || !firmware) {
267 g_warning("Error allocating buffers");
272 while ((c = getc(f)) != EOF) {
273 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
274 compressed_buf[csize++] = c ^ imm;
278 fwsize = buffer_size;
279 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
281 g_free(compressed_buf);
283 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
287 g_free(compressed_buf);
289 *buf_size = fwsize * 2 * 8;
291 *buf = p = (unsigned char *)g_malloc(*buf_size);
294 g_warning("Error allocating buffers");
298 for (i = 0; i < fwsize; ++i) {
299 for (bit = 7; bit >= 0; --bit) {
300 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
301 p[offset++] = v | 0x01;
308 if (offset != *buf_size) {
310 g_warning("Error reading firmware %s "
311 "offset=%ld, file_size=%ld, buf_size=%zd\n",
312 filename, offset, file_size, *buf_size);
320 static int hw_init(char *deviceinfo)
322 struct sigrok_device_instance *sdi;
324 deviceinfo = deviceinfo;
328 /* Look for SIGMAs. */
329 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
330 USB_DESCRIPTION, NULL) < 0)
333 /* Register SIGMA device. */
334 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
335 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
339 device_instances = g_slist_append(device_instances, sdi);
341 /* We will open the device again when we need it. */
342 ftdi_usb_close(&ftdic);
347 static int upload_firmware(int firmware_idx)
353 unsigned char result[32];
354 char firmware_path[128];
356 /* Make sure it's an ASIX SIGMA. */
357 if ((ret = ftdi_usb_open_desc(&ftdic,
358 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
359 g_warning("ftdi_usb_open failed: %s",
360 ftdi_get_error_string(&ftdic));
364 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
365 g_warning("ftdi_set_bitmode failed: %s",
366 ftdi_get_error_string(&ftdic));
370 /* Four times the speed of sigmalogan - Works well. */
371 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
372 g_warning("ftdi_set_baudrate failed: %s",
373 ftdi_get_error_string(&ftdic));
377 /* Force the FPGA to reboot. */
378 sigma_write(suicide, sizeof(suicide));
379 sigma_write(suicide, sizeof(suicide));
380 sigma_write(suicide, sizeof(suicide));
381 sigma_write(suicide, sizeof(suicide));
383 /* Prepare to upload firmware (FPGA specific). */
384 sigma_write(init, sizeof(init));
386 ftdi_usb_purge_buffers(&ftdic);
388 /* Wait until the FPGA asserts INIT_B. */
390 ret = sigma_read(result, 1);
391 if (result[0] & 0x20)
395 /* Prepare firmware */
396 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
397 firmware_files[firmware_idx]);
399 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
400 g_warning("An error occured while reading the firmware: %s",
405 /* Upload firmare. */
406 sigma_write(buf, buf_size);
410 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
411 g_warning("ftdi_set_bitmode failed: %s",
412 ftdi_get_error_string(&ftdic));
416 ftdi_usb_purge_buffers(&ftdic);
418 /* Discard garbage. */
419 while (1 == sigma_read(&pins, 1))
422 /* Initialize the logic analyzer mode. */
423 sigma_write(logic_mode_start, sizeof(logic_mode_start));
425 /* Expect a 3 byte reply. */
426 ret = sigma_read(result, 3);
428 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
429 g_warning("Configuration failed. Invalid reply received.");
433 cur_firmware = firmware_idx;
438 static int hw_opendev(int device_index)
440 struct sigrok_device_instance *sdi;
443 /* Make sure it's an ASIX SIGMA */
444 if ((ret = ftdi_usb_open_desc(&ftdic,
445 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
447 g_warning("ftdi_usb_open failed: %s",
448 ftdi_get_error_string(&ftdic));
453 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
456 sdi->status = ST_ACTIVE;
461 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
467 for (i = 0; supported_samplerates[i]; i++) {
468 if (supported_samplerates[i] == samplerate)
471 if (supported_samplerates[i] == 0)
472 return SIGROK_ERR_SAMPLERATE;
474 if (samplerate <= MHZ(50)) {
475 ret = upload_firmware(0);
477 // XXX: Setup divider if < 50 MHz
479 if (samplerate == MHZ(100)) {
480 ret = upload_firmware(1);
483 else if (samplerate == MHZ(200)) {
484 ret = upload_firmware(2);
488 cur_samplerate = samplerate;
489 samples_per_event = 16 / num_probes;
491 g_message("Firmware uploaded");
496 static void hw_closedev(int device_index)
498 device_index = device_index;
500 ftdi_usb_close(&ftdic);
503 static void hw_cleanup(void)
507 static void *hw_get_device_info(int device_index, int device_info_id)
509 struct sigrok_device_instance *sdi;
512 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
513 fprintf(stderr, "It's NULL.\n");
517 switch (device_info_id) {
522 info = GINT_TO_POINTER(16);
527 case DI_TRIGGER_TYPES:
528 info = 0; //TRIGGER_TYPES;
530 case DI_CUR_SAMPLERATE:
531 info = &cur_samplerate;
538 static int hw_get_status(int device_index)
540 struct sigrok_device_instance *sdi;
542 sdi = get_sigrok_device_instance(device_instances, device_index);
549 static int *hw_get_capabilities(void)
554 static int hw_set_configuration(int device_index, int capability, void *value)
556 struct sigrok_device_instance *sdi;
559 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
562 if (capability == HWCAP_SAMPLERATE) {
563 ret = set_samplerate(sdi, *(uint64_t*) value);
564 } else if (capability == HWCAP_PROBECONFIG) {
566 } else if (capability == HWCAP_LIMIT_MSEC) {
567 limit_msec = strtoull(value, NULL, 10);
577 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
578 * Each event is 20ns apart, and can contain multiple samples.
580 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
581 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
582 * For 50 MHz and below, events contain one sample for each channel,
583 * spread 20 ns apart.
585 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
586 uint16_t *lastsample, void *user_data)
589 uint16_t samples[65536 * samples_per_event];
590 struct datafeed_packet packet;
591 int i, j, k, l, numpad, tosend;
592 size_t n = 0, sent = 0;
593 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
598 for (i = 0; i < 64; ++i) {
599 ts = *(uint16_t *) &buf[i * 16];
600 tsdiff = ts - *lastts;
603 /* Pad last sample up to current point. */
604 numpad = tsdiff * samples_per_event - clustersize;
606 for (j = 0; j < numpad; ++j)
607 samples[j] = *lastsample;
612 event = (uint16_t *) &buf[i * 16 + 2];
616 /* For each event in cluster. */
617 for (j = 0; j < 7; ++j) {
619 /* For each sample in event. */
620 for (k = 0; k < samples_per_event; ++k) {
623 /* For each probe. */
624 for (l = 0; l < num_probes; ++l)
625 cur_sample |= (!!(event[j] & (1 << (l *
626 samples_per_event + k))))
629 samples[n++] = cur_sample;
633 *lastsample = samples[n - 1];
635 /* Send to sigrok. */
638 tosend = MIN(2048, n - sent);
640 packet.type = DF_LOGIC16;
641 packet.length = tosend * sizeof(uint16_t);
642 packet.payload = samples + sent;
643 session_bus(user_data, &packet);
652 static int receive_data(int fd, int revents, void *user_data)
654 struct datafeed_packet packet;
655 const int chunks_per_read = 32;
656 unsigned char buf[chunks_per_read * CHUNK_SIZE];
657 int bufsz, numchunks, curchunk, i, newchunks;
658 uint32_t triggerpos, stoppos, running_msec;
661 uint16_t lastsample = 0;
666 /* Get the current position. */
667 sigma_read_pos(&stoppos, &triggerpos);
668 numchunks = stoppos / 512;
670 /* Check if the has expired, or memory is full. */
671 gettimeofday(&tv, 0);
672 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
673 (tv.tv_usec - start_tv.tv_usec) / 1000;
675 if (running_msec < limit_msec && numchunks < 32767)
678 /* Stop acqusition. */
679 sigma_set_register(WRITE_MODE, 0x11);
681 /* Set SDRAM Read Enable. */
682 sigma_set_register(WRITE_MODE, 0x02);
684 /* Get the current position. */
685 sigma_read_pos(&stoppos, &triggerpos);
687 /* Read mode status. We will care for this later. */
688 sigma_get_register(READ_MODE);
690 /* Download sample data. */
691 for (curchunk = 0; curchunk < numchunks;) {
692 newchunks = MIN(chunks_per_read, numchunks - curchunk);
694 g_message("Downloading sample data: %.0f %%",
695 100.0 * curchunk / numchunks);
697 bufsz = sigma_read_dram(curchunk, newchunks, buf);
701 lastts = *(uint16_t *) buf - 1;
703 /* Decode chunks and send them to sigrok. */
704 for (i = 0; i < newchunks; ++i) {
705 decode_chunk_ts(buf + (i * CHUNK_SIZE),
706 &lastts, &lastsample, user_data);
709 curchunk += newchunks;
713 packet.type = DF_END;
715 session_bus(user_data, &packet);
720 static int hw_start_acquisition(int device_index, gpointer session_device_id)
722 struct sigrok_device_instance *sdi;
723 struct datafeed_packet packet;
724 struct datafeed_header header;
725 uint8_t trigger_option[2] = { 0x38, 0x00 };
727 session_device_id = session_device_id;
729 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
732 device_index = device_index;
734 if (cur_firmware == -1) {
735 /* Samplerate has not been set. Default to 200 MHz */
736 set_samplerate(sdi, 200);
739 /* Setup trigger (by trigger-in). */
740 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
742 /* More trigger setup. */
743 sigma_write_register(WRITE_TRIGGER_OPTION,
744 trigger_option, sizeof(trigger_option));
746 /* Trigger normal (falling edge). */
747 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08);
749 /* Set clock select register. */
750 if (cur_samplerate == MHZ(200))
751 /* Enable 4 probes. */
752 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
753 else if (cur_samplerate == MHZ(100))
754 /* Enable 8 probes. */
755 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
758 * 50 MHz mode (or fraction thereof)
759 * Any fraction down to 50 MHz / 256 can be used,
760 * but is not suppoted by Sigrok API.
763 int frac = MHZ(50) / cur_samplerate - 1;
765 struct clockselect_50 clockselect = {
768 .disabled_probes = 0,
771 sigma_write_register(WRITE_CLOCK_SELECT,
772 (uint8_t *) &clockselect,
773 sizeof(clockselect));
777 /* Setup maximum post trigger time. */
778 sigma_set_register(WRITE_POST_TRIGGER, 0xff);
780 /* Start acqusition (software trigger start). */
781 gettimeofday(&start_tv, 0);
782 sigma_set_register(WRITE_MODE, 0x0d);
784 /* Add capture source. */
785 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
787 receive_data(0, 1, session_device_id);
789 /* Send header packet to the session bus. */
790 packet.type = DF_HEADER;
791 packet.length = sizeof(struct datafeed_header);
792 packet.payload = &header;
793 header.feed_version = 1;
794 gettimeofday(&header.starttime, NULL);
795 header.samplerate = cur_samplerate;
796 header.protocol_id = PROTO_RAW;
797 header.num_probes = num_probes;
798 session_bus(session_device_id, &packet);
803 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
805 device_index = device_index;
806 session_device_id = session_device_id;
808 /* Stop acquisition. */
809 sigma_set_register(WRITE_MODE, 0x11);
811 // XXX Set some state to indicate that data should be sent to sigrok
812 // Now, we just wait for timeout
815 struct device_plugin asix_sigma_plugin_info = {
825 hw_set_configuration,
826 hw_start_acquisition,