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204b1629 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
204b1629 | 3 | * |
3ba56876 | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
204b1629 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
204b1629 UH |
8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
3ba56876 | 23 | #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H |
24 | #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
25 | ||
26 | #include <stdint.h> | |
4154a516 | 27 | #include <stdlib.h> |
3ba56876 | 28 | #include <glib.h> |
29 | #include <ftdi.h> | |
30 | #include <string.h> | |
31 | #include <libsigrok/libsigrok.h> | |
32 | #include "libsigrok-internal.h" | |
28a35d8a | 33 | |
f272d7dd UH |
34 | #define LOG_PREFIX "asix-sigma" |
35 | ||
de3f7acb GS |
36 | /* |
37 | * Triggers are not working in this implementation. Stop claiming | |
38 | * support for the feature which effectively is not available, until | |
39 | * the implementation got fixed. Yet keep the code in place and allow | |
40 | * developers to turn on this switch during development. | |
41 | */ | |
8a57728d | 42 | #define ASIX_SIGMA_WITH_TRIGGER 1 |
de3f7acb | 43 | |
53a939ab GS |
44 | /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ |
45 | #define ASIX_WITH_OMEGA 0 | |
46 | ||
47 | #define USB_VENDOR_ASIX 0xa600 | |
48 | #define USB_PRODUCT_SIGMA 0xa000 | |
49 | #define USB_PRODUCT_OMEGA 0xa004 | |
50 | ||
51 | enum asix_device_type { | |
52 | ASIX_TYPE_NONE, | |
53 | ASIX_TYPE_SIGMA, | |
54 | ASIX_TYPE_OMEGA, | |
55 | }; | |
3ba56876 | 56 | |
3f5f5484 GS |
57 | /* Mask to isolate one bit, mask to span a number of bits. */ |
58 | #define BIT(pos) (1UL << (pos)) | |
59 | #define BITS_MASK(count) ((1UL << (count)) - 1) | |
60 | ||
61 | #define HI4(b) (((b) >> 4) & 0x0f) | |
62 | #define LO4(b) (((b) >> 0) & 0x0f) | |
63 | ||
7c41c420 GS |
64 | /* |
65 | * FPGA commands are 8bits wide. The upper nibble is a command opcode, | |
66 | * the lower nibble can carry operand values. 8bit register addresses | |
67 | * and 8bit data values get communicated in two steps. | |
68 | */ | |
69 | ||
70 | /* Register access. */ | |
71 | #define REG_ADDR_LOW (0x0 << 4) | |
72 | #define REG_ADDR_HIGH (0x1 << 4) | |
73 | #define REG_DATA_LOW (0x2 << 4) | |
74 | #define REG_DATA_HIGH_WRITE (0x3 << 4) | |
75 | #define REG_READ_ADDR (0x4 << 4) | |
3f5f5484 GS |
76 | #define REG_ADDR_ADJUST BIT(0) /* Auto adjust register address. */ |
77 | #define REG_ADDR_DOWN BIT(1) /* 1 decrement, 0 increment. */ | |
7c41c420 GS |
78 | #define REG_ADDR_INC (REG_ADDR_ADJUST) |
79 | #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) | |
80 | ||
81 | /* Sample memory access. */ | |
82 | #define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ | |
83 | #define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ | |
84 | #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ | |
85 | #define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ | |
86 | #define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ | |
87 | #define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) | |
88 | ||
89 | /* | |
90 | * Registers at a specific address can have different meanings depending | |
91 | * on whether data is read or written. This is why direction is part of | |
92 | * the programming language identifiers. | |
93 | * | |
94 | * The vendor documentation suggests that in addition to the first 16 | |
95 | * register addresses which implement the logic analyzer's feature set, | |
96 | * there are 240 more registers in the 16 to 255 address range which | |
97 | * are available to applications and plugin features. Can libsigrok's | |
98 | * asix-sigma driver store configuration data there, to avoid expensive | |
99 | * operations (think: firmware re-load). | |
53c8a99c GS |
100 | * |
101 | * Update: The documentation may be incorrect, or the FPGA netlist may | |
102 | * be incomplete. Experiments show that registers beyond 0x0f can get | |
103 | * accessed, USB communication passes, but data bytes are always 0xff. | |
104 | * Are several firmware versions around, and the documentation does not | |
105 | * match the one that ships with sigrok? | |
7c41c420 GS |
106 | */ |
107 | ||
fefa1800 | 108 | enum sigma_write_register { |
28a35d8a | 109 | WRITE_CLOCK_SELECT = 0, |
9fb4c632 GS |
110 | WRITE_TRIGGER_SELECT = 1, |
111 | WRITE_TRIGGER_SELECT2 = 2, | |
28a35d8a HE |
112 | WRITE_MODE = 3, |
113 | WRITE_MEMROW = 4, | |
114 | WRITE_POST_TRIGGER = 5, | |
115 | WRITE_TRIGGER_OPTION = 6, | |
116 | WRITE_PIN_VIEW = 7, | |
9fb4c632 | 117 | /* Unassigned register locations. */ |
fefa1800 | 118 | WRITE_TEST = 15, |
53c8a99c GS |
119 | /* Reserved for plugin features. */ |
120 | REG_PLUGIN_START = 16, | |
121 | REG_PLUGIN_STOP = 256, | |
28a35d8a HE |
122 | }; |
123 | ||
fefa1800 | 124 | enum sigma_read_register { |
28a35d8a HE |
125 | READ_ID = 0, |
126 | READ_TRIGGER_POS_LOW = 1, | |
127 | READ_TRIGGER_POS_HIGH = 2, | |
128 | READ_TRIGGER_POS_UP = 3, | |
129 | READ_STOP_POS_LOW = 4, | |
130 | READ_STOP_POS_HIGH = 5, | |
131 | READ_STOP_POS_UP = 6, | |
132 | READ_MODE = 7, | |
133 | READ_PIN_CHANGE_LOW = 8, | |
134 | READ_PIN_CHANGE_HIGH = 9, | |
135 | READ_BLOCK_LAST_TS_LOW = 10, | |
136 | READ_BLOCK_LAST_TS_HIGH = 11, | |
9fb4c632 GS |
137 | READ_BLOCK_TS_OVERRUN = 12, |
138 | READ_PIN_VIEW = 13, | |
139 | /* Unassigned register location. */ | |
fefa1800 | 140 | READ_TEST = 15, |
53c8a99c | 141 | /* Reserved for plugin features. See above. */ |
28a35d8a HE |
142 | }; |
143 | ||
3f5f5484 GS |
144 | #define CLKSEL_CLKSEL8 BIT(0) |
145 | #define CLKSEL_PINMASK BITS_MASK(4) | |
146 | #define CLKSEL_RISING BIT(4) | |
147 | #define CLKSEL_FALLING BIT(5) | |
2d8a5089 | 148 | |
3f5f5484 | 149 | #define TRGSEL_SELINC_MASK BITS_MASK(2) |
0f017b7d | 150 | #define TRGSEL_SELINC_SHIFT 0 |
3f5f5484 | 151 | #define TRGSEL_SELRES_MASK BITS_MASK(2) |
0f017b7d | 152 | #define TRGSEL_SELRES_SHIFT 2 |
3f5f5484 | 153 | #define TRGSEL_SELA_MASK BITS_MASK(2) |
0f017b7d | 154 | #define TRGSEL_SELA_SHIFT 4 |
3f5f5484 | 155 | #define TRGSEL_SELB_MASK BITS_MASK(2) |
0f017b7d | 156 | #define TRGSEL_SELB_SHIFT 6 |
3f5f5484 | 157 | #define TRGSEL_SELC_MASK BITS_MASK(2) |
16791da9 | 158 | #define TRGSEL_SELC_SHIFT 8 |
3f5f5484 | 159 | #define TRGSEL_SELPRESC_MASK BITS_MASK(4) |
16791da9 GS |
160 | #define TRGSEL_SELPRESC_SHIFT 12 |
161 | ||
162 | enum trgsel_selcode_t { | |
163 | TRGSEL_SELCODE_LEVEL = 0, | |
164 | TRGSEL_SELCODE_FALL = 1, | |
165 | TRGSEL_SELCODE_RISE = 2, | |
166 | TRGSEL_SELCODE_EVENT = 3, | |
167 | TRGSEL_SELCODE_NEVER = 3, | |
168 | }; | |
0f017b7d | 169 | |
3f5f5484 GS |
170 | #define TRGSEL2_PINS_MASK BITS_MASK(3) |
171 | #define TRGSEL2_PINPOL_RISE BIT(3) | |
172 | #define TRGSEL2_LUT_ADDR_MASK BITS_MASK(4) | |
173 | #define TRGSEL2_LUT_WRITE BIT(4) | |
174 | #define TRGSEL2_RESET BIT(5) | |
175 | #define TRGSEL2_LEDSEL0 BIT(6) | |
176 | #define TRGSEL2_LEDSEL1 BIT(7) | |
57bbf56b | 177 | |
22f64ed8 | 178 | /* WRITE_MODE register fields. */ |
3f5f5484 GS |
179 | #define WMR_SDRAMWRITEEN BIT(0) |
180 | #define WMR_SDRAMREADEN BIT(1) | |
181 | #define WMR_TRGRES BIT(2) | |
182 | #define WMR_TRGEN BIT(3) | |
183 | #define WMR_FORCESTOP BIT(4) | |
184 | #define WMR_TRGSW BIT(5) | |
22f64ed8 | 185 | /* not used: bit position 6 */ |
3f5f5484 | 186 | #define WMR_SDRAMINIT BIT(7) |
22f64ed8 GS |
187 | |
188 | /* READ_MODE register fields. */ | |
3f5f5484 GS |
189 | #define RMR_SDRAMWRITEEN BIT(0) |
190 | #define RMR_SDRAMREADEN BIT(1) | |
22f64ed8 | 191 | /* not used: bit position 2 */ |
3f5f5484 GS |
192 | #define RMR_TRGEN BIT(3) |
193 | #define RMR_ROUND BIT(4) | |
194 | #define RMR_TRIGGERED BIT(5) | |
195 | #define RMR_POSTTRIGGERED BIT(6) | |
22f64ed8 GS |
196 | /* not used: bit position 7 */ |
197 | ||
a53b8e4d GS |
198 | /* |
199 | * Trigger options. First and second write are similar, but _some_ | |
200 | * positions change their meaning. | |
201 | */ | |
3f5f5484 GS |
202 | #define TRGOPT_TRGIEN BIT(7) |
203 | #define TRGOPT_TRGOEN BIT(6) | |
204 | #define TRGOPT_TRGOINEN BIT(5) /* 1st write */ | |
a53b8e4d | 205 | #define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */ |
3f5f5484 | 206 | #define TRGOPT_TRGOEVNTEN BIT(4) /* 1st write */ |
a53b8e4d | 207 | #define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */ |
3f5f5484 | 208 | #define TRGOPT_TRGOOUTEN BIT(3) /* 1st write */ |
a53b8e4d | 209 | #define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */ |
3f5f5484 GS |
210 | #define TRGOPT_TRGOUTR_OUT BIT(1) |
211 | #define TRGOPT_TRGOUTR_EN BIT(0) | |
a53b8e4d GS |
212 | #define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN) |
213 | ||
fd830beb | 214 | /* |
5b1d15ef GS |
215 | * Layout of the sample data DRAM, which will be downloaded to the PC: |
216 | * | |
217 | * Sigma memory is organized in 32K rows. Each row contains 64 clusters. | |
2c33b092 GS |
218 | * Each cluster contains a timestamp (16bit) and 7 events (16bits each). |
219 | * Events contain 16 bits of sample data (potentially taken at multiple | |
220 | * sample points, see below). | |
221 | * | |
222 | * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The | |
223 | * size of a memory row is 1024 bytes. Assuming x16 organization of the | |
224 | * memory array, address specs (sample count, trigger position) are kept | |
225 | * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit | |
226 | * refer to the "event" within the row. Because there is one timestamp for | |
227 | * seven events each, one memory row can hold up to 64x7 == 448 events. | |
5b1d15ef GS |
228 | * |
229 | * Sample data is represented in 16bit quantities. The first sample in | |
230 | * the cluster corresponds to the cluster's timestamp. Each next sample | |
231 | * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is | |
232 | * one sample period, according to the samplerate). In the absence of | |
233 | * pin level changes, no data is provided (RLE compression). A cluster | |
234 | * is enforced for each 64K ticks of the timestamp, to reliably handle | |
2c33b092 | 235 | * rollover and determine the next timestamp of the next cluster. |
5b1d15ef | 236 | * |
2c33b092 GS |
237 | * For samplerates up to 50MHz, an event directly translates to one set |
238 | * of sample data at a single sample point, spanning up to 16 channels. | |
5b1d15ef GS |
239 | * For samplerates of 100MHz, there is one 16 bit entity for each 20ns |
240 | * period (50MHz rate). The 16 bit memory contains 2 samples of up to | |
241 | * 8 channels. Bits of multiple samples are interleaved. For samplerates | |
242 | * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, | |
243 | * each 5ns apart. | |
fd830beb MV |
244 | */ |
245 | ||
2c33b092 GS |
246 | #define ROW_COUNT 32768 |
247 | #define ROW_LENGTH_BYTES 1024 | |
248 | #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) | |
249 | #define ROW_SHIFT 9 /* log2 of u16 count */ | |
3f5f5484 | 250 | #define ROW_MASK BITS_MASK(ROW_SHIFT) |
2c33b092 GS |
251 | #define EVENTS_PER_CLUSTER 7 |
252 | #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) | |
253 | #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) | |
fd830beb | 254 | |
fd830beb | 255 | struct sigma_dram_line { |
2c33b092 | 256 | struct sigma_dram_cluster { |
2a62a9c4 GS |
257 | uint16_t timestamp; |
258 | uint16_t samples[EVENTS_PER_CLUSTER]; | |
2c33b092 | 259 | } cluster[CLUSTERS_PER_ROW]; |
fd830beb MV |
260 | }; |
261 | ||
57bbf56b HE |
262 | /* The effect of all these are still a bit unclear. */ |
263 | struct triggerinout { | |
8bd4dc87 GS |
264 | gboolean trgout_resistor_enable, trgout_resistor_pullup; |
265 | gboolean trgout_resistor_enable2, trgout_resistor_pullup2; | |
266 | gboolean trgout_bytrigger, trgout_byevent, trgout_bytriggerin; | |
267 | gboolean trgout_long, trgout_pin; /* 1ms pulse, 1k resistor */ | |
268 | gboolean trgin_negate, trgout_enable, trgin_enable; | |
57bbf56b HE |
269 | }; |
270 | ||
ee492173 | 271 | struct triggerlut { |
ee492173 | 272 | uint16_t m0d[4], m1d[4], m2d[4]; |
16791da9 | 273 | uint16_t m3q, m3s, m4; |
ee492173 | 274 | struct { |
8bd4dc87 GS |
275 | uint8_t selpresc; |
276 | uint8_t sela, selb, selc; | |
277 | uint8_t selinc, selres; | |
278 | uint16_t cmpa, cmpb; | |
ee492173 HE |
279 | } params; |
280 | }; | |
281 | ||
c53d793f HE |
282 | /* Trigger configuration */ |
283 | struct sigma_trigger { | |
ba7dd8bb | 284 | /* Only two channels can be used in mask. */ |
a42aec7f HE |
285 | uint16_t risingmask; |
286 | uint16_t fallingmask; | |
c53d793f HE |
287 | |
288 | /* Simple trigger support (<= 50 MHz). */ | |
289 | uint16_t simplemask; | |
290 | uint16_t simplevalue; | |
291 | ||
c53d793f HE |
292 | /* TODO: Advanced trigger support (boolean expressions). */ |
293 | }; | |
294 | ||
295 | /* Events for trigger operation. */ | |
296 | enum triggerop { | |
297 | OP_LEVEL = 1, | |
298 | OP_NOT, | |
299 | OP_RISE, | |
300 | OP_FALL, | |
301 | OP_RISEFALL, | |
302 | OP_NOTRISE, | |
303 | OP_NOTFALL, | |
304 | OP_NOTRISEFALL, | |
305 | }; | |
306 | ||
307 | /* Logical functions for trigger operation. */ | |
308 | enum triggerfunc { | |
309 | FUNC_AND = 1, | |
310 | FUNC_NAND, | |
311 | FUNC_OR, | |
312 | FUNC_NOR, | |
313 | FUNC_XOR, | |
314 | FUNC_NXOR, | |
315 | }; | |
316 | ||
6aac7737 HE |
317 | struct sigma_state { |
318 | enum { | |
319 | SIGMA_UNINITIALIZED = 0, | |
1bb9dc82 | 320 | SIGMA_CONFIG, |
6aac7737 HE |
321 | SIGMA_IDLE, |
322 | SIGMA_CAPTURE, | |
dde0175d | 323 | SIGMA_STOPPING, |
6aac7737 HE |
324 | SIGMA_DOWNLOAD, |
325 | } state; | |
6aac7737 HE |
326 | uint16_t lastts; |
327 | uint16_t lastsample; | |
6aac7737 HE |
328 | }; |
329 | ||
80e717b3 GS |
330 | enum sigma_firmware_idx { |
331 | SIGMA_FW_NONE, | |
332 | SIGMA_FW_50MHZ, | |
333 | SIGMA_FW_100MHZ, | |
334 | SIGMA_FW_200MHZ, | |
335 | SIGMA_FW_SYNC, | |
336 | SIGMA_FW_FREQ, | |
337 | }; | |
338 | ||
2d8a5089 GS |
339 | enum ext_clock_edge_t { |
340 | SIGMA_CLOCK_EDGE_RISING, | |
341 | SIGMA_CLOCK_EDGE_FALLING, | |
342 | SIGMA_CLOCK_EDGE_EITHER, | |
343 | }; | |
344 | ||
98b43eb3 GS |
345 | struct submit_buffer; |
346 | ||
0e1357e8 | 347 | struct dev_context { |
53a939ab GS |
348 | struct { |
349 | uint16_t vid, pid; | |
350 | uint32_t serno; | |
351 | uint16_t prefix; | |
352 | enum asix_device_type type; | |
353 | } id; | |
7fe1f91f GS |
354 | struct { |
355 | struct ftdi_context ctx; | |
356 | gboolean is_open, must_close; | |
357 | } ftdi; | |
2d8a5089 GS |
358 | struct { |
359 | uint64_t samplerate; | |
360 | gboolean use_ext_clock; | |
361 | size_t clock_pin; | |
362 | enum ext_clock_edge_t clock_edge; | |
363 | } clock; | |
156b6879 GS |
364 | struct { |
365 | /* | |
366 | * User specified configuration values, in contrast to | |
367 | * internal arrangement of acquisition, and submission | |
368 | * to the session feed. | |
369 | */ | |
370 | struct sr_sw_limits config; | |
371 | struct sr_sw_limits acquire; | |
372 | struct sr_sw_limits submit; | |
373 | } limit; | |
80e717b3 | 374 | enum sigma_firmware_idx firmware_idx; |
3d9373af GS |
375 | size_t num_channels; |
376 | size_t samples_per_event; | |
efad7ccc | 377 | uint64_t capture_ratio; |
99965709 | 378 | struct sigma_trigger trigger; |
3d9373af | 379 | gboolean use_triggers; |
99965709 | 380 | struct sigma_state state; |
98b43eb3 | 381 | struct submit_buffer *buffer; |
99965709 HE |
382 | }; |
383 | ||
7fe1f91f GS |
384 | /* "Automatic" and forced USB connection open/close support. */ |
385 | SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi); | |
386 | SR_PRIV int sigma_check_close(struct dev_context *devc); | |
387 | SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi); | |
388 | SR_PRIV int sigma_force_close(struct dev_context *devc); | |
389 | ||
53c8a99c GS |
390 | /* Save configuration across sessions, to reduce cost of continuation. */ |
391 | SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi); | |
392 | SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi); | |
393 | ||
a426f74a | 394 | /* Send register content (simple and complex) to the hardware. */ |
9b4d261f GS |
395 | SR_PRIV int sigma_write_register(struct dev_context *devc, |
396 | uint8_t reg, uint8_t *data, size_t len); | |
397 | SR_PRIV int sigma_set_register(struct dev_context *devc, | |
398 | uint8_t reg, uint8_t value); | |
399 | SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, | |
400 | struct triggerlut *lut); | |
a426f74a GS |
401 | |
402 | /* Samplerate constraints check, get/set/list helpers. */ | |
5e78a564 | 403 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); |
abcd4771 | 404 | SR_PRIV GVariant *sigma_get_samplerates_list(void); |
a426f74a GS |
405 | |
406 | /* Preparation of data acquisition, spec conversion, hardware configuration. */ | |
5e78a564 GS |
407 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); |
408 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); | |
3ba56876 | 409 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); |
9b4d261f GS |
410 | SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, |
411 | struct triggerlut *lut); | |
3ba56876 | 412 | |
a426f74a GS |
413 | /* Callback to periodically drive acuisition progress. */ |
414 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); | |
415 | ||
204b1629 | 416 | #endif |