[libsigrok.git] / src / hardware / asix-sigma / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
 * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
#define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H

#include <stdint.h>
#include <stdlib.h>
#include <glib.h>
#include <ftdi.h>
#include <string.h>
#include <libsigrok/libsigrok.h>
#include "libsigrok-internal.h"

#define LOG_PREFIX "asix-sigma"

/*
 * Triggers are not working in this implementation. Stop claiming
 * support for the feature which effectively is not available, until
 * the implementation got fixed. Yet keep the code in place and allow
 * developers to turn on this switch during development.
 */
#define ASIX_SIGMA_WITH_TRIGGER	0

/* Experimental support for OMEGA (scan only, operation is ENOIMPL). */
#define ASIX_WITH_OMEGA 0

#define USB_VENDOR_ASIX			0xa600
#define USB_PRODUCT_SIGMA		0xa000
#define USB_PRODUCT_OMEGA		0xa004

enum asix_device_type {
	ASIX_TYPE_NONE,
	ASIX_TYPE_SIGMA,
	ASIX_TYPE_OMEGA,
};

/*
 * FPGA commands are 8bits wide. The upper nibble is a command opcode,
 * the lower nibble can carry operand values. 8bit register addresses
 * and 8bit data values get communicated in two steps.
 */

/* Register access. */
#define REG_ADDR_LOW		(0x0 << 4)
#define REG_ADDR_HIGH		(0x1 << 4)
#define REG_DATA_LOW		(0x2 << 4)
#define REG_DATA_HIGH_WRITE	(0x3 << 4)
#define REG_READ_ADDR		(0x4 << 4)
#define REG_ADDR_ADJUST		(1 << 0) /* Auto adjust register address. */
#define REG_ADDR_DOWN		(1 << 1) /* 1 decrement, 0 increment. */
#define REG_ADDR_INC		(REG_ADDR_ADJUST)
#define REG_ADDR_DEC		(REG_ADDR_ADJUST | REG_ADDR_DOWN)

/* Sample memory access. */
#define REG_DRAM_WAIT_ACK	(0x5 << 4) /* Wait for completion. */
#define REG_DRAM_BLOCK		(0x6 << 4) /* DRAM to BRAM, plus bank select. */
#define REG_DRAM_BLOCK_BEGIN	(0x8 << 4) /* Read first BRAM bytes. */
#define REG_DRAM_BLOCK_DATA	(0xa << 4) /* Read full BRAM block. */
#define REG_DRAM_SEL_N		(0x1 << 4) /* Bank select, added to 6/8/a. */
#define REG_DRAM_SEL_BOOL(b)	((b) ? REG_DRAM_SEL_N : 0)

/*
 * Registers at a specific address can have different meanings depending
 * on whether data is read or written. This is why direction is part of
 * the programming language identifiers.
 *
 * The vendor documentation suggests that in addition to the first 16
 * register addresses which implement the logic analyzer's feature set,
 * there are 240 more registers in the 16 to 255 address range which
 * are available to applications and plugin features. Can libsigrok's
 * asix-sigma driver store configuration data there, to avoid expensive
 * operations (think: firmware re-load).
 */

enum sigma_write_register {
	WRITE_CLOCK_SELECT	= 0,
	WRITE_TRIGGER_SELECT	= 1,
	WRITE_TRIGGER_SELECT2	= 2,
	WRITE_MODE		= 3,
	WRITE_MEMROW		= 4,
	WRITE_POST_TRIGGER	= 5,
	WRITE_TRIGGER_OPTION	= 6,
	WRITE_PIN_VIEW		= 7,
	/* Unassigned register locations. */
	WRITE_TEST		= 15,
};

enum sigma_read_register {
	READ_ID			= 0,
	READ_TRIGGER_POS_LOW	= 1,
	READ_TRIGGER_POS_HIGH	= 2,
	READ_TRIGGER_POS_UP	= 3,
	READ_STOP_POS_LOW	= 4,
	READ_STOP_POS_HIGH	= 5,
	READ_STOP_POS_UP	= 6,
	READ_MODE		= 7,
	READ_PIN_CHANGE_LOW	= 8,
	READ_PIN_CHANGE_HIGH	= 9,
	READ_BLOCK_LAST_TS_LOW	= 10,
	READ_BLOCK_LAST_TS_HIGH	= 11,
	READ_BLOCK_TS_OVERRUN	= 12,
	READ_PIN_VIEW		= 13,
	/* Unassigned register location. */
	READ_TEST		= 15,
};

#define TRGSEL2_LEDSEL0		(1 << 6)
#define TRGSEL2_LEDSEL1		(1 << 7)

/* WRITE_MODE register fields. */
#define WMR_SDRAMWRITEEN	(1 << 0)
#define WMR_SDRAMREADEN		(1 << 1)
#define WMR_TRGRES		(1 << 2)
#define WMR_TRGEN		(1 << 3)
#define WMR_FORCESTOP		(1 << 4)
#define WMR_TRGSW		(1 << 5)
/* not used: bit position 6 */
#define WMR_SDRAMINIT		(1 << 7)

/* READ_MODE register fields. */
#define RMR_SDRAMWRITEEN	(1 << 0)
#define RMR_SDRAMREADEN		(1 << 1)
/* not used: bit position 2 */
#define RMR_TRGEN		(1 << 3)
#define RMR_ROUND		(1 << 4)
#define RMR_TRIGGERED		(1 << 5)
#define RMR_POSTTRIGGERED	(1 << 6)
/* not used: bit position 7 */

/*
 * Trigger options. First and second write are similar, but _some_
 * positions change their meaning.
 */
#define TRGOPT_TRGIEN		(1 << 7)
#define TRGOPT_TRGOEN		(1 << 6)
#define TRGOPT_TRGOINEN		(1 << 5) /* 1st write */
#define TRGOPT_TRGINEG		TRGOPT1_TRGOINEN /* 2nd write */
#define TRGOPT_TRGOEVNTEN	(1 << 4) /* 1st write */
#define TRGOPT_TRGOPIN		TRGOPT1_TRGOEVNTEN /* 2nd write */
#define TRGOPT_TRGOOUTEN	(1 << 3) /* 1st write */
#define TRGOPT_TRGOLONG		TRGOPT1_TRGOOUTEN /* 2nd write */
#define TRGOPT_TRGOUTR_OUT	(1 << 1)
#define TRGOPT_TRGOUTR_EN	(1 << 0)
#define TRGOPT_CLEAR_MASK	(TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN)

/*
 * Layout of the sample data DRAM, which will be downloaded to the PC:
 *
 * Sigma memory is organized in 32K rows. Each row contains 64 clusters.
 * Each cluster contains a timestamp (16bit) and 7 events (16bits each).
 * Events contain 16 bits of sample data (potentially taken at multiple
 * sample points, see below).
 *
 * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The
 * size of a memory row is 1024 bytes. Assuming x16 organization of the
 * memory array, address specs (sample count, trigger position) are kept
 * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit
 * refer to the "event" within the row. Because there is one timestamp for
 * seven events each, one memory row can hold up to 64x7 == 448 events.
 *
 * Sample data is represented in 16bit quantities. The first sample in
 * the cluster corresponds to the cluster's timestamp. Each next sample
 * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
 * one sample period, according to the samplerate). In the absence of
 * pin level changes, no data is provided (RLE compression). A cluster
 * is enforced for each 64K ticks of the timestamp, to reliably handle
 * rollover and determine the next timestamp of the next cluster.
 *
 * For samplerates up to 50MHz, an event directly translates to one set
 * of sample data at a single sample point, spanning up to 16 channels.
 * For samplerates of 100MHz, there is one 16 bit entity for each 20ns
 * period (50MHz rate). The 16 bit memory contains 2 samples of up to
 * 8 channels. Bits of multiple samples are interleaved. For samplerates
 * of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
 * each 5ns apart.
 */

#define ROW_COUNT		32768
#define ROW_LENGTH_BYTES	1024
#define ROW_LENGTH_U16		(ROW_LENGTH_BYTES / sizeof(uint16_t))
#define ROW_SHIFT		9 /* log2 of u16 count */
#define ROW_MASK		((1UL << ROW_SHIFT) - 1)
#define EVENTS_PER_CLUSTER	7
#define CLUSTERS_PER_ROW	(ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER))
#define EVENTS_PER_ROW		(CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER)

struct sigma_dram_line {
	struct sigma_dram_cluster {
		uint16_t timestamp;
		uint16_t samples[EVENTS_PER_CLUSTER];
	} cluster[CLUSTERS_PER_ROW];
};

struct clockselect_50 {
	uint8_t async;
	uint64_t fraction;
	uint16_t disabled_channels;
};

/* The effect of all these are still a bit unclear. */
struct triggerinout {
	uint8_t trgout_resistor_enable : 1;
	uint8_t trgout_resistor_pullup : 1;
	uint8_t reserved1 : 1;
	uint8_t trgout_bytrigger : 1;
	uint8_t trgout_byevent : 1;
	uint8_t trgout_bytriggerin : 1;
	uint8_t reserved2 : 2;

	/* Should be set same as the first two */
	uint8_t trgout_resistor_enable2 : 1;
	uint8_t trgout_resistor_pullup2 : 1;

	uint8_t reserved3 : 1;
	uint8_t trgout_long : 1;
	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	uint8_t trgin_negate : 1;
	uint8_t trgout_enable : 1;
	uint8_t trgin_enable : 1;
};

struct triggerlut {
	/* The actual LUTs. */
	uint16_t m0d[4], m1d[4], m2d[4];
	uint16_t m3, m3s, m4;

	/* Parameters should be sent as a single register write. */
	struct {
		uint8_t selc : 2;
		uint8_t selpresc : 6;

		uint8_t selinc : 2;
		uint8_t selres : 2;
		uint8_t sela : 2;
		uint8_t selb : 2;

		uint16_t cmpb;
		uint16_t cmpa;
	} params;
};

/* Trigger configuration */
struct sigma_trigger {
	/* Only two channels can be used in mask. */
	uint16_t risingmask;
	uint16_t fallingmask;

	/* Simple trigger support (<= 50 MHz). */
	uint16_t simplemask;
	uint16_t simplevalue;

	/* TODO: Advanced trigger support (boolean expressions). */
};

/* Events for trigger operation. */
enum triggerop {
	OP_LEVEL = 1,
	OP_NOT,
	OP_RISE,
	OP_FALL,
	OP_RISEFALL,
	OP_NOTRISE,
	OP_NOTFALL,
	OP_NOTRISEFALL,
};

/* Logical functions for trigger operation. */
enum triggerfunc {
	FUNC_AND = 1,
	FUNC_NAND,
	FUNC_OR,
	FUNC_NOR,
	FUNC_XOR,
	FUNC_NXOR,
};

struct sigma_state {
	enum {
		SIGMA_UNINITIALIZED = 0,
		SIGMA_CONFIG,
		SIGMA_IDLE,
		SIGMA_CAPTURE,
		SIGMA_STOPPING,
		SIGMA_DOWNLOAD,
	} state;
	uint16_t lastts;
	uint16_t lastsample;
};

enum sigma_firmware_idx {
	SIGMA_FW_NONE,
	SIGMA_FW_50MHZ,
	SIGMA_FW_100MHZ,
	SIGMA_FW_200MHZ,
	SIGMA_FW_SYNC,
	SIGMA_FW_FREQ,
};

struct submit_buffer;

struct dev_context {
	struct {
		uint16_t vid, pid;
		uint32_t serno;
		uint16_t prefix;
		enum asix_device_type type;
	} id;
	struct {
		struct ftdi_context ctx;
		gboolean is_open, must_close;
	} ftdi;
	uint64_t samplerate;
	struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
	struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
	struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */
	enum sigma_firmware_idx firmware_idx;
	int num_channels;
	int samples_per_event;
	uint64_t capture_ratio;
	struct sigma_trigger trigger;
	int use_triggers;
	struct sigma_state state;
	struct submit_buffer *buffer;
};

/* "Automatic" and forced USB connection open/close support. */
SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_check_close(struct dev_context *devc);
SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_force_close(struct dev_context *devc);

/* Send register content (simple and complex) to the hardware. */
SR_PRIV int sigma_write_register(struct dev_context *devc,
	uint8_t reg, uint8_t *data, size_t len);
SR_PRIV int sigma_set_register(struct dev_context *devc,
	uint8_t reg, uint8_t value);
SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
	struct triggerlut *lut);

/* Samplerate constraints check, get/set/list helpers. */
SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate);

extern SR_PRIV const uint64_t samplerates[];
extern SR_PRIV const size_t samplerates_count;

/* Preparation of data acquisition, spec conversion, hardware configuration. */
SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc);
SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
	struct triggerlut *lut);

/* Callback to periodically drive acuisition progress. */
SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);

#endif
Commit	Line	Data
204b1629	1	/*
50985c20	2	* This file is part of the libsigrok project.
204b1629	3	*
3ba56876	4	* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
204b1629 UH	5	* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
204b1629 UH	6	* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
9334ed6c	7	* Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
204b1629 UH	8	*
	9	* This program is free software: you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation, either version 3 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
3ba56876	23	#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
	24	#define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H
	25
	26	#include <stdint.h>
4154a516	27	#include <stdlib.h>
3ba56876	28	#include <glib.h>
	29	#include <ftdi.h>
	30	#include <string.h>
	31	#include <libsigrok/libsigrok.h>
	32	#include "libsigrok-internal.h"
28a35d8a	33
f272d7dd UH	34	#define LOG_PREFIX "asix-sigma"
f272d7dd UH	35
de3f7acb GS	36	/*
	37	* Triggers are not working in this implementation. Stop claiming
	38	* support for the feature which effectively is not available, until
	39	* the implementation got fixed. Yet keep the code in place and allow
	40	* developers to turn on this switch during development.
	41	*/
	42	#define ASIX_SIGMA_WITH_TRIGGER 0
	43
53a939ab GS	44	/* Experimental support for OMEGA (scan only, operation is ENOIMPL). */
	45	#define ASIX_WITH_OMEGA 0
	46
	47	#define USB_VENDOR_ASIX 0xa600
	48	#define USB_PRODUCT_SIGMA 0xa000
	49	#define USB_PRODUCT_OMEGA 0xa004
	50
	51	enum asix_device_type {
	52	ASIX_TYPE_NONE,
	53	ASIX_TYPE_SIGMA,
	54	ASIX_TYPE_OMEGA,
	55	};
3ba56876	56
7c41c420 GS	57	/*
	58	* FPGA commands are 8bits wide. The upper nibble is a command opcode,
	59	* the lower nibble can carry operand values. 8bit register addresses
	60	* and 8bit data values get communicated in two steps.
	61	*/
	62
	63	/* Register access. */
	64	#define REG_ADDR_LOW (0x0 << 4)
	65	#define REG_ADDR_HIGH (0x1 << 4)
	66	#define REG_DATA_LOW (0x2 << 4)
	67	#define REG_DATA_HIGH_WRITE (0x3 << 4)
	68	#define REG_READ_ADDR (0x4 << 4)
	69	#define REG_ADDR_ADJUST (1 << 0) /* Auto adjust register address. */
	70	#define REG_ADDR_DOWN (1 << 1) /* 1 decrement, 0 increment. */
	71	#define REG_ADDR_INC (REG_ADDR_ADJUST)
	72	#define REG_ADDR_DEC (REG_ADDR_ADJUST \| REG_ADDR_DOWN)
	73
	74	/* Sample memory access. */
	75	#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */
	76	#define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */
	77	#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */
	78	#define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */
	79	#define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */
	80	#define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0)
	81
	82	/*
	83	* Registers at a specific address can have different meanings depending
	84	* on whether data is read or written. This is why direction is part of
	85	* the programming language identifiers.
	86	*
	87	* The vendor documentation suggests that in addition to the first 16
	88	* register addresses which implement the logic analyzer's feature set,
	89	* there are 240 more registers in the 16 to 255 address range which
	90	* are available to applications and plugin features. Can libsigrok's
	91	* asix-sigma driver store configuration data there, to avoid expensive
	92	* operations (think: firmware re-load).
	93	*/
	94
fefa1800	95	enum sigma_write_register {
28a35d8a	96	WRITE_CLOCK_SELECT = 0,
9fb4c632 GS	97	WRITE_TRIGGER_SELECT = 1,
9fb4c632 GS	98	WRITE_TRIGGER_SELECT2 = 2,
28a35d8a HE	99	WRITE_MODE = 3,
	100	WRITE_MEMROW = 4,
	101	WRITE_POST_TRIGGER = 5,
	102	WRITE_TRIGGER_OPTION = 6,
	103	WRITE_PIN_VIEW = 7,
9fb4c632	104	/* Unassigned register locations. */
fefa1800	105	WRITE_TEST = 15,
28a35d8a HE	106	};
28a35d8a HE	107
fefa1800	108	enum sigma_read_register {
28a35d8a HE	109	READ_ID = 0,
	110	READ_TRIGGER_POS_LOW = 1,
	111	READ_TRIGGER_POS_HIGH = 2,
	112	READ_TRIGGER_POS_UP = 3,
	113	READ_STOP_POS_LOW = 4,
	114	READ_STOP_POS_HIGH = 5,
	115	READ_STOP_POS_UP = 6,
	116	READ_MODE = 7,
	117	READ_PIN_CHANGE_LOW = 8,
	118	READ_PIN_CHANGE_HIGH = 9,
	119	READ_BLOCK_LAST_TS_LOW = 10,
	120	READ_BLOCK_LAST_TS_HIGH = 11,
9fb4c632 GS	121	READ_BLOCK_TS_OVERRUN = 12,
	122	READ_PIN_VIEW = 13,
	123	/* Unassigned register location. */
fefa1800	124	READ_TEST = 15,
28a35d8a HE	125	};
28a35d8a HE	126
a53b8e4d GS	127	#define TRGSEL2_LEDSEL0 (1 << 6)
a53b8e4d GS	128	#define TRGSEL2_LEDSEL1 (1 << 7)
57bbf56b	129
22f64ed8 GS	130	/* WRITE_MODE register fields. */
	131	#define WMR_SDRAMWRITEEN (1 << 0)
	132	#define WMR_SDRAMREADEN (1 << 1)
	133	#define WMR_TRGRES (1 << 2)
	134	#define WMR_TRGEN (1 << 3)
	135	#define WMR_FORCESTOP (1 << 4)
	136	#define WMR_TRGSW (1 << 5)
	137	/* not used: bit position 6 */
	138	#define WMR_SDRAMINIT (1 << 7)
	139
	140	/* READ_MODE register fields. */
	141	#define RMR_SDRAMWRITEEN (1 << 0)
	142	#define RMR_SDRAMREADEN (1 << 1)
	143	/* not used: bit position 2 */
	144	#define RMR_TRGEN (1 << 3)
	145	#define RMR_ROUND (1 << 4)
	146	#define RMR_TRIGGERED (1 << 5)
	147	#define RMR_POSTTRIGGERED (1 << 6)
	148	/* not used: bit position 7 */
	149
a53b8e4d GS	150	/*
	151	* Trigger options. First and second write are similar, but _some_
	152	* positions change their meaning.
	153	*/
	154	#define TRGOPT_TRGIEN (1 << 7)
	155	#define TRGOPT_TRGOEN (1 << 6)
	156	#define TRGOPT_TRGOINEN (1 << 5) /* 1st write */
	157	#define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */
	158	#define TRGOPT_TRGOEVNTEN (1 << 4) /* 1st write */
	159	#define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */
	160	#define TRGOPT_TRGOOUTEN (1 << 3) /* 1st write */
	161	#define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */
	162	#define TRGOPT_TRGOUTR_OUT (1 << 1)
	163	#define TRGOPT_TRGOUTR_EN (1 << 0)
	164	#define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN \| TRGOPT_TRGOEVNTEN \| TRGOPT_TRGOOUTEN)
	165
fd830beb	166	/*
5b1d15ef GS	167	* Layout of the sample data DRAM, which will be downloaded to the PC:
	168	*
	169	* Sigma memory is organized in 32K rows. Each row contains 64 clusters.
2c33b092 GS	170	* Each cluster contains a timestamp (16bit) and 7 events (16bits each).
	171	* Events contain 16 bits of sample data (potentially taken at multiple
	172	* sample points, see below).
	173	*
	174	* Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The
	175	* size of a memory row is 1024 bytes. Assuming x16 organization of the
	176	* memory array, address specs (sample count, trigger position) are kept
	177	* in 24bit entities. The upper 15 bit address the "row", the lower 9 bit
	178	* refer to the "event" within the row. Because there is one timestamp for
	179	* seven events each, one memory row can hold up to 64x7 == 448 events.
5b1d15ef GS	180	*
	181	* Sample data is represented in 16bit quantities. The first sample in
	182	* the cluster corresponds to the cluster's timestamp. Each next sample
	183	* corresponds to the timestamp + 1, timestamp + 2, etc (the distance is
	184	* one sample period, according to the samplerate). In the absence of
	185	* pin level changes, no data is provided (RLE compression). A cluster
	186	* is enforced for each 64K ticks of the timestamp, to reliably handle
2c33b092	187	* rollover and determine the next timestamp of the next cluster.
5b1d15ef	188	*
2c33b092 GS	189	* For samplerates up to 50MHz, an event directly translates to one set
2c33b092 GS	190	* of sample data at a single sample point, spanning up to 16 channels.
5b1d15ef GS	191	* For samplerates of 100MHz, there is one 16 bit entity for each 20ns
	192	* period (50MHz rate). The 16 bit memory contains 2 samples of up to
	193	* 8 channels. Bits of multiple samples are interleaved. For samplerates
	194	* of 200MHz one 16bit entity contains 4 samples of up to 4 channels,
	195	* each 5ns apart.
fd830beb MV	196	*/
fd830beb MV	197
2c33b092 GS	198	#define ROW_COUNT 32768
	199	#define ROW_LENGTH_BYTES 1024
	200	#define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t))
	201	#define ROW_SHIFT 9 /* log2 of u16 count */
	202	#define ROW_MASK ((1UL << ROW_SHIFT) - 1)
	203	#define EVENTS_PER_CLUSTER 7
	204	#define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER))
	205	#define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER)
fd830beb	206
fd830beb	207	struct sigma_dram_line {
2c33b092	208	struct sigma_dram_cluster {
2a62a9c4 GS	209	uint16_t timestamp;
2a62a9c4 GS	210	uint16_t samples[EVENTS_PER_CLUSTER];
2c33b092	211	} cluster[CLUSTERS_PER_ROW];
fd830beb MV	212	};
fd830beb MV	213
edca2c5c HE	214	struct clockselect_50 {
edca2c5c HE	215	uint8_t async;
a53b8e4d	216	uint64_t fraction;
ba7dd8bb	217	uint16_t disabled_channels;
edca2c5c HE	218	};
edca2c5c HE	219
57bbf56b HE	220	/* The effect of all these are still a bit unclear. */
	221	struct triggerinout {
	222	uint8_t trgout_resistor_enable : 1;
	223	uint8_t trgout_resistor_pullup : 1;
	224	uint8_t reserved1 : 1;
	225	uint8_t trgout_bytrigger : 1;
	226	uint8_t trgout_byevent : 1;
	227	uint8_t trgout_bytriggerin : 1;
	228	uint8_t reserved2 : 2;
	229
	230	/* Should be set same as the first two */
	231	uint8_t trgout_resistor_enable2 : 1;
	232	uint8_t trgout_resistor_pullup2 : 1;
	233
	234	uint8_t reserved3 : 1;
	235	uint8_t trgout_long : 1;
	236	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	237	uint8_t trgin_negate : 1;
	238	uint8_t trgout_enable : 1;
	239	uint8_t trgin_enable : 1;
	240	};
	241
ee492173 HE	242	struct triggerlut {
	243	/* The actual LUTs. */
	244	uint16_t m0d[4], m1d[4], m2d[4];
	245	uint16_t m3, m3s, m4;
	246
f3f19d11	247	/* Parameters should be sent as a single register write. */
ee492173 HE	248	struct {
	249	uint8_t selc : 2;
	250	uint8_t selpresc : 6;
	251
	252	uint8_t selinc : 2;
	253	uint8_t selres : 2;
	254	uint8_t sela : 2;
	255	uint8_t selb : 2;
	256
	257	uint16_t cmpb;
	258	uint16_t cmpa;
	259	} params;
	260	};
	261
c53d793f HE	262	/* Trigger configuration */
c53d793f HE	263	struct sigma_trigger {
ba7dd8bb	264	/* Only two channels can be used in mask. */
a42aec7f HE	265	uint16_t risingmask;
a42aec7f HE	266	uint16_t fallingmask;
c53d793f HE	267
	268	/* Simple trigger support (<= 50 MHz). */
	269	uint16_t simplemask;
	270	uint16_t simplevalue;
	271
c53d793f HE	272	/* TODO: Advanced trigger support (boolean expressions). */
	273	};
	274
	275	/* Events for trigger operation. */
	276	enum triggerop {
	277	OP_LEVEL = 1,
	278	OP_NOT,
	279	OP_RISE,
	280	OP_FALL,
	281	OP_RISEFALL,
	282	OP_NOTRISE,
	283	OP_NOTFALL,
	284	OP_NOTRISEFALL,
	285	};
	286
	287	/* Logical functions for trigger operation. */
	288	enum triggerfunc {
	289	FUNC_AND = 1,
	290	FUNC_NAND,
	291	FUNC_OR,
	292	FUNC_NOR,
	293	FUNC_XOR,
	294	FUNC_NXOR,
	295	};
	296
6aac7737 HE	297	struct sigma_state {
	298	enum {
	299	SIGMA_UNINITIALIZED = 0,
1bb9dc82	300	SIGMA_CONFIG,
6aac7737 HE	301	SIGMA_IDLE,
6aac7737 HE	302	SIGMA_CAPTURE,
dde0175d	303	SIGMA_STOPPING,
6aac7737 HE	304	SIGMA_DOWNLOAD,
6aac7737 HE	305	} state;
6aac7737 HE	306	uint16_t lastts;
6aac7737 HE	307	uint16_t lastsample;
6aac7737 HE	308	};
6aac7737 HE	309
80e717b3 GS	310	enum sigma_firmware_idx {
	311	SIGMA_FW_NONE,
	312	SIGMA_FW_50MHZ,
	313	SIGMA_FW_100MHZ,
	314	SIGMA_FW_200MHZ,
	315	SIGMA_FW_SYNC,
	316	SIGMA_FW_FREQ,
	317	};
	318
98b43eb3 GS	319	struct submit_buffer;
98b43eb3 GS	320
0e1357e8	321	struct dev_context {
53a939ab GS	322	struct {
	323	uint16_t vid, pid;
	324	uint32_t serno;
	325	uint16_t prefix;
	326	enum asix_device_type type;
	327	} id;
7fe1f91f GS	328	struct {
	329	struct ftdi_context ctx;
	330	gboolean is_open, must_close;
	331	} ftdi;
5e78a564 GS	332	uint64_t samplerate;
	333	struct sr_sw_limits cfg_limits; /* Configured limits (user specified). */
	334	struct sr_sw_limits acq_limits; /* Acquisition limits (internal use). */
	335	struct sr_sw_limits feed_limits; /* Datafeed limits (internal use). */
80e717b3	336	enum sigma_firmware_idx firmware_idx;
ba7dd8bb	337	int num_channels;
99965709	338	int samples_per_event;
efad7ccc	339	uint64_t capture_ratio;
99965709	340	struct sigma_trigger trigger;
5b5ea7c6	341	int use_triggers;
99965709	342	struct sigma_state state;
98b43eb3	343	struct submit_buffer *buffer;
99965709 HE	344	};
99965709 HE	345
7fe1f91f GS	346	/* "Automatic" and forced USB connection open/close support. */
	347	SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi);
	348	SR_PRIV int sigma_check_close(struct dev_context *devc);
	349	SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi);
	350	SR_PRIV int sigma_force_close(struct dev_context *devc);
	351
a426f74a	352	/* Send register content (simple and complex) to the hardware. */
9b4d261f GS	353	SR_PRIV int sigma_write_register(struct dev_context *devc,
	354	uint8_t reg, uint8_t *data, size_t len);
	355	SR_PRIV int sigma_set_register(struct dev_context *devc,
	356	uint8_t reg, uint8_t value);
	357	SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
	358	struct triggerlut *lut);
a426f74a GS	359
a426f74a GS	360	/* Samplerate constraints check, get/set/list helpers. */
5e78a564	361	SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate);
a426f74a GS	362
	363	extern SR_PRIV const uint64_t samplerates[];
	364	extern SR_PRIV const size_t samplerates_count;
	365
	366	/* Preparation of data acquisition, spec conversion, hardware configuration. */
5e78a564 GS	367	SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi);
5e78a564 GS	368	SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc);
3ba56876	369	SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi);
9b4d261f GS	370	SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
9b4d261f GS	371	struct triggerlut *lut);
3ba56876	372
a426f74a GS	373	/* Callback to periodically drive acuisition progress. */
	374	SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data);
	375
204b1629	376	#endif