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f44d2db2 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
f44d2db2 | 3 | ## |
0bb7bcf3 | 4 | ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
f44d2db2 UH |
18 | ## |
19 | ||
677d597b | 20 | import sigrokdecode as srd |
b5712ccb | 21 | from math import floor, ceil |
f44d2db2 | 22 | |
4cace3b8 | 23 | ''' |
c515eed7 | 24 | OUTPUT_PYTHON format: |
4cace3b8 | 25 | |
bf69977d UH |
26 | Packet: |
27 | [<ptype>, <rxtx>, <pdata>] | |
4cace3b8 | 28 | |
bf69977d | 29 | This is the list of <ptype>s and their respective <pdata> values: |
4cace3b8 | 30 | - 'STARTBIT': The data is the (integer) value of the start bit (0/1). |
0c7d5a56 UH |
31 | - 'DATA': This is always a tuple containing two items: |
32 | - 1st item: the (integer) value of the UART data. Valid values | |
6ffd71c1 | 33 | range from 0 to 511 (as the data can be up to 9 bits in size). |
0c7d5a56 | 34 | - 2nd item: the list of individual data bits and their ss/es numbers. |
4cace3b8 UH |
35 | - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). |
36 | - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
37 | - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). | |
38 | - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). | |
39 | - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
40 | the expected parity value, the second is the actual parity value. | |
41 | - TODO: Frame error? | |
42 | ||
43 | The <rxtx> field is 0 for RX packets, 1 for TX packets. | |
44 | ''' | |
45 | ||
97cca21f UH |
46 | # Used for differentiating between the two data directions. |
47 | RX = 0 | |
48 | TX = 1 | |
49 | ||
f44d2db2 UH |
50 | # Given a parity type to check (odd, even, zero, one), the value of the |
51 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
52 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
a7fc4c34 | 53 | # 'none' is _not_ allowed as value for 'parity_type'. |
f44d2db2 UH |
54 | def parity_ok(parity_type, parity_bit, data, num_data_bits): |
55 | ||
56 | # Handle easy cases first (parity bit is always 1 or 0). | |
a7fc4c34 | 57 | if parity_type == 'zero': |
f44d2db2 | 58 | return parity_bit == 0 |
a7fc4c34 | 59 | elif parity_type == 'one': |
f44d2db2 UH |
60 | return parity_bit == 1 |
61 | ||
62 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
ac941bf9 | 63 | ones = bin(data).count('1') + parity_bit |
f44d2db2 UH |
64 | |
65 | # Check for odd/even parity. | |
a7fc4c34 | 66 | if parity_type == 'odd': |
ac941bf9 | 67 | return (ones % 2) == 1 |
a7fc4c34 | 68 | elif parity_type == 'even': |
ac941bf9 | 69 | return (ones % 2) == 0 |
f44d2db2 | 70 | |
21cda951 UH |
71 | class SamplerateError(Exception): |
72 | pass | |
73 | ||
f04964c6 UH |
74 | class ChannelError(Exception): |
75 | pass | |
76 | ||
677d597b | 77 | class Decoder(srd.Decoder): |
12851357 | 78 | api_version = 2 |
f44d2db2 UH |
79 | id = 'uart' |
80 | name = 'UART' | |
3d3da57d | 81 | longname = 'Universal Asynchronous Receiver/Transmitter' |
a465436e | 82 | desc = 'Asynchronous, serial bus.' |
f44d2db2 UH |
83 | license = 'gplv2+' |
84 | inputs = ['logic'] | |
85 | outputs = ['uart'] | |
6a15597a | 86 | optional_channels = ( |
f44d2db2 UH |
87 | # Allow specifying only one of the signals, e.g. if only one data |
88 | # direction exists (or is relevant). | |
29ed0f4c UH |
89 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
90 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
da9bcbd9 | 91 | ) |
84c1c0b5 BV |
92 | options = ( |
93 | {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, | |
94 | {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, | |
95 | 'values': (5, 6, 7, 8, 9)}, | |
96 | {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', | |
97 | 'values': ('none', 'odd', 'even', 'zero', 'one')}, | |
98 | {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', | |
99 | 'values': ('yes', 'no')}, | |
100 | {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, | |
101 | 'values': (0.0, 0.5, 1.0, 1.5)}, | |
102 | {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', | |
103 | 'values': ('lsb-first', 'msb-first')}, | |
ea36c198 | 104 | {'id': 'format', 'desc': 'Data format', 'default': 'hex', |
84c1c0b5 | 105 | 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, |
4eafeeef DB |
106 | {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no', |
107 | 'values': ('yes', 'no')}, | |
108 | {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', | |
109 | 'values': ('yes', 'no')}, | |
84c1c0b5 | 110 | ) |
da9bcbd9 BV |
111 | annotations = ( |
112 | ('rx-data', 'RX data'), | |
113 | ('tx-data', 'TX data'), | |
114 | ('rx-start', 'RX start bits'), | |
115 | ('tx-start', 'TX start bits'), | |
116 | ('rx-parity-ok', 'RX parity OK bits'), | |
117 | ('tx-parity-ok', 'TX parity OK bits'), | |
118 | ('rx-parity-err', 'RX parity error bits'), | |
119 | ('tx-parity-err', 'TX parity error bits'), | |
120 | ('rx-stop', 'RX stop bits'), | |
121 | ('tx-stop', 'TX stop bits'), | |
122 | ('rx-warnings', 'RX warnings'), | |
123 | ('tx-warnings', 'TX warnings'), | |
124 | ('rx-data-bits', 'RX data bits'), | |
125 | ('tx-data-bits', 'TX data bits'), | |
126 | ) | |
2ce20a91 | 127 | annotation_rows = ( |
4e3b276a | 128 | ('rx-data', 'RX', (0, 2, 4, 6, 8)), |
4aedd5b8 | 129 | ('rx-data-bits', 'RX bits', (12,)), |
4e3b276a | 130 | ('rx-warnings', 'RX warnings', (10,)), |
4aedd5b8 UH |
131 | ('tx-data', 'TX', (1, 3, 5, 7, 9)), |
132 | ('tx-data-bits', 'TX bits', (13,)), | |
4e3b276a | 133 | ('tx-warnings', 'TX warnings', (11,)), |
2ce20a91 | 134 | ) |
0bb7bcf3 UH |
135 | binary = ( |
136 | ('rx', 'RX dump'), | |
137 | ('tx', 'TX dump'), | |
138 | ('rxtx', 'RX/TX dump'), | |
139 | ) | |
96a044da | 140 | idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] |
f44d2db2 | 141 | |
97cca21f | 142 | def putx(self, rxtx, data): |
b5712ccb PA |
143 | s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 |
144 | self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data) | |
15ac6604 | 145 | |
4aedd5b8 | 146 | def putpx(self, rxtx, data): |
b5712ccb PA |
147 | s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 |
148 | self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data) | |
4aedd5b8 | 149 | |
15ac6604 | 150 | def putg(self, data): |
b5712ccb PA |
151 | s, halfbit = self.samplenum, self.bit_width / 2.0 |
152 | self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data) | |
15ac6604 UH |
153 | |
154 | def putp(self, data): | |
b5712ccb PA |
155 | s, halfbit = self.samplenum, self.bit_width / 2.0 |
156 | self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) | |
97cca21f | 157 | |
0bb7bcf3 | 158 | def putbin(self, rxtx, data): |
b5712ccb | 159 | s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 |
2f370328 | 160 | self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) |
0bb7bcf3 | 161 | |
92b7b49f | 162 | def __init__(self): |
f372d597 | 163 | self.samplerate = None |
f44d2db2 | 164 | self.samplenum = 0 |
97cca21f UH |
165 | self.frame_start = [-1, -1] |
166 | self.startbit = [-1, -1] | |
167 | self.cur_data_bit = [0, 0] | |
e9a3c933 | 168 | self.datavalue = [0, 0] |
1ccef461 | 169 | self.paritybit = [-1, -1] |
97cca21f UH |
170 | self.stopbit1 = [-1, -1] |
171 | self.startsample = [-1, -1] | |
2b716038 | 172 | self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] |
83be7b83 | 173 | self.oldbit = [1, 1] |
96a044da | 174 | self.oldpins = [-1, -1] |
4aedd5b8 | 175 | self.databits = [[], []] |
f44d2db2 | 176 | |
f372d597 | 177 | def start(self): |
c515eed7 | 178 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
2f370328 | 179 | self.out_binary = self.register(srd.OUTPUT_BINARY) |
be465111 | 180 | self.out_ann = self.register(srd.OUTPUT_ANN) |
98b89139 | 181 | self.bw = (self.options['num_data_bits'] + 7) // 8 |
f44d2db2 | 182 | |
f372d597 BV |
183 | def metadata(self, key, value): |
184 | if key == srd.SRD_CONF_SAMPLERATE: | |
35b380b1 | 185 | self.samplerate = value |
f372d597 BV |
186 | # The width of one UART bit in number of samples. |
187 | self.bit_width = float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 | 188 | |
f44d2db2 | 189 | # Return true if we reached the middle of the desired bit, false otherwise. |
97cca21f | 190 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
191 | # bitpos is the samplenumber which is in the middle of the |
192 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
193 | # (if used) or the first stop bit, and so on). | |
b5712ccb PA |
194 | # The samples within bit are 0, 1, ..., (bit_width - 1), therefore |
195 | # index of the middle sample within bit window is (bit_width - 1) / 2. | |
196 | bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0 | |
f44d2db2 UH |
197 | bitpos += bitnum * self.bit_width |
198 | if self.samplenum >= bitpos: | |
199 | return True | |
200 | return False | |
201 | ||
97cca21f UH |
202 | def reached_bit_last(self, rxtx, bitnum): |
203 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
204 | if self.samplenum >= bitpos: |
205 | return True | |
206 | return False | |
207 | ||
97cca21f | 208 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
209 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
210 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
211 | if not (old_signal == 1 and signal == 0): | |
212 | return | |
213 | ||
214 | # Save the sample number where the start bit begins. | |
97cca21f | 215 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 216 | |
2b716038 | 217 | self.state[rxtx] = 'GET START BIT' |
f44d2db2 | 218 | |
97cca21f | 219 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 220 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 221 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 222 | return |
f44d2db2 | 223 | |
97cca21f | 224 | self.startbit[rxtx] = signal |
f44d2db2 | 225 | |
711d0602 GS |
226 | # The startbit must be 0. If not, we report an error and wait |
227 | # for the next start bit (assuming this one was spurious). | |
97cca21f | 228 | if self.startbit[rxtx] != 0: |
15ac6604 | 229 | self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) |
76a4498f | 230 | self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) |
711d0602 GS |
231 | self.state[rxtx] = 'WAIT FOR START BIT' |
232 | return | |
f44d2db2 | 233 | |
97cca21f | 234 | self.cur_data_bit[rxtx] = 0 |
e9a3c933 | 235 | self.datavalue[rxtx] = 0 |
97cca21f | 236 | self.startsample[rxtx] = -1 |
f44d2db2 | 237 | |
2b716038 | 238 | self.state[rxtx] = 'GET DATA BITS' |
f44d2db2 | 239 | |
15ac6604 | 240 | self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) |
2ce20a91 | 241 | self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 242 | |
97cca21f | 243 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 244 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 245 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 246 | return |
f44d2db2 | 247 | |
15ac6604 | 248 | # Save the sample number of the middle of the first data bit. |
97cca21f UH |
249 | if self.startsample[rxtx] == -1: |
250 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
251 | |
252 | # Get the next data bit in LSB-first or MSB-first fashion. | |
a7fc4c34 | 253 | if self.options['bit_order'] == 'lsb-first': |
e9a3c933 GS |
254 | self.datavalue[rxtx] >>= 1 |
255 | self.datavalue[rxtx] |= \ | |
fd4aa8aa | 256 | (signal << (self.options['num_data_bits'] - 1)) |
22fc7ace | 257 | else: |
e9a3c933 GS |
258 | self.datavalue[rxtx] <<= 1 |
259 | self.datavalue[rxtx] |= (signal << 0) | |
f44d2db2 | 260 | |
4aedd5b8 UH |
261 | self.putg([rxtx + 12, ['%d' % signal]]) |
262 | ||
263 | # Store individual data bits and their start/end samplenumbers. | |
264 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
265 | self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) | |
266 | ||
f44d2db2 | 267 | # Return here, unless we already received all data bits. |
4a04ece4 | 268 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: |
97cca21f | 269 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 270 | return |
f44d2db2 | 271 | |
2b716038 | 272 | self.state[rxtx] = 'GET PARITY BIT' |
f44d2db2 | 273 | |
7cf698c5 | 274 | self.putpx(rxtx, ['DATA', rxtx, |
e9a3c933 | 275 | (self.datavalue[rxtx], self.databits[rxtx])]) |
f44d2db2 | 276 | |
6ffd71c1 GS |
277 | b = self.datavalue[rxtx] |
278 | formatted = self.format_value(b) | |
279 | if formatted is not None: | |
280 | self.putx(rxtx, [rxtx, [formatted]]) | |
f44d2db2 | 281 | |
98b89139 UH |
282 | bdata = b.to_bytes(self.bw, byteorder='big') |
283 | self.putbin(rxtx, [rxtx, bdata]) | |
284 | self.putbin(rxtx, [2, bdata]) | |
0bb7bcf3 | 285 | |
c1fc50b1 | 286 | self.databits[rxtx] = [] |
4aedd5b8 | 287 | |
6ffd71c1 GS |
288 | def format_value(self, v): |
289 | # Format value 'v' according to configured options. | |
290 | # Reflects the user selected kind of representation, as well as | |
291 | # the number of data bits in the UART frames. | |
292 | ||
293 | fmt, bits = self.options['format'], self.options['num_data_bits'] | |
294 | ||
295 | # Assume "is printable" for values from 32 to including 126, | |
296 | # below 32 is "control" and thus not printable, above 127 is | |
297 | # "not ASCII" in its strict sense, 127 (DEL) is not printable, | |
298 | # fall back to hex representation for non-printables. | |
299 | if fmt == 'ascii': | |
300 | if v in range(32, 126 + 1): | |
301 | return chr(v) | |
302 | hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]" | |
303 | return hexfmt.format(v) | |
304 | ||
305 | # Mere number to text conversion without prefix and padding | |
306 | # for the "decimal" output format. | |
307 | if fmt == 'dec': | |
308 | return "{:d}".format(v) | |
309 | ||
310 | # Padding with leading zeroes for hex/oct/bin formats, but | |
311 | # without a prefix for density -- since the format is user | |
312 | # specified, there is no ambiguity. | |
313 | if fmt == 'hex': | |
314 | digits = (bits + 4 - 1) // 4 | |
315 | fmtchar = "X" | |
316 | elif fmt == 'oct': | |
317 | digits = (bits + 3 - 1) // 3 | |
318 | fmtchar = "o" | |
319 | elif fmt == 'bin': | |
320 | digits = bits | |
321 | fmtchar = "b" | |
322 | else: | |
323 | fmtchar = None | |
324 | if fmtchar is not None: | |
325 | fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar) | |
326 | return fmt.format(v) | |
327 | ||
328 | return None | |
329 | ||
97cca21f | 330 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 331 | # If no parity is used/configured, skip to the next state immediately. |
a7fc4c34 | 332 | if self.options['parity_type'] == 'none': |
2b716038 | 333 | self.state[rxtx] = 'GET STOP BITS' |
1bb57ab8 | 334 | return |
f44d2db2 UH |
335 | |
336 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 337 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 338 | return |
f44d2db2 | 339 | |
97cca21f | 340 | self.paritybit[rxtx] = signal |
f44d2db2 | 341 | |
2b716038 | 342 | self.state[rxtx] = 'GET STOP BITS' |
f44d2db2 | 343 | |
ac941bf9 | 344 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], |
e9a3c933 | 345 | self.datavalue[rxtx], self.options['num_data_bits']): |
15ac6604 | 346 | self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) |
2ce20a91 | 347 | self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 348 | else: |
61132abd | 349 | # TODO: Return expected/actual parity values. |
15ac6604 | 350 | self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... |
4e3b276a | 351 | self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
352 | |
353 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 354 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 355 | # Skip samples until we're in the middle of the stop bit(s). |
a7fc4c34 | 356 | skip_parity = 0 if self.options['parity_type'] == 'none' else 1 |
4a04ece4 UH |
357 | b = self.options['num_data_bits'] + 1 + skip_parity |
358 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 359 | return |
f44d2db2 | 360 | |
97cca21f | 361 | self.stopbit1[rxtx] = signal |
f44d2db2 | 362 | |
5cc4b6a0 | 363 | # Stop bits must be 1. If not, we report an error. |
97cca21f | 364 | if self.stopbit1[rxtx] != 1: |
15ac6604 | 365 | self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) |
76a4498f | 366 | self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) |
5cc4b6a0 | 367 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 368 | |
2b716038 | 369 | self.state[rxtx] = 'WAIT FOR START BIT' |
f44d2db2 | 370 | |
15ac6604 | 371 | self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) |
2ce20a91 | 372 | self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) |
f44d2db2 | 373 | |
decde15e | 374 | def decode(self, ss, es, data): |
21cda951 UH |
375 | if not self.samplerate: |
376 | raise SamplerateError('Cannot decode without samplerate.') | |
2fcd7c22 UH |
377 | for (self.samplenum, pins) in data: |
378 | ||
96a044da DT |
379 | # We want to skip identical samples for performance reasons but, |
380 | # for now, we can only do that when we are in the idle state | |
381 | # (meaning both channels are waiting for the start bit). | |
382 | if self.state == self.idle_state and self.oldpins == pins: | |
383 | continue | |
384 | ||
2fcd7c22 | 385 | self.oldpins, (rx, tx) = pins, pins |
f44d2db2 | 386 | |
4eafeeef DB |
387 | if self.options['invert_rx'] == 'yes': |
388 | rx = not rx | |
389 | if self.options['invert_tx'] == 'yes': | |
390 | tx = not tx | |
391 | ||
3dd546c1 UH |
392 | # Either RX or TX (but not both) can be omitted. |
393 | has_pin = [rx in (0, 1), tx in (0, 1)] | |
394 | if has_pin == [False, False]: | |
f04964c6 | 395 | raise ChannelError('Either TX or RX (or both) pins required.') |
3dd546c1 | 396 | |
f44d2db2 | 397 | # State machine. |
97cca21f | 398 | for rxtx in (RX, TX): |
3dd546c1 UH |
399 | # Don't try to handle RX (or TX) if not supplied. |
400 | if not has_pin[rxtx]: | |
401 | continue | |
402 | ||
97cca21f UH |
403 | signal = rx if (rxtx == RX) else tx |
404 | ||
2b716038 | 405 | if self.state[rxtx] == 'WAIT FOR START BIT': |
97cca21f | 406 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) |
2b716038 | 407 | elif self.state[rxtx] == 'GET START BIT': |
97cca21f | 408 | self.get_start_bit(rxtx, signal) |
2b716038 | 409 | elif self.state[rxtx] == 'GET DATA BITS': |
97cca21f | 410 | self.get_data_bits(rxtx, signal) |
2b716038 | 411 | elif self.state[rxtx] == 'GET PARITY BIT': |
97cca21f | 412 | self.get_parity_bit(rxtx, signal) |
2b716038 | 413 | elif self.state[rxtx] == 'GET STOP BITS': |
97cca21f | 414 | self.get_stop_bits(rxtx, signal) |
97cca21f UH |
415 | |
416 | # Save current RX/TX values for the next round. | |
417 | self.oldbit[rxtx] = signal |