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f44d2db2 UH |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4a04ece4 | 4 | ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # | |
22 | # UART protocol decoder | |
23 | # | |
24 | ||
6efe1e11 UH |
25 | # |
26 | # Universal Asynchronous Receiver Transmitter (UART) is a simple serial | |
27 | # communication protocol which allows two devices to talk to each other. | |
28 | # | |
29 | # It uses just two data signals and a ground (GND) signal: | |
30 | # - RX/RXD: Receive signal | |
31 | # - TX/TXD: Transmit signal | |
32 | # | |
33 | # The protocol is asynchronous, i.e., there is no dedicated clock signal. | |
34 | # Rather, both devices have to agree on a baudrate (number of bits to be | |
35 | # transmitted per second) beforehand. Baudrates can be arbitrary in theory, | |
36 | # but usually the choice is limited by the hardware UARTs that are used. | |
37 | # Common values are 9600 or 115200. | |
38 | # | |
39 | # The protocol allows full-duplex transmission, i.e. both devices can send | |
40 | # data at the same time. However, unlike SPI (which is always full-duplex, | |
41 | # i.e., each send operation is automatically also a receive operation), UART | |
42 | # allows one-way communication, too. In such a case only one signal (and GND) | |
43 | # is required. | |
44 | # | |
45 | # The data is sent over the TX line in so-called 'frames', which consist of: | |
46 | # - Exactly one start bit (always 0/low). | |
47 | # - Between 5 and 9 data bits. | |
48 | # - An (optional) parity bit. | |
49 | # - One or more stop bit(s). | |
50 | # | |
51 | # The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the | |
52 | # receiver can continually monitor its RX line for a falling edge, in order | |
53 | # to detect the start bit. | |
54 | # | |
55 | # Once detected, it can (due to the agreed-upon baudrate and thus the known | |
56 | # width/duration of one UART bit) sample the state of the RX line "in the | |
57 | # middle" of each (start/data/parity/stop) bit it wants to analyze. | |
58 | # | |
59 | # It is configurable whether there is a parity bit in a frame, and if yes, | |
60 | # which type of parity is used: | |
61 | # - None: No parity bit is included. | |
62 | # - Odd: The number of 1 bits in the data (and parity bit itself) is odd. | |
63 | # - Even: The number of 1 bits in the data (and parity bit itself) is even. | |
64 | # - Mark/one: The parity bit is always 1/high (also called 'mark state'). | |
65 | # - Space/zero: The parity bit is always 0/low (also called 'space state'). | |
66 | # | |
67 | # It is also configurable how many stop bits are to be used: | |
68 | # - 1 stop bit (most common case) | |
69 | # - 2 stop bits | |
70 | # - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width) | |
71 | # - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width) | |
72 | # | |
73 | # The bit order of the 5-9 data bits is LSB-first. | |
74 | # | |
75 | # Possible special cases: | |
76 | # - One or both data lines could be inverted, which also means that the idle | |
77 | # state of the signal line(s) is low instead of high. | |
78 | # - Only the data bits on one or both data lines (and the parity bit) could | |
79 | # be inverted (but the start/stop bits remain non-inverted). | |
80 | # - The bit order could be MSB-first instead of LSB-first. | |
81 | # - The baudrate could change in the middle of the communication. This only | |
82 | # happens in very special cases, and can only work if both devices know | |
83 | # to which baudrate they are to switch, and when. | |
84 | # - Theoretically, the baudrate on RX and the one on TX could also be | |
85 | # different, but that's a very obscure case and probably doesn't happen | |
86 | # very often in practice. | |
87 | # | |
88 | # Error conditions: | |
89 | # - If there is a parity bit, but it doesn't match the expected parity, | |
90 | # this is called a 'parity error'. | |
91 | # - If there are no stop bit(s), that's called a 'frame error'. | |
92 | # | |
93 | # More information: | |
94 | # TODO: URLs | |
95 | # | |
96 | ||
61132abd UH |
97 | # |
98 | # Protocol output format: | |
61132abd | 99 | # |
97cca21f UH |
100 | # UART packet: |
101 | # [<packet-type>, <rxtx>, <packet-data>] | |
61132abd | 102 | # |
97cca21f | 103 | # This is the list of <packet-types>s and their respective <packet-data>: |
b9e44d1e UH |
104 | # - 'STARTBIT': The data is the (integer) value of the start bit (0 or 1). |
105 | # - 'DATA': The data is the (integer) value of the UART data. Valid values | |
61132abd | 106 | # range from 0 to 512 (as the data can be up to 9 bits in size). |
b9e44d1e UH |
107 | # - 'PARITYBIT': The data is the (integer) value of the parity bit (0 or 1). |
108 | # - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
109 | # - 'INVALID STARTBIT': The data is the (integer) value of the start bit | |
110 | # (0 or 1). | |
111 | # - 'INVALID STOPBIT': The data is the (integer) value of the stop bit | |
112 | # (0 or 1). | |
113 | # - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
61132abd | 114 | # the expected parity value, the second is the actual parity value. |
b9e44d1e | 115 | # - TODO: Frame error? |
61132abd | 116 | # |
97cca21f | 117 | # The <rxtx> field is 0 for RX packets, 1 for TX packets. |
61132abd UH |
118 | # |
119 | ||
677d597b | 120 | import sigrokdecode as srd |
f44d2db2 UH |
121 | |
122 | # States | |
123 | WAIT_FOR_START_BIT = 0 | |
124 | GET_START_BIT = 1 | |
125 | GET_DATA_BITS = 2 | |
126 | GET_PARITY_BIT = 3 | |
127 | GET_STOP_BITS = 4 | |
128 | ||
97cca21f UH |
129 | # Used for differentiating between the two data directions. |
130 | RX = 0 | |
131 | TX = 1 | |
132 | ||
f44d2db2 UH |
133 | # Parity options |
134 | PARITY_NONE = 0 | |
135 | PARITY_ODD = 1 | |
136 | PARITY_EVEN = 2 | |
137 | PARITY_ZERO = 3 | |
138 | PARITY_ONE = 4 | |
139 | ||
140 | # Stop bit options | |
141 | STOP_BITS_0_5 = 0 | |
142 | STOP_BITS_1 = 1 | |
143 | STOP_BITS_1_5 = 2 | |
144 | STOP_BITS_2 = 3 | |
145 | ||
146 | # Bit order options | |
147 | LSB_FIRST = 0 | |
148 | MSB_FIRST = 1 | |
149 | ||
1bb57ab8 UH |
150 | # Annotation feed formats |
151 | ANN_ASCII = 0 | |
152 | ANN_DEC = 1 | |
153 | ANN_HEX = 2 | |
154 | ANN_OCT = 3 | |
155 | ANN_BITS = 4 | |
f44d2db2 | 156 | |
f44d2db2 UH |
157 | # Given a parity type to check (odd, even, zero, one), the value of the |
158 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
159 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
160 | # PARITY_NONE is _not_ allowed as value for 'parity_type'. | |
161 | def parity_ok(parity_type, parity_bit, data, num_data_bits): | |
162 | ||
163 | # Handle easy cases first (parity bit is always 1 or 0). | |
164 | if parity_type == PARITY_ZERO: | |
165 | return parity_bit == 0 | |
166 | elif parity_type == PARITY_ONE: | |
167 | return parity_bit == 1 | |
168 | ||
169 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
ac941bf9 | 170 | ones = bin(data).count('1') + parity_bit |
f44d2db2 UH |
171 | |
172 | # Check for odd/even parity. | |
173 | if parity_type == PARITY_ODD: | |
ac941bf9 | 174 | return (ones % 2) == 1 |
f44d2db2 | 175 | elif parity_type == PARITY_EVEN: |
ac941bf9 | 176 | return (ones % 2) == 0 |
f44d2db2 UH |
177 | else: |
178 | raise Exception('Invalid parity type: %d' % parity_type) | |
179 | ||
677d597b | 180 | class Decoder(srd.Decoder): |
a2c2afd9 | 181 | api_version = 1 |
f44d2db2 UH |
182 | id = 'uart' |
183 | name = 'UART' | |
3d3da57d | 184 | longname = 'Universal Asynchronous Receiver/Transmitter' |
f44d2db2 UH |
185 | desc = 'Universal Asynchronous Receiver/Transmitter (UART)' |
186 | longdesc = 'TODO.' | |
f44d2db2 UH |
187 | license = 'gplv2+' |
188 | inputs = ['logic'] | |
189 | outputs = ['uart'] | |
29ed0f4c | 190 | probes = [ |
f44d2db2 UH |
191 | # Allow specifying only one of the signals, e.g. if only one data |
192 | # direction exists (or is relevant). | |
29ed0f4c UH |
193 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
194 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
195 | ] | |
b77614bc | 196 | optional_probes = [] |
f44d2db2 | 197 | options = { |
97cca21f | 198 | 'baudrate': ['Baud rate', 115200], |
f44d2db2 | 199 | 'num_data_bits': ['Data bits', 8], # Valid: 5-9. |
ac941bf9 UH |
200 | 'parity_type': ['Parity type', PARITY_NONE], |
201 | 'parity_check': ['Check parity?', True], # TODO: Bool supported? | |
f44d2db2 UH |
202 | 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1], |
203 | 'bit_order': ['Bit order', LSB_FIRST], | |
f44d2db2 | 204 | # TODO: Options to invert the signal(s). |
f44d2db2 | 205 | } |
e97b6ef5 | 206 | annotations = [ |
97cca21f UH |
207 | ['ASCII', 'Data bytes as ASCII characters'], |
208 | ['Decimal', 'Databytes as decimal, integer values'], | |
209 | ['Hex', 'Data bytes in hex format'], | |
210 | ['Octal', 'Data bytes as octal numbers'], | |
211 | ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'], | |
1bb57ab8 | 212 | ] |
f44d2db2 | 213 | |
97cca21f UH |
214 | def putx(self, rxtx, data): |
215 | self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data) | |
216 | ||
f44d2db2 | 217 | def __init__(self, **kwargs): |
f44d2db2 | 218 | self.samplenum = 0 |
97cca21f UH |
219 | self.frame_start = [-1, -1] |
220 | self.startbit = [-1, -1] | |
221 | self.cur_data_bit = [0, 0] | |
222 | self.databyte = [0, 0] | |
223 | self.stopbit1 = [-1, -1] | |
224 | self.startsample = [-1, -1] | |
f44d2db2 UH |
225 | |
226 | # Initial state. | |
97cca21f | 227 | self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT] |
f44d2db2 | 228 | |
97cca21f | 229 | self.oldbit = [None, None] |
f44d2db2 UH |
230 | |
231 | def start(self, metadata): | |
f44d2db2 | 232 | self.samplerate = metadata['samplerate'] |
56202222 UH |
233 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart') |
234 | self.out_ann = self.add(srd.OUTPUT_ANN, 'uart') | |
f44d2db2 | 235 | |
f44d2db2 | 236 | # The width of one UART bit in number of samples. |
4a04ece4 UH |
237 | self.bit_width = \ |
238 | float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 UH |
239 | |
240 | def report(self): | |
241 | pass | |
242 | ||
243 | # Return true if we reached the middle of the desired bit, false otherwise. | |
97cca21f | 244 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
245 | # bitpos is the samplenumber which is in the middle of the |
246 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
247 | # (if used) or the first stop bit, and so on). | |
97cca21f | 248 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) |
f44d2db2 UH |
249 | bitpos += bitnum * self.bit_width |
250 | if self.samplenum >= bitpos: | |
251 | return True | |
252 | return False | |
253 | ||
97cca21f UH |
254 | def reached_bit_last(self, rxtx, bitnum): |
255 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
256 | if self.samplenum >= bitpos: |
257 | return True | |
258 | return False | |
259 | ||
97cca21f | 260 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
261 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
262 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
263 | if not (old_signal == 1 and signal == 0): | |
264 | return | |
265 | ||
266 | # Save the sample number where the start bit begins. | |
97cca21f | 267 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 268 | |
97cca21f | 269 | self.state[rxtx] = GET_START_BIT |
f44d2db2 | 270 | |
97cca21f | 271 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 272 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 273 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 274 | return |
f44d2db2 | 275 | |
97cca21f | 276 | self.startbit[rxtx] = signal |
f44d2db2 | 277 | |
5cc4b6a0 | 278 | # The startbit must be 0. If not, we report an error. |
97cca21f UH |
279 | if self.startbit[rxtx] != 0: |
280 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, | |
b9e44d1e | 281 | ['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) |
5cc4b6a0 | 282 | # TODO: Abort? Ignore rest of the frame? |
f44d2db2 | 283 | |
97cca21f UH |
284 | self.cur_data_bit[rxtx] = 0 |
285 | self.databyte[rxtx] = 0 | |
286 | self.startsample[rxtx] = -1 | |
f44d2db2 | 287 | |
97cca21f | 288 | self.state[rxtx] = GET_DATA_BITS |
f44d2db2 | 289 | |
97cca21f | 290 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, |
b9e44d1e | 291 | ['STARTBIT', rxtx, self.startbit[rxtx]]) |
97cca21f | 292 | self.put(self.frame_start[rxtx], self.samplenum, self.out_ann, |
5cc4b6a0 | 293 | [ANN_ASCII, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 294 | |
97cca21f | 295 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 296 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 297 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 298 | return |
f44d2db2 UH |
299 | |
300 | # Save the sample number where the data byte starts. | |
97cca21f UH |
301 | if self.startsample[rxtx] == -1: |
302 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
303 | |
304 | # Get the next data bit in LSB-first or MSB-first fashion. | |
4a04ece4 | 305 | if self.options['bit_order'] == LSB_FIRST: |
97cca21f | 306 | self.databyte[rxtx] >>= 1 |
fd4aa8aa UH |
307 | self.databyte[rxtx] |= \ |
308 | (signal << (self.options['num_data_bits'] - 1)) | |
4a04ece4 | 309 | elif self.options['bit_order'] == MSB_FIRST: |
97cca21f UH |
310 | self.databyte[rxtx] <<= 1 |
311 | self.databyte[rxtx] |= (signal << 0) | |
f44d2db2 | 312 | else: |
4a04ece4 UH |
313 | raise Exception('Invalid bit order value: %d', |
314 | self.options['bit_order']) | |
f44d2db2 UH |
315 | |
316 | # Return here, unless we already received all data bits. | |
4a04ece4 UH |
317 | # TODO? Off-by-one? |
318 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: | |
97cca21f | 319 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 320 | return |
f44d2db2 | 321 | |
97cca21f | 322 | self.state[rxtx] = GET_PARITY_BIT |
f44d2db2 | 323 | |
97cca21f | 324 | self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto, |
b9e44d1e | 325 | ['DATA', rxtx, self.databyte[rxtx]]) |
f44d2db2 | 326 | |
97cca21f UH |
327 | s = 'RX: ' if (rxtx == RX) else 'TX: ' |
328 | self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]]) | |
329 | self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]]) | |
330 | self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]), | |
331 | s + hex(self.databyte[rxtx])[2:]]]) | |
332 | self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]), | |
333 | s + oct(self.databyte[rxtx])[2:]]]) | |
334 | self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]), | |
335 | s + bin(self.databyte[rxtx])[2:]]]) | |
f44d2db2 | 336 | |
97cca21f | 337 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 338 | # If no parity is used/configured, skip to the next state immediately. |
ac941bf9 | 339 | if self.options['parity_type'] == PARITY_NONE: |
97cca21f | 340 | self.state[rxtx] = GET_STOP_BITS |
1bb57ab8 | 341 | return |
f44d2db2 UH |
342 | |
343 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 344 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 345 | return |
f44d2db2 | 346 | |
97cca21f | 347 | self.paritybit[rxtx] = signal |
f44d2db2 | 348 | |
97cca21f | 349 | self.state[rxtx] = GET_STOP_BITS |
f44d2db2 | 350 | |
ac941bf9 | 351 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], |
4a04ece4 | 352 | self.databyte[rxtx], self.options['num_data_bits']): |
f44d2db2 | 353 | # TODO: Fix range. |
1bb57ab8 | 354 | self.put(self.samplenum, self.samplenum, self.out_proto, |
b9e44d1e | 355 | ['PARITYBIT', rxtx, self.paritybit[rxtx]]) |
1bb57ab8 | 356 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 357 | [ANN_ASCII, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 358 | else: |
1bb57ab8 | 359 | # TODO: Fix range. |
61132abd | 360 | # TODO: Return expected/actual parity values. |
1bb57ab8 | 361 | self.put(self.samplenum, self.samplenum, self.out_proto, |
b9e44d1e | 362 | ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... |
1bb57ab8 | 363 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 364 | [ANN_ASCII, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
365 | |
366 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 367 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 368 | # Skip samples until we're in the middle of the stop bit(s). |
ac941bf9 | 369 | skip_parity = 0 if self.options['parity_type'] == PARITY_NONE else 1 |
4a04ece4 UH |
370 | b = self.options['num_data_bits'] + 1 + skip_parity |
371 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 372 | return |
f44d2db2 | 373 | |
97cca21f | 374 | self.stopbit1[rxtx] = signal |
f44d2db2 | 375 | |
5cc4b6a0 | 376 | # Stop bits must be 1. If not, we report an error. |
97cca21f UH |
377 | if self.stopbit1[rxtx] != 1: |
378 | self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, | |
b9e44d1e | 379 | ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) |
5cc4b6a0 | 380 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 381 | |
97cca21f | 382 | self.state[rxtx] = WAIT_FOR_START_BIT |
f44d2db2 | 383 | |
f44d2db2 | 384 | # TODO: Fix range. |
1bb57ab8 | 385 | self.put(self.samplenum, self.samplenum, self.out_proto, |
b9e44d1e | 386 | ['STOPBIT', rxtx, self.stopbit1[rxtx]]) |
1bb57ab8 | 387 | self.put(self.samplenum, self.samplenum, self.out_ann, |
5cc4b6a0 | 388 | [ANN_ASCII, ['Stop bit', 'Stop', 'P']]) |
f44d2db2 | 389 | |
decde15e UH |
390 | def decode(self, ss, es, data): |
391 | # TODO: Either RX or TX could be omitted (optional probe). | |
97cca21f | 392 | for (samplenum, (rx, tx)) in data: |
f44d2db2 UH |
393 | |
394 | # TODO: Start counting at 0 or 1? Increase before or after? | |
395 | self.samplenum += 1 | |
396 | ||
397 | # First sample: Save RX/TX value. | |
97cca21f UH |
398 | if self.oldbit[RX] == None: |
399 | self.oldbit[RX] = rx | |
400 | continue | |
401 | if self.oldbit[TX] == None: | |
402 | self.oldbit[TX] = tx | |
f44d2db2 UH |
403 | continue |
404 | ||
f44d2db2 | 405 | # State machine. |
97cca21f UH |
406 | for rxtx in (RX, TX): |
407 | signal = rx if (rxtx == RX) else tx | |
408 | ||
409 | if self.state[rxtx] == WAIT_FOR_START_BIT: | |
410 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) | |
411 | elif self.state[rxtx] == GET_START_BIT: | |
412 | self.get_start_bit(rxtx, signal) | |
413 | elif self.state[rxtx] == GET_DATA_BITS: | |
414 | self.get_data_bits(rxtx, signal) | |
415 | elif self.state[rxtx] == GET_PARITY_BIT: | |
416 | self.get_parity_bit(rxtx, signal) | |
417 | elif self.state[rxtx] == GET_STOP_BITS: | |
418 | self.get_stop_bits(rxtx, signal) | |
419 | else: | |
decde15e | 420 | raise Exception('Invalid state: %d' % self.state[rxtx]) |
97cca21f UH |
421 | |
422 | # Save current RX/TX values for the next round. | |
423 | self.oldbit[rxtx] = signal | |
f44d2db2 | 424 |