1 144-171 uart: ['STARTBIT', 1, 0]
2 170-327 uart: ['DATA', 1, (60, [[0, 170, 196], [0, 196, 222], [1, 222, 248], [1, 248, 274], [1, 274, 300], [1, 300, 326]])]
3 326-353 uart: ['STOPBIT', 1, 1]
4 144-353 uart: ['FRAME', 1, (60, True)]
5 353-562 uart: ['IDLE', 1, 0]
6 607-634 uart: ['STARTBIT', 1, 0]
7 633-790 uart: ['DATA', 1, (61, [[1, 633, 659], [0, 659, 685], [1, 685, 711], [1, 711, 737], [1, 737, 763], [1, 763, 789]])]
8 789-816 uart: ['STOPBIT', 1, 1]
9 607-816 uart: ['FRAME', 1, (61, True)]
10 816-1025 uart: ['IDLE', 1, 0]
11 1071-1098 uart: ['STARTBIT', 1, 0]
12 1097-1254 uart: ['DATA', 1, (62, [[0, 1097, 1123], [1, 1123, 1149], [1, 1149, 1175], [1, 1175, 1201], [1, 1201, 1227], [1, 1227, 1253]])]
13 1253-1280 uart: ['STOPBIT', 1, 1]
14 1071-1280 uart: ['FRAME', 1, (62, True)]
15 1280-1489 uart: ['IDLE', 1, 0]
16 1534-1561 uart: ['STARTBIT', 1, 0]
17 1560-1717 uart: ['DATA', 1, (63, [[1, 1560, 1586], [1, 1586, 1612], [1, 1612, 1638], [1, 1638, 1664], [1, 1664, 1690], [1, 1690, 1716]])]
18 1716-1743 uart: ['STOPBIT', 1, 1]
19 1534-1743 uart: ['FRAME', 1, (63, True)]
20 1743-1952 uart: ['IDLE', 1, 0]
21 1997-2024 uart: ['STARTBIT', 1, 0]
22 2023-2180 uart: ['DATA', 1, (0, [[0, 2023, 2049], [0, 2049, 2075], [0, 2075, 2101], [0, 2101, 2127], [0, 2127, 2153], [0, 2153, 2179]])]
23 2179-2206 uart: ['STOPBIT', 1, 1]
24 1997-2206 uart: ['FRAME', 1, (0, True)]
25 2206-2415 uart: ['IDLE', 1, 0]
26 2459-2486 uart: ['STARTBIT', 1, 0]
27 2485-2642 uart: ['DATA', 1, (1, [[1, 2485, 2511], [0, 2511, 2537], [0, 2537, 2563], [0, 2563, 2589], [0, 2589, 2615], [0, 2615, 2641]])]
28 2641-2668 uart: ['STOPBIT', 1, 1]
29 2459-2668 uart: ['FRAME', 1, (1, True)]
30 2668-2877 uart: ['IDLE', 1, 0]
31 2924-2951 uart: ['STARTBIT', 1, 0]
32 2950-3107 uart: ['DATA', 1, (2, [[0, 2950, 2976], [1, 2976, 3002], [0, 3002, 3028], [0, 3028, 3054], [0, 3054, 3080], [0, 3080, 3106]])]
33 3106-3133 uart: ['STOPBIT', 1, 1]
34 2924-3133 uart: ['FRAME', 1, (2, True)]
35 3133-3342 uart: ['IDLE', 1, 0]
36 3388-3415 uart: ['STARTBIT', 1, 0]
37 3414-3571 uart: ['DATA', 1, (3, [[1, 3414, 3440], [1, 3440, 3466], [0, 3466, 3492], [0, 3492, 3518], [0, 3518, 3544], [0, 3544, 3570]])]
38 3570-3597 uart: ['STOPBIT', 1, 1]
39 3388-3597 uart: ['FRAME', 1, (3, True)]
40 3597-3806 uart: ['IDLE', 1, 0]
41 3853-3880 uart: ['STARTBIT', 1, 0]
42 3879-4036 uart: ['DATA', 1, (4, [[0, 3879, 3905], [0, 3905, 3931], [1, 3931, 3957], [0, 3957, 3983], [0, 3983, 4009], [0, 4009, 4035]])]
43 4035-4062 uart: ['STOPBIT', 1, 1]
44 3853-4062 uart: ['FRAME', 1, (4, True)]
45 4062-4271 uart: ['IDLE', 1, 0]
46 4318-4345 uart: ['STARTBIT', 1, 0]
47 4344-4501 uart: ['DATA', 1, (5, [[1, 4344, 4370], [0, 4370, 4396], [1, 4396, 4422], [0, 4422, 4448], [0, 4448, 4474], [0, 4474, 4500]])]
48 4500-4527 uart: ['STOPBIT', 1, 1]
49 4318-4527 uart: ['FRAME', 1, (5, True)]
50 4527-4736 uart: ['IDLE', 1, 0]
51 4784-4811 uart: ['STARTBIT', 1, 0]
52 4810-4967 uart: ['DATA', 1, (6, [[0, 4810, 4836], [1, 4836, 4862], [1, 4862, 4888], [0, 4888, 4914], [0, 4914, 4940], [0, 4940, 4966]])]
53 4966-4993 uart: ['STOPBIT', 1, 1]
54 4784-4993 uart: ['FRAME', 1, (6, True)]
55 4993-5202 uart: ['IDLE', 1, 0]
56 5249-5276 uart: ['STARTBIT', 1, 0]
57 5275-5432 uart: ['DATA', 1, (7, [[1, 5275, 5301], [1, 5301, 5327], [1, 5327, 5353], [0, 5353, 5379], [0, 5379, 5405], [0, 5405, 5431]])]
58 5431-5458 uart: ['STOPBIT', 1, 1]
59 5249-5458 uart: ['FRAME', 1, (7, True)]
60 5458-5667 uart: ['IDLE', 1, 0]
61 5713-5740 uart: ['STARTBIT', 1, 0]
62 5739-5896 uart: ['DATA', 1, (8, [[0, 5739, 5765], [0, 5765, 5791], [0, 5791, 5817], [1, 5817, 5843], [0, 5843, 5869], [0, 5869, 5895]])]
63 5895-5922 uart: ['STOPBIT', 1, 1]
64 5713-5922 uart: ['FRAME', 1, (8, True)]
65 5922-6131 uart: ['IDLE', 1, 0]
66 6178-6205 uart: ['STARTBIT', 1, 0]
67 6204-6361 uart: ['DATA', 1, (9, [[1, 6204, 6230], [0, 6230, 6256], [0, 6256, 6282], [1, 6282, 6308], [0, 6308, 6334], [0, 6334, 6360]])]
68 6360-6387 uart: ['STOPBIT', 1, 1]
69 6178-6387 uart: ['FRAME', 1, (9, True)]
70 6387-6596 uart: ['IDLE', 1, 0]
71 6645-6672 uart: ['STARTBIT', 1, 0]
72 6671-6828 uart: ['DATA', 1, (10, [[0, 6671, 6697], [1, 6697, 6723], [0, 6723, 6749], [1, 6749, 6775], [0, 6775, 6801], [0, 6801, 6827]])]
73 6827-6854 uart: ['STOPBIT', 1, 1]
74 6645-6854 uart: ['FRAME', 1, (10, True)]
75 6854-7063 uart: ['IDLE', 1, 0]
76 7111-7138 uart: ['STARTBIT', 1, 0]
77 7137-7294 uart: ['DATA', 1, (11, [[1, 7137, 7163], [1, 7163, 7189], [0, 7189, 7215], [1, 7215, 7241], [0, 7241, 7267], [0, 7267, 7293]])]
78 7293-7320 uart: ['STOPBIT', 1, 1]
79 7111-7320 uart: ['FRAME', 1, (11, True)]
80 7320-7529 uart: ['IDLE', 1, 0]
81 7578-7605 uart: ['STARTBIT', 1, 0]
82 7604-7761 uart: ['DATA', 1, (12, [[0, 7604, 7630], [0, 7630, 7656], [1, 7656, 7682], [1, 7682, 7708], [0, 7708, 7734], [0, 7734, 7760]])]
83 7760-7787 uart: ['STOPBIT', 1, 1]
84 7578-7787 uart: ['FRAME', 1, (12, True)]
85 7787-7996 uart: ['IDLE', 1, 0]
86 8042-8069 uart: ['STARTBIT', 1, 0]
87 8068-8225 uart: ['DATA', 1, (13, [[1, 8068, 8094], [0, 8094, 8120], [1, 8120, 8146], [1, 8146, 8172], [0, 8172, 8198], [0, 8198, 8224]])]
88 8224-8251 uart: ['STOPBIT', 1, 1]
89 8042-8251 uart: ['FRAME', 1, (13, True)]
90 8251-8460 uart: ['IDLE', 1, 0]
91 8509-8536 uart: ['STARTBIT', 1, 0]
92 8535-8692 uart: ['DATA', 1, (14, [[0, 8535, 8561], [1, 8561, 8587], [1, 8587, 8613], [1, 8613, 8639], [0, 8639, 8665], [0, 8665, 8691]])]
93 8691-8718 uart: ['STOPBIT', 1, 1]
94 8509-8718 uart: ['FRAME', 1, (14, True)]
95 8718-8927 uart: ['IDLE', 1, 0]
96 8974-9001 uart: ['STARTBIT', 1, 0]
97 9000-9157 uart: ['DATA', 1, (15, [[1, 9000, 9026], [1, 9026, 9052], [1, 9052, 9078], [1, 9078, 9104], [0, 9104, 9130], [0, 9130, 9156]])]
98 9156-9183 uart: ['STOPBIT', 1, 1]
99 8974-9183 uart: ['FRAME', 1, (15, True)]
100 9183-9392 uart: ['IDLE', 1, 0]
101 9438-9465 uart: ['STARTBIT', 1, 0]
102 9464-9621 uart: ['DATA', 1, (16, [[0, 9464, 9490], [0, 9490, 9516], [0, 9516, 9542], [0, 9542, 9568], [1, 9568, 9594], [0, 9594, 9620]])]
103 9620-9647 uart: ['STOPBIT', 1, 1]
104 9438-9647 uart: ['FRAME', 1, (16, True)]
105 9647-9856 uart: ['IDLE', 1, 0]
106 9903-9930 uart: ['STARTBIT', 1, 0]
107 9929-10086 uart: ['DATA', 1, (17, [[1, 9929, 9955], [0, 9955, 9981], [0, 9981, 10007], [0, 10007, 10033], [1, 10033, 10059], [0, 10059, 10085]])]
108 10085-10112 uart: ['STOPBIT', 1, 1]
109 9903-10112 uart: ['FRAME', 1, (17, True)]
110 10112-10321 uart: ['IDLE', 1, 0]
111 10370-10397 uart: ['STARTBIT', 1, 0]
112 10396-10553 uart: ['DATA', 1, (18, [[0, 10396, 10422], [1, 10422, 10448], [0, 10448, 10474], [0, 10474, 10500], [1, 10500, 10526], [0, 10526, 10552]])]
113 10552-10579 uart: ['STOPBIT', 1, 1]
114 10370-10579 uart: ['FRAME', 1, (18, True)]
115 10579-10788 uart: ['IDLE', 1, 0]
116 10836-10863 uart: ['STARTBIT', 1, 0]
117 10862-11019 uart: ['DATA', 1, (19, [[1, 10862, 10888], [1, 10888, 10914], [0, 10914, 10940], [0, 10940, 10966], [1, 10966, 10992], [0, 10992, 11018]])]
118 11018-11045 uart: ['STOPBIT', 1, 1]
119 10836-11045 uart: ['FRAME', 1, (19, True)]
120 11045-11254 uart: ['IDLE', 1, 0]
121 11303-11330 uart: ['STARTBIT', 1, 0]
122 11329-11486 uart: ['DATA', 1, (20, [[0, 11329, 11355], [0, 11355, 11381], [1, 11381, 11407], [0, 11407, 11433], [1, 11433, 11459], [0, 11459, 11485]])]
123 11485-11512 uart: ['STOPBIT', 1, 1]
124 11303-11512 uart: ['FRAME', 1, (20, True)]
125 11512-11721 uart: ['IDLE', 1, 0]
126 11769-11796 uart: ['STARTBIT', 1, 0]
127 11795-11952 uart: ['DATA', 1, (21, [[1, 11795, 11821], [0, 11821, 11847], [1, 11847, 11873], [0, 11873, 11899], [1, 11899, 11925], [0, 11925, 11951]])]
128 11951-11978 uart: ['STOPBIT', 1, 1]
129 11769-11978 uart: ['FRAME', 1, (21, True)]
130 11978-12187 uart: ['IDLE', 1, 0]
131 12238-12265 uart: ['STARTBIT', 1, 0]
132 12264-12421 uart: ['DATA', 1, (22, [[0, 12264, 12290], [1, 12290, 12316], [1, 12316, 12342], [0, 12342, 12368], [1, 12368, 12394], [0, 12394, 12420]])]
133 12420-12447 uart: ['STOPBIT', 1, 1]
134 12238-12447 uart: ['FRAME', 1, (22, True)]
135 12447-12656 uart: ['IDLE', 1, 0]
136 12705-12732 uart: ['STARTBIT', 1, 0]
137 12731-12888 uart: ['DATA', 1, (23, [[1, 12731, 12757], [1, 12757, 12783], [1, 12783, 12809], [0, 12809, 12835], [1, 12835, 12861], [0, 12861, 12887]])]
138 12887-12914 uart: ['STOPBIT', 1, 1]
139 12705-12914 uart: ['FRAME', 1, (23, True)]
140 12914-13123 uart: ['IDLE', 1, 0]
141 13171-13198 uart: ['STARTBIT', 1, 0]
142 13197-13354 uart: ['DATA', 1, (24, [[0, 13197, 13223], [0, 13223, 13249], [0, 13249, 13275], [1, 13275, 13301], [1, 13301, 13327], [0, 13327, 13353]])]
143 13353-13380 uart: ['STOPBIT', 1, 1]
144 13171-13380 uart: ['FRAME', 1, (24, True)]
145 13380-13589 uart: ['IDLE', 1, 0]
146 13636-13663 uart: ['STARTBIT', 1, 0]
147 13662-13819 uart: ['DATA', 1, (25, [[1, 13662, 13688], [0, 13688, 13714], [0, 13714, 13740], [1, 13740, 13766], [1, 13766, 13792], [0, 13792, 13818]])]
148 13818-13845 uart: ['STOPBIT', 1, 1]
149 13636-13845 uart: ['FRAME', 1, (25, True)]
150 13845-14054 uart: ['IDLE', 1, 0]
151 14102-14129 uart: ['STARTBIT', 1, 0]
152 14128-14285 uart: ['DATA', 1, (26, [[0, 14128, 14154], [1, 14154, 14180], [0, 14180, 14206], [1, 14206, 14232], [1, 14232, 14258], [0, 14258, 14284]])]
153 14284-14311 uart: ['STOPBIT', 1, 1]
154 14102-14311 uart: ['FRAME', 1, (26, True)]
155 14311-14520 uart: ['IDLE', 1, 0]
156 14569-14596 uart: ['STARTBIT', 1, 0]
157 14595-14752 uart: ['DATA', 1, (27, [[1, 14595, 14621], [1, 14621, 14647], [0, 14647, 14673], [1, 14673, 14699], [1, 14699, 14725], [0, 14725, 14751]])]
158 14751-14778 uart: ['STOPBIT', 1, 1]
159 14569-14778 uart: ['FRAME', 1, (27, True)]
160 14778-14987 uart: ['IDLE', 1, 0]
161 15036-15063 uart: ['STARTBIT', 1, 0]
162 15062-15219 uart: ['DATA', 1, (28, [[0, 15062, 15088], [0, 15088, 15114], [1, 15114, 15140], [1, 15140, 15166], [1, 15166, 15192], [0, 15192, 15218]])]
163 15218-15245 uart: ['STOPBIT', 1, 1]
164 15036-15245 uart: ['FRAME', 1, (28, True)]
165 15245-15454 uart: ['IDLE', 1, 0]
166 15500-15527 uart: ['STARTBIT', 1, 0]
167 15526-15683 uart: ['DATA', 1, (29, [[1, 15526, 15552], [0, 15552, 15578], [1, 15578, 15604], [1, 15604, 15630], [1, 15630, 15656], [0, 15656, 15682]])]
168 15682-15709 uart: ['STOPBIT', 1, 1]
169 15500-15709 uart: ['FRAME', 1, (29, True)]
170 15709-15918 uart: ['IDLE', 1, 0]
171 15967-15994 uart: ['STARTBIT', 1, 0]
172 15993-16150 uart: ['DATA', 1, (30, [[0, 15993, 16019], [1, 16019, 16045], [1, 16045, 16071], [1, 16071, 16097], [1, 16097, 16123], [0, 16123, 16149]])]
173 16149-16176 uart: ['STOPBIT', 1, 1]
174 15967-16176 uart: ['FRAME', 1, (30, True)]
175 16176-16385 uart: ['IDLE', 1, 0]
176 16432-16459 uart: ['STARTBIT', 1, 0]
177 16458-16615 uart: ['DATA', 1, (31, [[1, 16458, 16484], [1, 16484, 16510], [1, 16510, 16536], [1, 16536, 16562], [1, 16562, 16588], [0, 16588, 16614]])]
178 16614-16641 uart: ['STOPBIT', 1, 1]
179 16432-16641 uart: ['FRAME', 1, (31, True)]
180 16641-16850 uart: ['IDLE', 1, 0]
181 16896-16923 uart: ['STARTBIT', 1, 0]
182 16922-17079 uart: ['DATA', 1, (32, [[0, 16922, 16948], [0, 16948, 16974], [0, 16974, 17000], [0, 17000, 17026], [0, 17026, 17052], [1, 17052, 17078]])]
183 17078-17105 uart: ['STOPBIT', 1, 1]
184 16896-17105 uart: ['FRAME', 1, (32, True)]
185 17105-17314 uart: ['IDLE', 1, 0]
186 17359-17386 uart: ['STARTBIT', 1, 0]
187 17385-17542 uart: ['DATA', 1, (33, [[1, 17385, 17411], [0, 17411, 17437], [0, 17437, 17463], [0, 17463, 17489], [0, 17489, 17515], [1, 17515, 17541]])]
188 17541-17568 uart: ['STOPBIT', 1, 1]
189 17359-17568 uart: ['FRAME', 1, (33, True)]
190 17568-17777 uart: ['IDLE', 1, 0]
191 17823-17850 uart: ['STARTBIT', 1, 0]
192 17849-18006 uart: ['DATA', 1, (34, [[0, 17849, 17875], [1, 17875, 17901], [0, 17901, 17927], [0, 17927, 17953], [0, 17953, 17979], [1, 17979, 18005]])]
193 18005-18032 uart: ['STOPBIT', 1, 1]
194 17823-18032 uart: ['FRAME', 1, (34, True)]
195 18032-18241 uart: ['IDLE', 1, 0]
196 18288-18315 uart: ['STARTBIT', 1, 0]
197 18314-18471 uart: ['DATA', 1, (35, [[1, 18314, 18340], [1, 18340, 18366], [0, 18366, 18392], [0, 18392, 18418], [0, 18418, 18444], [1, 18444, 18470]])]
198 18470-18497 uart: ['STOPBIT', 1, 1]
199 18288-18497 uart: ['FRAME', 1, (35, True)]
200 18497-18706 uart: ['IDLE', 1, 0]
201 18753-18780 uart: ['STARTBIT', 1, 0]
202 18779-18936 uart: ['DATA', 1, (36, [[0, 18779, 18805], [0, 18805, 18831], [1, 18831, 18857], [0, 18857, 18883], [0, 18883, 18909], [1, 18909, 18935]])]
203 18935-18962 uart: ['STOPBIT', 1, 1]
204 18753-18962 uart: ['FRAME', 1, (36, True)]
205 18962-19171 uart: ['IDLE', 1, 0]
206 19217-19244 uart: ['STARTBIT', 1, 0]
207 19243-19400 uart: ['DATA', 1, (37, [[1, 19243, 19269], [0, 19269, 19295], [1, 19295, 19321], [0, 19321, 19347], [0, 19347, 19373], [1, 19373, 19399]])]
208 19399-19426 uart: ['STOPBIT', 1, 1]
209 19217-19426 uart: ['FRAME', 1, (37, True)]
210 19426-19635 uart: ['IDLE', 1, 0]
211 19684-19711 uart: ['STARTBIT', 1, 0]
212 19710-19867 uart: ['DATA', 1, (38, [[0, 19710, 19736], [1, 19736, 19762], [1, 19762, 19788], [0, 19788, 19814], [0, 19814, 19840], [1, 19840, 19866]])]
213 19866-19893 uart: ['STOPBIT', 1, 1]
214 19684-19893 uart: ['FRAME', 1, (38, True)]
215 19893-20102 uart: ['IDLE', 1, 0]
216 20148-20175 uart: ['STARTBIT', 1, 0]
217 20174-20331 uart: ['DATA', 1, (39, [[1, 20174, 20200], [1, 20200, 20226], [1, 20226, 20252], [0, 20252, 20278], [0, 20278, 20304], [1, 20304, 20330]])]
218 20330-20357 uart: ['STOPBIT', 1, 1]
219 20148-20357 uart: ['FRAME', 1, (39, True)]
220 20357-20566 uart: ['IDLE', 1, 0]
221 20613-20640 uart: ['STARTBIT', 1, 0]
222 20639-20796 uart: ['DATA', 1, (40, [[0, 20639, 20665], [0, 20665, 20691], [0, 20691, 20717], [1, 20717, 20743], [0, 20743, 20769], [1, 20769, 20795]])]
223 20795-20822 uart: ['STOPBIT', 1, 1]
224 20613-20822 uart: ['FRAME', 1, (40, True)]
225 20822-21031 uart: ['IDLE', 1, 0]
226 21078-21105 uart: ['STARTBIT', 1, 0]
227 21104-21261 uart: ['DATA', 1, (41, [[1, 21104, 21130], [0, 21130, 21156], [0, 21156, 21182], [1, 21182, 21208], [0, 21208, 21234], [1, 21234, 21260]])]
228 21260-21287 uart: ['STOPBIT', 1, 1]
229 21078-21287 uart: ['FRAME', 1, (41, True)]
230 21287-21496 uart: ['IDLE', 1, 0]
231 21544-21571 uart: ['STARTBIT', 1, 0]
232 21570-21727 uart: ['DATA', 1, (42, [[0, 21570, 21596], [1, 21596, 21622], [0, 21622, 21648], [1, 21648, 21674], [0, 21674, 21700], [1, 21700, 21726]])]
233 21726-21753 uart: ['STOPBIT', 1, 1]
234 21544-21753 uart: ['FRAME', 1, (42, True)]
235 21753-21962 uart: ['IDLE', 1, 0]
236 22011-22038 uart: ['STARTBIT', 1, 0]
237 22037-22194 uart: ['DATA', 1, (43, [[1, 22037, 22063], [1, 22063, 22089], [0, 22089, 22115], [1, 22115, 22141], [0, 22141, 22167], [1, 22167, 22193]])]
238 22193-22220 uart: ['STOPBIT', 1, 1]
239 22011-22220 uart: ['FRAME', 1, (43, True)]
240 22220-22429 uart: ['IDLE', 1, 0]
241 22478-22505 uart: ['STARTBIT', 1, 0]
242 22504-22661 uart: ['DATA', 1, (44, [[0, 22504, 22530], [0, 22530, 22556], [1, 22556, 22582], [1, 22582, 22608], [0, 22608, 22634], [1, 22634, 22660]])]
243 22660-22687 uart: ['STOPBIT', 1, 1]
244 22478-22687 uart: ['FRAME', 1, (44, True)]
245 22687-22896 uart: ['IDLE', 1, 0]
246 22942-22969 uart: ['STARTBIT', 1, 0]
247 22968-23125 uart: ['DATA', 1, (45, [[1, 22968, 22994], [0, 22994, 23020], [1, 23020, 23046], [1, 23046, 23072], [0, 23072, 23098], [1, 23098, 23124]])]
248 23124-23151 uart: ['STOPBIT', 1, 1]
249 22942-23151 uart: ['FRAME', 1, (45, True)]
250 23151-23360 uart: ['IDLE', 1, 0]
251 23409-23436 uart: ['STARTBIT', 1, 0]
252 23435-23592 uart: ['DATA', 1, (46, [[0, 23435, 23461], [1, 23461, 23487], [1, 23487, 23513], [1, 23513, 23539], [0, 23539, 23565], [1, 23565, 23591]])]
253 23591-23618 uart: ['STOPBIT', 1, 1]
254 23409-23618 uart: ['FRAME', 1, (46, True)]
255 23618-23827 uart: ['IDLE', 1, 0]
256 23873-23900 uart: ['STARTBIT', 1, 0]
257 23899-24056 uart: ['DATA', 1, (47, [[1, 23899, 23925], [1, 23925, 23951], [1, 23951, 23977], [1, 23977, 24003], [0, 24003, 24029], [1, 24029, 24055]])]
258 24055-24082 uart: ['STOPBIT', 1, 1]
259 23873-24082 uart: ['FRAME', 1, (47, True)]
260 24082-24291 uart: ['IDLE', 1, 0]
261 24338-24365 uart: ['STARTBIT', 1, 0]
262 24364-24521 uart: ['DATA', 1, (48, [[0, 24364, 24390], [0, 24390, 24416], [0, 24416, 24442], [0, 24442, 24468], [1, 24468, 24494], [1, 24494, 24520]])]
263 24520-24547 uart: ['STOPBIT', 1, 1]
264 24338-24547 uart: ['FRAME', 1, (48, True)]
265 24547-24756 uart: ['IDLE', 1, 0]
266 24801-24828 uart: ['STARTBIT', 1, 0]
267 24827-24984 uart: ['DATA', 1, (49, [[1, 24827, 24853], [0, 24853, 24879], [0, 24879, 24905], [0, 24905, 24931], [1, 24931, 24957], [1, 24957, 24983]])]
268 24983-25010 uart: ['STOPBIT', 1, 1]
269 24801-25010 uart: ['FRAME', 1, (49, True)]
270 25010-25219 uart: ['IDLE', 1, 0]
271 25265-25292 uart: ['STARTBIT', 1, 0]
272 25291-25448 uart: ['DATA', 1, (50, [[0, 25291, 25317], [1, 25317, 25343], [0, 25343, 25369], [0, 25369, 25395], [1, 25395, 25421], [1, 25421, 25447]])]
273 25447-25474 uart: ['STOPBIT', 1, 1]
274 25265-25474 uart: ['FRAME', 1, (50, True)]
275 25474-25683 uart: ['IDLE', 1, 0]
276 25730-25757 uart: ['STARTBIT', 1, 0]
277 25756-25913 uart: ['DATA', 1, (51, [[1, 25756, 25782], [1, 25782, 25808], [0, 25808, 25834], [0, 25834, 25860], [1, 25860, 25886], [1, 25886, 25912]])]
278 25912-25939 uart: ['STOPBIT', 1, 1]
279 25730-25939 uart: ['FRAME', 1, (51, True)]
280 25939-26148 uart: ['IDLE', 1, 0]
281 26194-26221 uart: ['STARTBIT', 1, 0]
282 26220-26377 uart: ['DATA', 1, (52, [[0, 26220, 26246], [0, 26246, 26272], [1, 26272, 26298], [0, 26298, 26324], [1, 26324, 26350], [1, 26350, 26376]])]
283 26376-26403 uart: ['STOPBIT', 1, 1]
284 26194-26403 uart: ['FRAME', 1, (52, True)]
285 26403-26612 uart: ['IDLE', 1, 0]
286 26659-26686 uart: ['STARTBIT', 1, 0]
287 26685-26842 uart: ['DATA', 1, (53, [[1, 26685, 26711], [0, 26711, 26737], [1, 26737, 26763], [0, 26763, 26789], [1, 26789, 26815], [1, 26815, 26841]])]
288 26841-26868 uart: ['STOPBIT', 1, 1]
289 26659-26868 uart: ['FRAME', 1, (53, True)]
290 26868-27077 uart: ['IDLE', 1, 0]
291 27126-27153 uart: ['STARTBIT', 1, 0]
292 27152-27309 uart: ['DATA', 1, (54, [[0, 27152, 27178], [1, 27178, 27204], [1, 27204, 27230], [0, 27230, 27256], [1, 27256, 27282], [1, 27282, 27308]])]
293 27308-27335 uart: ['STOPBIT', 1, 1]
294 27126-27335 uart: ['FRAME', 1, (54, True)]
295 27335-27544 uart: ['IDLE', 1, 0]
296 27590-27617 uart: ['STARTBIT', 1, 0]
297 27616-27773 uart: ['DATA', 1, (55, [[1, 27616, 27642], [1, 27642, 27668], [1, 27668, 27694], [0, 27694, 27720], [1, 27720, 27746], [1, 27746, 27772]])]
298 27772-27799 uart: ['STOPBIT', 1, 1]
299 27590-27799 uart: ['FRAME', 1, (55, True)]
300 27799-28008 uart: ['IDLE', 1, 0]
301 28055-28082 uart: ['STARTBIT', 1, 0]
302 28081-28238 uart: ['DATA', 1, (56, [[0, 28081, 28107], [0, 28107, 28133], [0, 28133, 28159], [1, 28159, 28185], [1, 28185, 28211], [1, 28211, 28237]])]
303 28237-28264 uart: ['STOPBIT', 1, 1]
304 28055-28264 uart: ['FRAME', 1, (56, True)]
305 28264-28473 uart: ['IDLE', 1, 0]
306 28518-28545 uart: ['STARTBIT', 1, 0]
307 28544-28701 uart: ['DATA', 1, (57, [[1, 28544, 28570], [0, 28570, 28596], [0, 28596, 28622], [1, 28622, 28648], [1, 28648, 28674], [1, 28674, 28700]])]
308 28700-28727 uart: ['STOPBIT', 1, 1]
309 28518-28727 uart: ['FRAME', 1, (57, True)]
310 28727-28936 uart: ['IDLE', 1, 0]
311 28982-29009 uart: ['STARTBIT', 1, 0]
312 29008-29165 uart: ['DATA', 1, (58, [[0, 29008, 29034], [1, 29034, 29060], [0, 29060, 29086], [1, 29086, 29112], [1, 29112, 29138], [1, 29138, 29164]])]
313 29164-29191 uart: ['STOPBIT', 1, 1]
314 28982-29191 uart: ['FRAME', 1, (58, True)]
315 29191-29400 uart: ['IDLE', 1, 0]
316 29447-29474 uart: ['STARTBIT', 1, 0]
317 29473-29630 uart: ['DATA', 1, (59, [[1, 29473, 29499], [1, 29499, 29525], [0, 29525, 29551], [1, 29551, 29577], [1, 29577, 29603], [1, 29603, 29629]])]
318 29629-29656 uart: ['STOPBIT', 1, 1]
319 29447-29656 uart: ['FRAME', 1, (59, True)]
320 29656-29865 uart: ['IDLE', 1, 0]
321 29911-29938 uart: ['STARTBIT', 1, 0]
322 29937-30094 uart: ['DATA', 1, (60, [[0, 29937, 29963], [0, 29963, 29989], [1, 29989, 30015], [1, 30015, 30041], [1, 30041, 30067], [1, 30067, 30093]])]
323 30093-30120 uart: ['STOPBIT', 1, 1]
324 29911-30120 uart: ['FRAME', 1, (60, True)]
325 30120-30329 uart: ['IDLE', 1, 0]
326 30374-30401 uart: ['STARTBIT', 1, 0]
327 30400-30557 uart: ['DATA', 1, (61, [[1, 30400, 30426], [0, 30426, 30452], [1, 30452, 30478], [1, 30478, 30504], [1, 30504, 30530], [1, 30530, 30556]])]
328 30556-30583 uart: ['STOPBIT', 1, 1]
329 30374-30583 uart: ['FRAME', 1, (61, True)]
330 30583-30792 uart: ['IDLE', 1, 0]
331 30839-30866 uart: ['STARTBIT', 1, 0]
332 30865-31022 uart: ['DATA', 1, (62, [[0, 30865, 30891], [1, 30891, 30917], [1, 30917, 30943], [1, 30943, 30969], [1, 30969, 30995], [1, 30995, 31021]])]
333 31021-31048 uart: ['STOPBIT', 1, 1]
334 30839-31048 uart: ['FRAME', 1, (62, True)]
335 31048-31257 uart: ['IDLE', 1, 0]
336 31301-31328 uart: ['STARTBIT', 1, 0]
337 31327-31484 uart: ['DATA', 1, (63, [[1, 31327, 31353], [1, 31353, 31379], [1, 31379, 31405], [1, 31405, 31431], [1, 31431, 31457], [1, 31457, 31483]])]
338 31483-31510 uart: ['STOPBIT', 1, 1]
339 31301-31510 uart: ['FRAME', 1, (63, True)]
340 31510-31719 uart: ['IDLE', 1, 0]
341 31764-31791 uart: ['STARTBIT', 1, 0]
342 31790-31947 uart: ['DATA', 1, (0, [[0, 31790, 31816], [0, 31816, 31842], [0, 31842, 31868], [0, 31868, 31894], [0, 31894, 31920], [0, 31920, 31946]])]
343 31946-31973 uart: ['STOPBIT', 1, 1]
344 31764-31973 uart: ['FRAME', 1, (0, True)]
345 31973-32182 uart: ['IDLE', 1, 0]
346 32226-32253 uart: ['STARTBIT', 1, 0]
347 32252-32409 uart: ['DATA', 1, (1, [[1, 32252, 32278], [0, 32278, 32304], [0, 32304, 32330], [0, 32330, 32356], [0, 32356, 32382], [0, 32382, 32408]])]
348 32408-32435 uart: ['STOPBIT', 1, 1]
349 32226-32435 uart: ['FRAME', 1, (1, True)]
350 32435-32644 uart: ['IDLE', 1, 0]
351 32691-32718 uart: ['STARTBIT', 1, 0]
352 32717-32874 uart: ['DATA', 1, (2, [[0, 32717, 32743], [1, 32743, 32769], [0, 32769, 32795], [0, 32795, 32821], [0, 32821, 32847], [0, 32847, 32873]])]
353 32873-32900 uart: ['STOPBIT', 1, 1]
354 32691-32900 uart: ['FRAME', 1, (2, True)]
355 32900-33109 uart: ['IDLE', 1, 0]
356 33156-33183 uart: ['STARTBIT', 1, 0]
357 33182-33339 uart: ['DATA', 1, (3, [[1, 33182, 33208], [1, 33208, 33234], [0, 33234, 33260], [0, 33260, 33286], [0, 33286, 33312], [0, 33312, 33338]])]
358 33338-33365 uart: ['STOPBIT', 1, 1]
359 33156-33365 uart: ['FRAME', 1, (3, True)]
360 33365-33574 uart: ['IDLE', 1, 0]
361 33620-33647 uart: ['STARTBIT', 1, 0]
362 33646-33803 uart: ['DATA', 1, (4, [[0, 33646, 33672], [0, 33672, 33698], [1, 33698, 33724], [0, 33724, 33750], [0, 33750, 33776], [0, 33776, 33802]])]
363 33802-33829 uart: ['STOPBIT', 1, 1]
364 33620-33829 uart: ['FRAME', 1, (4, True)]
projects / sigrok-test.git / blob