projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| ed6cad19 GS |
1 | ------------------------------------------------------------------------------- |
| 2 | SiLabs CP2110 serial-over-HID, UT612 LCR meter | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a capture of UART-over-HID communication to a UNI-T UT612 LCR meter | |
| 6 | which contains the SiLabs CP2110 HID chip and the ES51919 LCR meter chip. | |
| 7 | UART communication uses 9600/8n1, USB HID runs at full speed (USB1.1 12MHz). | |
| 8 | ||
| 9 | The LCR meter actually exclusively transmits data to the PC's RX line. The | |
| 10 | PC's TX traffic is just a development hack in preparation of bidirectional | |
| 11 | communication where cables support it. | |
| 12 | ||
| 13 | ||
| 14 | Logic analyzer setup | |
| 15 | -------------------- | |
| 16 | ||
| 17 | The Asix Sigma analyzer was set to 50MHz samplerate. Capture length is 200M | |
| 18 | samples, which translates to four seconds duration. | |
| 19 | ||
| 20 | Probe CP2110 signals | |
| 21 | -------------------------- | |
| 22 | 1 USB D+ | |
| 23 | 2 USB D- | |
| 24 | 3 UART TX (sigrok to meter) | |
| 25 | 4 UART RX (meter to sigrok) |