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f44d2db2 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
f44d2db2 | 3 | ## |
0bb7bcf3 | 4 | ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
677d597b | 21 | import sigrokdecode as srd |
f44d2db2 | 22 | |
4cace3b8 | 23 | ''' |
c515eed7 | 24 | OUTPUT_PYTHON format: |
4cace3b8 | 25 | |
bf69977d UH |
26 | Packet: |
27 | [<ptype>, <rxtx>, <pdata>] | |
4cace3b8 | 28 | |
bf69977d | 29 | This is the list of <ptype>s and their respective <pdata> values: |
4cace3b8 UH |
30 | - 'STARTBIT': The data is the (integer) value of the start bit (0/1). |
31 | - 'DATA': The data is the (integer) value of the UART data. Valid values | |
32 | range from 0 to 512 (as the data can be up to 9 bits in size). | |
4aedd5b8 | 33 | - 'DATABITS': List of data bits and their ss/es numbers. |
4cace3b8 UH |
34 | - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). |
35 | - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
36 | - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). | |
37 | - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). | |
38 | - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
39 | the expected parity value, the second is the actual parity value. | |
40 | - TODO: Frame error? | |
41 | ||
42 | The <rxtx> field is 0 for RX packets, 1 for TX packets. | |
43 | ''' | |
44 | ||
97cca21f UH |
45 | # Used for differentiating between the two data directions. |
46 | RX = 0 | |
47 | TX = 1 | |
48 | ||
f44d2db2 UH |
49 | # Given a parity type to check (odd, even, zero, one), the value of the |
50 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
51 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
a7fc4c34 | 52 | # 'none' is _not_ allowed as value for 'parity_type'. |
f44d2db2 UH |
53 | def parity_ok(parity_type, parity_bit, data, num_data_bits): |
54 | ||
55 | # Handle easy cases first (parity bit is always 1 or 0). | |
a7fc4c34 | 56 | if parity_type == 'zero': |
f44d2db2 | 57 | return parity_bit == 0 |
a7fc4c34 | 58 | elif parity_type == 'one': |
f44d2db2 UH |
59 | return parity_bit == 1 |
60 | ||
61 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
ac941bf9 | 62 | ones = bin(data).count('1') + parity_bit |
f44d2db2 UH |
63 | |
64 | # Check for odd/even parity. | |
a7fc4c34 | 65 | if parity_type == 'odd': |
ac941bf9 | 66 | return (ones % 2) == 1 |
a7fc4c34 | 67 | elif parity_type == 'even': |
ac941bf9 | 68 | return (ones % 2) == 0 |
f44d2db2 | 69 | |
21cda951 UH |
70 | class SamplerateError(Exception): |
71 | pass | |
72 | ||
677d597b | 73 | class Decoder(srd.Decoder): |
12851357 | 74 | api_version = 2 |
f44d2db2 UH |
75 | id = 'uart' |
76 | name = 'UART' | |
3d3da57d | 77 | longname = 'Universal Asynchronous Receiver/Transmitter' |
a465436e | 78 | desc = 'Asynchronous, serial bus.' |
f44d2db2 UH |
79 | license = 'gplv2+' |
80 | inputs = ['logic'] | |
81 | outputs = ['uart'] | |
6a15597a | 82 | optional_channels = ( |
f44d2db2 UH |
83 | # Allow specifying only one of the signals, e.g. if only one data |
84 | # direction exists (or is relevant). | |
29ed0f4c UH |
85 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
86 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
da9bcbd9 | 87 | ) |
84c1c0b5 BV |
88 | options = ( |
89 | {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, | |
90 | {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, | |
91 | 'values': (5, 6, 7, 8, 9)}, | |
92 | {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', | |
93 | 'values': ('none', 'odd', 'even', 'zero', 'one')}, | |
94 | {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', | |
95 | 'values': ('yes', 'no')}, | |
96 | {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, | |
97 | 'values': (0.0, 0.5, 1.0, 1.5)}, | |
98 | {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', | |
99 | 'values': ('lsb-first', 'msb-first')}, | |
100 | {'id': 'format', 'desc': 'Data format', 'default': 'ascii', | |
101 | 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, | |
f44d2db2 | 102 | # TODO: Options to invert the signal(s). |
84c1c0b5 | 103 | ) |
da9bcbd9 BV |
104 | annotations = ( |
105 | ('rx-data', 'RX data'), | |
106 | ('tx-data', 'TX data'), | |
107 | ('rx-start', 'RX start bits'), | |
108 | ('tx-start', 'TX start bits'), | |
109 | ('rx-parity-ok', 'RX parity OK bits'), | |
110 | ('tx-parity-ok', 'TX parity OK bits'), | |
111 | ('rx-parity-err', 'RX parity error bits'), | |
112 | ('tx-parity-err', 'TX parity error bits'), | |
113 | ('rx-stop', 'RX stop bits'), | |
114 | ('tx-stop', 'TX stop bits'), | |
115 | ('rx-warnings', 'RX warnings'), | |
116 | ('tx-warnings', 'TX warnings'), | |
117 | ('rx-data-bits', 'RX data bits'), | |
118 | ('tx-data-bits', 'TX data bits'), | |
119 | ) | |
2ce20a91 | 120 | annotation_rows = ( |
4e3b276a | 121 | ('rx-data', 'RX', (0, 2, 4, 6, 8)), |
4aedd5b8 | 122 | ('rx-data-bits', 'RX bits', (12,)), |
4e3b276a | 123 | ('rx-warnings', 'RX warnings', (10,)), |
4aedd5b8 UH |
124 | ('tx-data', 'TX', (1, 3, 5, 7, 9)), |
125 | ('tx-data-bits', 'TX bits', (13,)), | |
4e3b276a | 126 | ('tx-warnings', 'TX warnings', (11,)), |
2ce20a91 | 127 | ) |
0bb7bcf3 UH |
128 | binary = ( |
129 | ('rx', 'RX dump'), | |
130 | ('tx', 'TX dump'), | |
131 | ('rxtx', 'RX/TX dump'), | |
132 | ) | |
f44d2db2 | 133 | |
97cca21f | 134 | def putx(self, rxtx, data): |
15ac6604 UH |
135 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) |
136 | self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) | |
137 | ||
4aedd5b8 UH |
138 | def putpx(self, rxtx, data): |
139 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
140 | self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data) | |
141 | ||
15ac6604 UH |
142 | def putg(self, data): |
143 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
144 | self.put(s - halfbit, s + halfbit, self.out_ann, data) | |
145 | ||
146 | def putp(self, data): | |
147 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
c515eed7 | 148 | self.put(s - halfbit, s + halfbit, self.out_python, data) |
97cca21f | 149 | |
0bb7bcf3 UH |
150 | def putbin(self, rxtx, data): |
151 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) | |
152 | self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data) | |
153 | ||
f44d2db2 | 154 | def __init__(self, **kwargs): |
f372d597 | 155 | self.samplerate = None |
f44d2db2 | 156 | self.samplenum = 0 |
97cca21f UH |
157 | self.frame_start = [-1, -1] |
158 | self.startbit = [-1, -1] | |
159 | self.cur_data_bit = [0, 0] | |
160 | self.databyte = [0, 0] | |
1ccef461 | 161 | self.paritybit = [-1, -1] |
97cca21f UH |
162 | self.stopbit1 = [-1, -1] |
163 | self.startsample = [-1, -1] | |
2b716038 | 164 | self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] |
83be7b83 UH |
165 | self.oldbit = [1, 1] |
166 | self.oldpins = [1, 1] | |
4aedd5b8 | 167 | self.databits = [[], []] |
f44d2db2 | 168 | |
f372d597 | 169 | def start(self): |
c515eed7 | 170 | self.out_python = self.register(srd.OUTPUT_PYTHON) |
0bb7bcf3 | 171 | self.out_bin = self.register(srd.OUTPUT_BINARY) |
be465111 | 172 | self.out_ann = self.register(srd.OUTPUT_ANN) |
f44d2db2 | 173 | |
f372d597 BV |
174 | def metadata(self, key, value): |
175 | if key == srd.SRD_CONF_SAMPLERATE: | |
35b380b1 | 176 | self.samplerate = value |
f372d597 BV |
177 | # The width of one UART bit in number of samples. |
178 | self.bit_width = float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 | 179 | |
f44d2db2 | 180 | # Return true if we reached the middle of the desired bit, false otherwise. |
97cca21f | 181 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
182 | # bitpos is the samplenumber which is in the middle of the |
183 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
184 | # (if used) or the first stop bit, and so on). | |
97cca21f | 185 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) |
f44d2db2 UH |
186 | bitpos += bitnum * self.bit_width |
187 | if self.samplenum >= bitpos: | |
188 | return True | |
189 | return False | |
190 | ||
97cca21f UH |
191 | def reached_bit_last(self, rxtx, bitnum): |
192 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
193 | if self.samplenum >= bitpos: |
194 | return True | |
195 | return False | |
196 | ||
97cca21f | 197 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
198 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
199 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
200 | if not (old_signal == 1 and signal == 0): | |
201 | return | |
202 | ||
203 | # Save the sample number where the start bit begins. | |
97cca21f | 204 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 205 | |
2b716038 | 206 | self.state[rxtx] = 'GET START BIT' |
f44d2db2 | 207 | |
97cca21f | 208 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 209 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 210 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 211 | return |
f44d2db2 | 212 | |
97cca21f | 213 | self.startbit[rxtx] = signal |
f44d2db2 | 214 | |
5cc4b6a0 | 215 | # The startbit must be 0. If not, we report an error. |
97cca21f | 216 | if self.startbit[rxtx] != 0: |
15ac6604 | 217 | self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) |
5cc4b6a0 | 218 | # TODO: Abort? Ignore rest of the frame? |
f44d2db2 | 219 | |
97cca21f UH |
220 | self.cur_data_bit[rxtx] = 0 |
221 | self.databyte[rxtx] = 0 | |
222 | self.startsample[rxtx] = -1 | |
f44d2db2 | 223 | |
2b716038 | 224 | self.state[rxtx] = 'GET DATA BITS' |
f44d2db2 | 225 | |
15ac6604 | 226 | self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) |
2ce20a91 | 227 | self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 228 | |
97cca21f | 229 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 230 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 231 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 232 | return |
f44d2db2 | 233 | |
15ac6604 | 234 | # Save the sample number of the middle of the first data bit. |
97cca21f UH |
235 | if self.startsample[rxtx] == -1: |
236 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
237 | |
238 | # Get the next data bit in LSB-first or MSB-first fashion. | |
a7fc4c34 | 239 | if self.options['bit_order'] == 'lsb-first': |
97cca21f | 240 | self.databyte[rxtx] >>= 1 |
fd4aa8aa UH |
241 | self.databyte[rxtx] |= \ |
242 | (signal << (self.options['num_data_bits'] - 1)) | |
22fc7ace | 243 | else: |
97cca21f UH |
244 | self.databyte[rxtx] <<= 1 |
245 | self.databyte[rxtx] |= (signal << 0) | |
f44d2db2 | 246 | |
4aedd5b8 UH |
247 | self.putg([rxtx + 12, ['%d' % signal]]) |
248 | ||
249 | # Store individual data bits and their start/end samplenumbers. | |
250 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
251 | self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) | |
252 | ||
f44d2db2 | 253 | # Return here, unless we already received all data bits. |
4a04ece4 | 254 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: |
97cca21f | 255 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 256 | return |
f44d2db2 | 257 | |
2b716038 | 258 | self.state[rxtx] = 'GET PARITY BIT' |
f44d2db2 | 259 | |
4aedd5b8 UH |
260 | self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]]) |
261 | self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]]) | |
f44d2db2 | 262 | |
3006c663 UH |
263 | b, f = self.databyte[rxtx], self.options['format'] |
264 | if f == 'ascii': | |
e0a0123d | 265 | c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b |
8705ddc8 | 266 | self.putx(rxtx, [rxtx, [c]]) |
3006c663 | 267 | elif f == 'dec': |
6d6b32d6 | 268 | self.putx(rxtx, [rxtx, [str(b)]]) |
3006c663 | 269 | elif f == 'hex': |
6d6b32d6 | 270 | self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]]) |
3006c663 | 271 | elif f == 'oct': |
6d6b32d6 | 272 | self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) |
3006c663 | 273 | elif f == 'bin': |
6d6b32d6 | 274 | self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) |
f44d2db2 | 275 | |
0bb7bcf3 UH |
276 | self.putbin(rxtx, (rxtx, bytes([b]))) |
277 | self.putbin(rxtx, (2, bytes([b]))) | |
278 | ||
4aedd5b8 UH |
279 | self.databits = [[], []] |
280 | ||
97cca21f | 281 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 282 | # If no parity is used/configured, skip to the next state immediately. |
a7fc4c34 | 283 | if self.options['parity_type'] == 'none': |
2b716038 | 284 | self.state[rxtx] = 'GET STOP BITS' |
1bb57ab8 | 285 | return |
f44d2db2 UH |
286 | |
287 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 288 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 289 | return |
f44d2db2 | 290 | |
97cca21f | 291 | self.paritybit[rxtx] = signal |
f44d2db2 | 292 | |
2b716038 | 293 | self.state[rxtx] = 'GET STOP BITS' |
f44d2db2 | 294 | |
ac941bf9 | 295 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], |
4a04ece4 | 296 | self.databyte[rxtx], self.options['num_data_bits']): |
15ac6604 | 297 | self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) |
2ce20a91 | 298 | self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 299 | else: |
61132abd | 300 | # TODO: Return expected/actual parity values. |
15ac6604 | 301 | self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... |
4e3b276a | 302 | self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
303 | |
304 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 305 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 306 | # Skip samples until we're in the middle of the stop bit(s). |
a7fc4c34 | 307 | skip_parity = 0 if self.options['parity_type'] == 'none' else 1 |
4a04ece4 UH |
308 | b = self.options['num_data_bits'] + 1 + skip_parity |
309 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 310 | return |
f44d2db2 | 311 | |
97cca21f | 312 | self.stopbit1[rxtx] = signal |
f44d2db2 | 313 | |
5cc4b6a0 | 314 | # Stop bits must be 1. If not, we report an error. |
97cca21f | 315 | if self.stopbit1[rxtx] != 1: |
15ac6604 | 316 | self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) |
4e3b276a | 317 | self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']]) |
5cc4b6a0 | 318 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 319 | |
2b716038 | 320 | self.state[rxtx] = 'WAIT FOR START BIT' |
f44d2db2 | 321 | |
15ac6604 | 322 | self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) |
2ce20a91 | 323 | self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) |
f44d2db2 | 324 | |
decde15e | 325 | def decode(self, ss, es, data): |
21cda951 UH |
326 | if not self.samplerate: |
327 | raise SamplerateError('Cannot decode without samplerate.') | |
2fcd7c22 UH |
328 | for (self.samplenum, pins) in data: |
329 | ||
b0827236 UH |
330 | # Note: Ignoring identical samples here for performance reasons |
331 | # is not possible for this PD, at least not in the current state. | |
332 | # if self.oldpins == pins: | |
333 | # continue | |
2fcd7c22 | 334 | self.oldpins, (rx, tx) = pins, pins |
f44d2db2 | 335 | |
3dd546c1 UH |
336 | # Either RX or TX (but not both) can be omitted. |
337 | has_pin = [rx in (0, 1), tx in (0, 1)] | |
338 | if has_pin == [False, False]: | |
339 | raise Exception('Either TX or RX (or both) pins required.') | |
340 | ||
f44d2db2 | 341 | # State machine. |
97cca21f | 342 | for rxtx in (RX, TX): |
3dd546c1 UH |
343 | # Don't try to handle RX (or TX) if not supplied. |
344 | if not has_pin[rxtx]: | |
345 | continue | |
346 | ||
97cca21f UH |
347 | signal = rx if (rxtx == RX) else tx |
348 | ||
2b716038 | 349 | if self.state[rxtx] == 'WAIT FOR START BIT': |
97cca21f | 350 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) |
2b716038 | 351 | elif self.state[rxtx] == 'GET START BIT': |
97cca21f | 352 | self.get_start_bit(rxtx, signal) |
2b716038 | 353 | elif self.state[rxtx] == 'GET DATA BITS': |
97cca21f | 354 | self.get_data_bits(rxtx, signal) |
2b716038 | 355 | elif self.state[rxtx] == 'GET PARITY BIT': |
97cca21f | 356 | self.get_parity_bit(rxtx, signal) |
2b716038 | 357 | elif self.state[rxtx] == 'GET STOP BITS': |
97cca21f | 358 | self.get_stop_bits(rxtx, signal) |
97cca21f UH |
359 | |
360 | # Save current RX/TX values for the next round. | |
361 | self.oldbit[rxtx] = signal |