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d4eabea8 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Bert Vermeulen <bert@biot.com> | |
4ee1e2f3 AG |
5 | * Copyright (C) 2015 Google, Inc. |
6 | * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.) | |
7e66bf05 | 7 | * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net> |
d4eabea8 BV |
8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
6ec6c43b | 23 | #include <config.h> |
22c18b03 | 24 | #include <string.h> |
ba464a12 | 25 | #include <strings.h> |
d4eabea8 BV |
26 | #include "protocol.h" |
27 | ||
28 | #define CH_IDX(x) (1 << x) | |
6ed709fe | 29 | #define FREQ_DC_ONLY {0, 0, 0, 0, 0} |
49a468ed FS |
30 | #define NO_OVP_LIMITS {0, 0, 0, 0, 0} |
31 | #define NO_OCP_LIMITS {0, 0, 0, 0, 0} | |
d4eabea8 | 32 | |
5c9e56c9 AG |
33 | /* Agilent/Keysight N5700A series */ |
34 | static const uint32_t agilent_n5700a_devopts[] = { | |
e91bb0a6 | 35 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
36 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
37 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
5c9e56c9 AG |
38 | }; |
39 | ||
40 | static const uint32_t agilent_n5700a_devopts_cg[] = { | |
41 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
42 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
43 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
44 | SR_CONF_VOLTAGE | SR_CONF_GET, |
45 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
46 | SR_CONF_CURRENT | SR_CONF_GET, | |
47 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
5c9e56c9 AG |
48 | }; |
49 | ||
6cc93128 | 50 | static const struct channel_group_spec agilent_n5700a_cg[] = { |
f2bbcc33 | 51 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
6cc93128 AG |
52 | }; |
53 | ||
8cb5affe | 54 | static const struct channel_spec agilent_n5767a_ch[] = { |
49a468ed | 55 | { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
5c9e56c9 AG |
56 | }; |
57 | ||
6cc93128 | 58 | static const struct channel_spec agilent_n5763a_ch[] = { |
49a468ed | 59 | { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
5c9e56c9 AG |
60 | }; |
61 | ||
62 | /* | |
63 | * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit | |
562a3490 | 64 | * in STAT:QUES:EVEN?, but this is not implemented. |
5c9e56c9 | 65 | */ |
8cb5affe | 66 | static const struct scpi_command agilent_n5700a_cmd[] = { |
5c9e56c9 AG |
67 | { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" }, |
68 | { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" }, | |
69 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
70 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
71 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
72 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
73 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
74 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
75 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" }, | |
76 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
77 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
78 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, | |
79 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, | |
80 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" }, | |
81 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"}, | |
82 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"}, | |
562a3490 | 83 | /* Current limit (CC mode) and OCP are set using the same command. */ |
5c9e56c9 AG |
84 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" }, |
85 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" }, | |
91ef511d | 86 | ALL_ZERO |
5c9e56c9 AG |
87 | }; |
88 | ||
c3bfb959 MW |
89 | /* BK Precision 9130 series */ |
90 | static const uint32_t bk_9130_devopts[] = { | |
91 | SR_CONF_CONTINUOUS, | |
92 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
93 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
94 | }; | |
95 | ||
96 | static const uint32_t bk_9130_devopts_cg[] = { | |
97 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
98 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
99 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
100 | SR_CONF_CURRENT | SR_CONF_GET, | |
101 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
102 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
103 | }; | |
104 | ||
105 | static const struct channel_spec bk_9130_ch[] = { | |
106 | { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
107 | { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
108 | { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
109 | }; | |
110 | ||
111 | static const struct channel_group_spec bk_9130_cg[] = { | |
f2bbcc33 FS |
112 | { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC }, |
113 | { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC }, | |
114 | { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC }, | |
c3bfb959 MW |
115 | }; |
116 | ||
117 | static const struct scpi_command bk_9130_cmd[] = { | |
118 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
119 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
120 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
121 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
122 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
123 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" }, | |
124 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
125 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
126 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
127 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
128 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
129 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" }, | |
130 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" }, | |
131 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" }, | |
132 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" }, | |
133 | ALL_ZERO | |
134 | }; | |
135 | ||
4ee1e2f3 AG |
136 | /* Chroma 61600 series AC source */ |
137 | static const uint32_t chroma_61604_devopts[] = { | |
e91bb0a6 | 138 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
139 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
140 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
4ee1e2f3 AG |
141 | }; |
142 | ||
143 | static const uint32_t chroma_61604_devopts_cg[] = { | |
144 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
145 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
146 | SR_CONF_VOLTAGE | SR_CONF_GET, |
147 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
6c0c9dd2 AG |
148 | SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET, |
149 | SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
da005885 UH |
150 | SR_CONF_CURRENT | SR_CONF_GET, |
151 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
4ee1e2f3 AG |
152 | }; |
153 | ||
8cb5affe | 154 | static const struct channel_spec chroma_61604_ch[] = { |
49a468ed | 155 | { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
4ee1e2f3 AG |
156 | }; |
157 | ||
8cb5affe | 158 | static const struct channel_group_spec chroma_61604_cg[] = { |
f2bbcc33 | 159 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC }, |
4ee1e2f3 AG |
160 | }; |
161 | ||
8cb5affe | 162 | static const struct scpi_command chroma_61604_cmd[] = { |
4ee1e2f3 AG |
163 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
164 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
165 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" }, | |
6c0c9dd2 | 166 | { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" }, |
4ee1e2f3 AG |
167 | { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" }, |
168 | { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" }, | |
169 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" }, | |
170 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" }, | |
6c0c9dd2 AG |
171 | { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" }, |
172 | { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" }, | |
4ee1e2f3 AG |
173 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, |
174 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
175 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
176 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" }, | |
177 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" }, | |
562a3490 | 178 | /* This is not a current limit mode. It is overcurrent protection. */ |
4ee1e2f3 AG |
179 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" }, |
180 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" }, | |
91ef511d | 181 | ALL_ZERO |
4ee1e2f3 AG |
182 | }; |
183 | ||
5281993e | 184 | /* Chroma 62000 series DC source */ |
5281993e | 185 | static const uint32_t chroma_62000_devopts[] = { |
e91bb0a6 | 186 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
187 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
188 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
5281993e AG |
189 | }; |
190 | ||
191 | static const uint32_t chroma_62000_devopts_cg[] = { | |
192 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
193 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
194 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
195 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
196 | SR_CONF_CURRENT | SR_CONF_GET, | |
197 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
198 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
199 | }; | |
200 | ||
5281993e | 201 | static const struct channel_group_spec chroma_62000_cg[] = { |
f2bbcc33 | 202 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
5281993e AG |
203 | }; |
204 | ||
205 | static const struct scpi_command chroma_62000_cmd[] = { | |
206 | { SCPI_CMD_REMOTE, ":CONF:REM ON" }, | |
207 | { SCPI_CMD_LOCAL, ":CONF:REM OFF" }, | |
208 | { SCPI_CMD_BEEPER, ":CONF:BEEP?" }, | |
209 | { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" }, | |
210 | { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" }, | |
211 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
212 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
213 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" }, | |
214 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
215 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" }, | |
216 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
217 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
218 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" }, | |
219 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" }, | |
220 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" }, | |
221 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" }, | |
222 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" }, | |
223 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" }, | |
224 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" }, | |
91ef511d | 225 | ALL_ZERO |
5281993e AG |
226 | }; |
227 | ||
9a5185c7 AG |
228 | static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi, |
229 | struct sr_scpi_hw_info *hw_info, | |
230 | struct channel_spec **channels, unsigned int *num_channels, | |
231 | struct channel_group_spec **channel_groups, | |
232 | unsigned int *num_channel_groups) | |
233 | { | |
6ed709fe | 234 | unsigned int volts, amps, watts; |
9a5185c7 AG |
235 | struct channel_spec *channel; |
236 | ||
237 | (void)sdi; | |
238 | ||
6ed709fe AJ |
239 | sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &s); |
240 | watts *= 100; | |
241 | sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts); | |
9a5185c7 AG |
242 | |
243 | if (volts > 600) { | |
244 | sr_err("Probed max voltage of %u V is out of spec.", volts); | |
245 | return SR_ERR_BUG; | |
246 | } | |
247 | ||
6ed709fe | 248 | if (amps > 120) { |
9a5185c7 AG |
249 | sr_err("Probed max current of %u A is out of spec.", amps); |
250 | return SR_ERR_BUG; | |
251 | } | |
252 | ||
6ed709fe AJ |
253 | if (watts > 5000) { |
254 | sr_err("Probed max power of %u W is out of spec.", watts); | |
255 | return SR_ERR_BUG; | |
256 | } | |
257 | ||
9a5185c7 AG |
258 | channel = g_malloc0(sizeof(struct channel_spec)); |
259 | channel->name = "1"; | |
6ed709fe | 260 | channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0; |
bcee1299 UH |
261 | channel->voltage[1] = volts; |
262 | channel->current[1] = amps; | |
263 | channel->power[1] = watts; | |
9a5185c7 | 264 | channel->voltage[2] = channel->current[2] = 0.01; |
6ed709fe AJ |
265 | channel->voltage[3] = channel->voltage[4] = 3; |
266 | channel->current[3] = channel->current[4] = 4; | |
9a5185c7 AG |
267 | *channels = channel; |
268 | *num_channels = 1; | |
269 | ||
270 | *channel_groups = g_malloc(sizeof(struct channel_group_spec)); | |
271 | **channel_groups = chroma_62000_cg[0]; | |
272 | *num_channel_groups = 1; | |
273 | ||
274 | return SR_OK; | |
275 | } | |
276 | ||
319fe9ce UH |
277 | /* Rigol DP700 series */ |
278 | static const uint32_t rigol_dp700_devopts[] = { | |
279 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
280 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
281 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
319fe9ce UH |
282 | }; |
283 | ||
284 | static const uint32_t rigol_dp700_devopts_cg[] = { | |
285 | SR_CONF_REGULATION | SR_CONF_GET, | |
286 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
287 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
d828b05e | 288 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
319fe9ce UH |
289 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
290 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
d828b05e | 291 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
319fe9ce UH |
292 | SR_CONF_VOLTAGE | SR_CONF_GET, |
293 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
294 | SR_CONF_CURRENT | SR_CONF_GET, | |
295 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
296 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
297 | }; | |
298 | ||
299 | static const struct channel_spec rigol_dp711_ch[] = { | |
d828b05e | 300 | { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } }, |
319fe9ce UH |
301 | }; |
302 | ||
303 | static const struct channel_spec rigol_dp712_ch[] = { | |
d828b05e | 304 | { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } }, |
319fe9ce UH |
305 | }; |
306 | ||
307 | static const struct channel_group_spec rigol_dp700_cg[] = { | |
f2bbcc33 | 308 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
319fe9ce UH |
309 | }; |
310 | ||
311 | /* Same as the DP800 series, except for the missing :SYST:OTP* commands. */ | |
312 | static const struct scpi_command rigol_dp700_cmd[] = { | |
313 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
314 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
315 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, | |
316 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
317 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
318 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
319 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
320 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
321 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
322 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
323 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
324 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
325 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
326 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
327 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
328 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
329 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
330 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, | |
331 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
332 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
333 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
334 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
335 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
336 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
337 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
338 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
339 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
340 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
341 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
342 | ALL_ZERO | |
343 | }; | |
344 | ||
d4eabea8 | 345 | /* Rigol DP800 series */ |
584560f1 | 346 | static const uint32_t rigol_dp800_devopts[] = { |
e91bb0a6 | 347 | SR_CONF_CONTINUOUS, |
5827f61b | 348 | SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET, |
88e4daa9 ML |
349 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
350 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
d4eabea8 BV |
351 | }; |
352 | ||
584560f1 | 353 | static const uint32_t rigol_dp800_devopts_cg[] = { |
7a0b98b5 | 354 | SR_CONF_REGULATION | SR_CONF_GET, |
5827f61b BV |
355 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
356 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
357 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
358 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
359 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
360 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
7a0b98b5 AJ |
361 | SR_CONF_VOLTAGE | SR_CONF_GET, |
362 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
363 | SR_CONF_CURRENT | SR_CONF_GET, | |
364 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
365 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
d4eabea8 BV |
366 | }; |
367 | ||
8cb5affe | 368 | static const struct channel_spec rigol_dp821a_ch[] = { |
49a468ed FS |
369 | { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
370 | { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
cfcdf576 ML |
371 | }; |
372 | ||
8cb5affe | 373 | static const struct channel_spec rigol_dp831_ch[] = { |
49a468ed FS |
374 | { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
375 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
376 | { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
d4eabea8 BV |
377 | }; |
378 | ||
8cb5affe | 379 | static const struct channel_spec rigol_dp832_ch[] = { |
49a468ed FS |
380 | { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
381 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
382 | { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
3222ee10 BV |
383 | }; |
384 | ||
8cb5affe | 385 | static const struct channel_group_spec rigol_dp820_cg[] = { |
f2bbcc33 FS |
386 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
387 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
cfcdf576 ML |
388 | }; |
389 | ||
8cb5affe | 390 | static const struct channel_group_spec rigol_dp830_cg[] = { |
f2bbcc33 FS |
391 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
392 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
393 | { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
d4eabea8 BV |
394 | }; |
395 | ||
8cb5affe | 396 | static const struct scpi_command rigol_dp800_cmd[] = { |
60475cd7 BV |
397 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, |
398 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
ee2860ee BV |
399 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, |
400 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
401 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
60475cd7 BV |
402 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
403 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
404 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
405 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
406 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
407 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
408 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
409 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
410 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
411 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
412 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
413 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
d4eabea8 | 414 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" }, |
53a81803 BV |
415 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" }, |
416 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" }, | |
60475cd7 BV |
417 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, |
418 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
419 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
420 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
421 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
422 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
423 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
424 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
425 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
426 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
427 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
428 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
91ef511d | 429 | ALL_ZERO |
d4eabea8 BV |
430 | }; |
431 | ||
dbc519f7 | 432 | /* HP 663xA series */ |
e76a3575 AG |
433 | static const uint32_t hp_6630a_devopts[] = { |
434 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
435 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
436 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
7c517d02 FS |
437 | }; |
438 | ||
439 | static const uint32_t hp_6630a_devopts_cg[] = { | |
e76a3575 AG |
440 | SR_CONF_ENABLED | SR_CONF_SET, |
441 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
442 | SR_CONF_CURRENT | SR_CONF_GET, | |
443 | SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST, | |
444 | SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST, | |
49a468ed | 445 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST, |
e76a3575 AG |
446 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET, |
447 | }; | |
448 | ||
dbc519f7 FS |
449 | static const struct channel_spec hp_6633a_ch[] = { |
450 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, | |
451 | }; | |
452 | ||
453 | static const struct channel_group_spec hp_6630a_cg[] = { | |
454 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
455 | }; | |
456 | ||
457 | static const struct scpi_command hp_6630a_cmd[] = { | |
458 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" }, | |
459 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" }, | |
460 | { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" }, | |
461 | { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" }, | |
462 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" }, | |
463 | { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" }, | |
464 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" }, | |
465 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" }, | |
466 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" }, | |
467 | ALL_ZERO | |
468 | }; | |
469 | ||
470 | /* HP 663xB series */ | |
a61c8cce | 471 | static const uint32_t hp_6630b_devopts[] = { |
e91bb0a6 | 472 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
473 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
474 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
7c517d02 FS |
475 | }; |
476 | ||
a61c8cce | 477 | static const uint32_t hp_6630b_devopts_cg[] = { |
7a0b98b5 AJ |
478 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
479 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
480 | SR_CONF_CURRENT | SR_CONF_GET, | |
481 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
482 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
8b5eadf4 | 483 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
49a468ed | 484 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
7e381bfc | 485 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
8b5eadf4 FS |
486 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, |
487 | SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET, | |
43ff1110 | 488 | SR_CONF_REGULATION | SR_CONF_GET, |
bc4a2a46 BV |
489 | }; |
490 | ||
a61c8cce | 491 | static const struct channel_spec hp_6631b_ch[] = { |
49a468ed | 492 | { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS }, |
a61c8cce FS |
493 | }; |
494 | ||
8cb5affe | 495 | static const struct channel_spec hp_6632b_ch[] = { |
49a468ed | 496 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, |
bc4a2a46 BV |
497 | }; |
498 | ||
a61c8cce | 499 | static const struct channel_spec hp_66332a_ch[] = { |
49a468ed | 500 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, |
a61c8cce FS |
501 | }; |
502 | ||
503 | static const struct channel_spec hp_6633b_ch[] = { | |
49a468ed | 504 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, |
a61c8cce FS |
505 | }; |
506 | ||
507 | static const struct channel_spec hp_6634b_ch[] = { | |
49a468ed | 508 | { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS }, |
a61c8cce FS |
509 | }; |
510 | ||
dbc519f7 | 511 | static const struct channel_group_spec hp_6630b_cg[] = { |
3d1aa50f | 512 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
bc4a2a46 BV |
513 | }; |
514 | ||
a61c8cce | 515 | static const struct scpi_command hp_6630b_cmd[] = { |
7e381bfc FS |
516 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
517 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
bc4a2a46 | 518 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" }, |
53a81803 BV |
519 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" }, |
520 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" }, | |
bc4a2a46 BV |
521 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, |
522 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
ca95e90f BV |
523 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, |
524 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
525 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
526 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
7e381bfc FS |
527 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" }, |
528 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" }, | |
529 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" }, | |
8b5eadf4 FS |
530 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, |
531 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, | |
7e381bfc FS |
532 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, |
533 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, | |
8b5eadf4 | 534 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, |
43ff1110 | 535 | { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" }, |
91ef511d | 536 | ALL_ZERO |
bc4a2a46 BV |
537 | }; |
538 | ||
fe4bb774 FS |
539 | static int hp_6630b_init_aquisition(const struct sr_dev_inst *sdi) |
540 | { | |
541 | struct sr_scpi_dev_inst *scpi; | |
542 | int ret; | |
543 | ||
544 | scpi = sdi->conn; | |
545 | ||
546 | /* | |
547 | * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the | |
548 | * Operational Status Register. | |
549 | * Use both positive and negative transitions of the status bits. | |
550 | */ | |
551 | ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328"); | |
552 | if (ret != SR_OK) | |
553 | return ret; | |
554 | ||
555 | /* | |
556 | * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the | |
557 | * Questionable Status Register. | |
558 | * Use both positive and negative transitions of the status bits. | |
559 | */ | |
560 | ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043"); | |
561 | if (ret != SR_OK) | |
562 | return ret; | |
563 | ||
564 | /* | |
565 | * Service Request Enable Register set for Operational Status Register | |
566 | * bits (128) and Questionable Status Register bits (8). | |
567 | * This masks the Status Register generating a SRQ/RQS. Not implemented yet! | |
568 | */ | |
569 | /* | |
570 | ret = sr_scpi_send(scpi, "*SRE 136"); | |
571 | if (ret != SR_OK) | |
572 | return ret; | |
573 | */ | |
574 | ||
575 | return SR_OK; | |
576 | } | |
577 | ||
578 | static int hp_6630b_update_status(const struct sr_dev_inst *sdi) | |
579 | { | |
580 | struct sr_scpi_dev_inst *scpi; | |
581 | int ret; | |
582 | int stb; | |
583 | int ques_even, ques_cond; | |
584 | int oper_even, oper_cond; | |
585 | gboolean output_enabled; | |
586 | gboolean unreg, cv, cc_pos, cc_neg; | |
587 | gboolean regulation_changed; | |
588 | char *regulation; | |
589 | ||
590 | scpi = sdi->conn; | |
591 | ||
592 | unreg = FALSE; | |
593 | cv = FALSE; | |
594 | cc_pos = FALSE; | |
595 | cc_neg = FALSE; | |
596 | regulation_changed = FALSE; | |
597 | ||
598 | /* | |
599 | * Use SPoll when SCPI uses GPIB as transport layer. | |
600 | * SPoll is approx. twice as fast as a normal GPIB write + read would be! | |
601 | */ | |
602 | #ifdef HAVE_LIBGPIB | |
603 | char spoll_buf; | |
604 | ||
605 | if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) { | |
606 | ret = sr_scpi_gpib_spoll(scpi, &spoll_buf); | |
607 | if (ret != SR_OK) | |
608 | return ret; | |
609 | stb = (uint8_t)spoll_buf; | |
610 | } | |
611 | else { | |
612 | #endif | |
613 | ret = sr_scpi_get_int(scpi, "*STB?", &stb); | |
614 | if (ret != SR_OK) | |
615 | return ret; | |
616 | #ifdef HAVE_LIBGPIB | |
617 | } | |
618 | #endif | |
619 | ||
620 | /* Questionable status summary bit */ | |
621 | if (stb & (1 << 3)) { | |
622 | /* Read the event register to clear it! */ | |
623 | ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even); | |
624 | if (ret != SR_OK) | |
625 | return ret; | |
626 | /* Now get the values. */ | |
627 | ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond); | |
628 | if (ret != SR_OK) | |
629 | return ret; | |
630 | ||
631 | /* OVP */ | |
632 | if (ques_even & (1 << 0)) | |
633 | sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE, | |
634 | g_variant_new_boolean(ques_cond & (1 << 0))); | |
635 | ||
636 | /* OCP */ | |
637 | if (ques_even & (1 << 1)) | |
638 | sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE, | |
639 | g_variant_new_boolean(ques_cond & (1 << 1))); | |
640 | ||
641 | /* OTP */ | |
642 | if (ques_even & (1 << 4)) | |
643 | sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE, | |
644 | g_variant_new_boolean(ques_cond & (1 << 4))); | |
645 | ||
646 | /* UNREG */ | |
647 | unreg = (ques_cond & (1 << 10)); | |
648 | regulation_changed = (ques_even & (1 << 10)) | regulation_changed; | |
649 | ||
650 | /* | |
651 | * Check if output state has changed, due to one of the | |
652 | * questionable states changed. | |
653 | * NOTE: The output state is send even if it hasn't changed, but that | |
654 | * only happends rarely. | |
655 | */ | |
656 | ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled); | |
657 | if (ret != SR_OK) | |
658 | return ret; | |
659 | sr_session_send_meta(sdi, SR_CONF_ENABLED, | |
660 | g_variant_new_boolean(output_enabled)); | |
661 | } | |
662 | ||
663 | /* Operation status summary bit */ | |
664 | if (stb & (1 << 7)) { | |
665 | /* Read the event register to clear it! */ | |
666 | ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even); | |
667 | if (ret != SR_OK) | |
668 | return ret; | |
669 | /* Now get the values. */ | |
670 | ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond); | |
671 | if (ret != SR_OK) | |
672 | return ret; | |
673 | ||
674 | /* CV */ | |
675 | cv = (oper_cond & (1 << 8)); | |
676 | regulation_changed = (oper_even & (1 << 8)) | regulation_changed; | |
677 | /* CC+ */ | |
678 | cc_pos = (oper_cond & (1 << 10)); | |
679 | regulation_changed = (oper_even & (1 << 10)) | regulation_changed; | |
680 | /* CC- */ | |
681 | cc_neg = (oper_cond & (1 << 11)); | |
682 | regulation_changed = (oper_even & (1 << 11)) | regulation_changed; | |
683 | } | |
684 | ||
685 | if (regulation_changed) { | |
686 | if (cv && !cc_pos && !cc_neg &&!unreg) | |
687 | regulation = "CV"; | |
688 | else if (cc_pos && !cv && !cc_neg && !unreg) | |
689 | regulation = "CC"; | |
690 | else if (cc_neg && !cv && !cc_pos && !unreg) | |
691 | regulation = "CC-"; | |
692 | else if (unreg && !cv && !cc_pos && !cc_neg) | |
693 | regulation = "UR"; | |
694 | else if (!cv && !cc_pos && !cc_neg &&!unreg) | |
695 | /* This happends in case of OCP active */ | |
696 | regulation = ""; | |
697 | else { | |
698 | /* This happends from time to time (CV and CC+ active). */ | |
699 | sr_dbg("Undefined regulation for HP 66xxB " | |
700 | "(CV=%i, CC+=%i, CC-=%i, UR=%i).", | |
701 | cv, cc_pos, cc_neg, unreg); | |
702 | return FALSE; | |
703 | } | |
704 | sr_session_send_meta(sdi, SR_CONF_REGULATION, | |
705 | g_variant_new_string(regulation)); | |
706 | } | |
707 | ||
708 | return SR_OK; | |
709 | } | |
710 | ||
c3eadb07 | 711 | /* Philips/Fluke PM2800 series */ |
9d9cf1c4 | 712 | static const uint32_t philips_pm2800_devopts[] = { |
e91bb0a6 | 713 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
714 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
715 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
9d9cf1c4 BV |
716 | }; |
717 | ||
c3eadb07 | 718 | static const uint32_t philips_pm2800_devopts_cg[] = { |
7a0b98b5 AJ |
719 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
720 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
721 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
722 | SR_CONF_CURRENT | SR_CONF_GET, | |
723 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
c3eadb07 BV |
724 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
725 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
726 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
727 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
7a0b98b5 | 728 | SR_CONF_REGULATION | SR_CONF_GET, |
c3eadb07 BV |
729 | }; |
730 | ||
731 | enum philips_pm2800_modules { | |
732 | PM2800_MOD_30V_10A = 1, | |
733 | PM2800_MOD_60V_5A, | |
734 | PM2800_MOD_60V_10A, | |
735 | PM2800_MOD_8V_15A, | |
736 | PM2800_MOD_60V_2A, | |
737 | PM2800_MOD_120V_1A, | |
738 | }; | |
739 | ||
329733d9 | 740 | static const struct philips_pm2800_module_spec { |
c3eadb07 | 741 | /* Min, max, programming resolution. */ |
bcee1299 UH |
742 | double voltage[5]; |
743 | double current[5]; | |
744 | double power[5]; | |
c3eadb07 BV |
745 | } philips_pm2800_module_specs[] = { |
746 | /* Autoranging modules. */ | |
6ed709fe AJ |
747 | [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } }, |
748 | [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } }, | |
749 | [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } }, | |
c3eadb07 | 750 | /* Linear modules. */ |
6ed709fe AJ |
751 | [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } }, |
752 | [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } }, | |
753 | [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } }, | |
c3eadb07 BV |
754 | }; |
755 | ||
329733d9 | 756 | static const struct philips_pm2800_model { |
c3eadb07 BV |
757 | unsigned int chassis; |
758 | unsigned int num_modules; | |
759 | unsigned int set; | |
760 | unsigned int modules[3]; | |
761 | } philips_pm2800_matrix[] = { | |
762 | /* Autoranging chassis. */ | |
763 | { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } }, | |
764 | { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } }, | |
765 | { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } }, | |
766 | { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } }, | |
767 | { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } }, | |
768 | { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } }, | |
769 | { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } }, | |
770 | { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } }, | |
771 | { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
772 | { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } }, | |
773 | { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
774 | /* Linear chassis. */ | |
775 | { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
776 | { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
777 | { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } }, | |
778 | { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
779 | { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
780 | { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } }, | |
781 | { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } }, | |
782 | }; | |
783 | ||
329733d9 | 784 | static const char *philips_pm2800_names[] = { "1", "2", "3" }; |
c3eadb07 BV |
785 | |
786 | static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi, | |
787 | struct sr_scpi_hw_info *hw_info, | |
788 | struct channel_spec **channels, unsigned int *num_channels, | |
789 | struct channel_group_spec **channel_groups, unsigned int *num_channel_groups) | |
790 | { | |
329733d9 UH |
791 | const struct philips_pm2800_model *model; |
792 | const struct philips_pm2800_module_spec *spec; | |
c3eadb07 BV |
793 | unsigned int chassis, num_modules, set, module, m, i; |
794 | ||
795 | (void)sdi; | |
796 | ||
797 | /* | |
798 | * The model number as reported by *IDN? looks like e.g. PM2813/11, | |
799 | * Where "PM28" is fixed, followed by the chassis code (1 = autoranging, | |
800 | * 3 = linear series) and the number of modules: 1-3 for autoranging, | |
801 | * 1-2 for linear. | |
802 | * After the slash, the first digit denotes the module set. The | |
803 | * digit after that denotes front (5) or rear (1) binding posts. | |
804 | */ | |
805 | chassis = hw_info->model[4] - 0x30; | |
806 | num_modules = hw_info->model[5] - 0x30; | |
807 | set = hw_info->model[7] - 0x30; | |
808 | for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) { | |
809 | model = &philips_pm2800_matrix[m]; | |
810 | if (model->chassis == chassis && model->num_modules == num_modules | |
811 | && model->set == set) | |
812 | break; | |
813 | } | |
814 | if (m == ARRAY_SIZE(philips_pm2800_matrix)) { | |
815 | sr_dbg("Model %s not found in matrix.", hw_info->model); | |
816 | return SR_ERR; | |
817 | } | |
818 | ||
819 | sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : ""); | |
820 | *channels = g_malloc0(sizeof(struct channel_spec) * num_modules); | |
821 | *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules); | |
822 | for (i = 0; i < num_modules; i++) { | |
823 | module = model->modules[i]; | |
824 | spec = &philips_pm2800_module_specs[module]; | |
6ed709fe | 825 | sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1, |
c3eadb07 | 826 | spec->voltage[0], spec->voltage[1], |
6ed709fe | 827 | spec->current[0], spec->current[1], |
d9251a2c | 828 | spec->power[0], spec->power[1]); |
329733d9 | 829 | (*channels)[i].name = (char *)philips_pm2800_names[i]; |
bcee1299 | 830 | memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15); |
329733d9 | 831 | (*channel_groups)[i].name = (char *)philips_pm2800_names[i]; |
c3eadb07 BV |
832 | (*channel_groups)[i].channel_index_mask = 1 << i; |
833 | (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP; | |
f2bbcc33 | 834 | (*channel_groups)[i].mqflags = SR_MQFLAG_DC; |
c3eadb07 BV |
835 | } |
836 | *num_channels = *num_channel_groups = num_modules; | |
837 | ||
838 | return SR_OK; | |
839 | } | |
840 | ||
8cb5affe | 841 | static const struct scpi_command philips_pm2800_cmd[] = { |
c3eadb07 BV |
842 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
843 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
844 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
845 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
846 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
847 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
848 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
849 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
850 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
851 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
852 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" }, | |
853 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" }, | |
854 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" }, | |
855 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" }, | |
856 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" }, | |
857 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" }, | |
858 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" }, | |
859 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" }, | |
91ef511d | 860 | ALL_ZERO |
c3eadb07 BV |
861 | }; |
862 | ||
81eb36d6 MS |
863 | static const uint32_t rs_hmc8043_devopts[] = { |
864 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
865 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
866 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
81eb36d6 MS |
867 | }; |
868 | ||
869 | static const uint32_t rs_hmc8043_devopts_cg[] = { | |
870 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
871 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
872 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
873 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
874 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
875 | SR_CONF_CURRENT | SR_CONF_GET, | |
876 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
877 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
878 | }; | |
879 | ||
880 | static const struct channel_spec rs_hmc8043_ch[] = { | |
49a468ed FS |
881 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
882 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
883 | { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
81eb36d6 MS |
884 | }; |
885 | ||
886 | static const struct channel_group_spec rs_hmc8043_cg[] = { | |
f2bbcc33 FS |
887 | { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC }, |
888 | { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC }, | |
889 | { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC }, | |
81eb36d6 MS |
890 | }; |
891 | ||
892 | static const struct scpi_command rs_hmc8043_cmd[] = { | |
893 | { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" }, | |
894 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
895 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
896 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
897 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
898 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
899 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
900 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
901 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" }, | |
902 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" }, | |
903 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" }, | |
904 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" }, | |
905 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" }, | |
906 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" }, | |
907 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" }, | |
908 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" }, | |
909 | ALL_ZERO | |
910 | }; | |
911 | ||
d4eabea8 | 912 | SR_PRIV const struct scpi_pps pps_profiles[] = { |
6cc93128 | 913 | /* Agilent N5763A */ |
5e7377f4 | 914 | { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0, |
6cc93128 AG |
915 | ARRAY_AND_SIZE(agilent_n5700a_devopts), |
916 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
917 | ARRAY_AND_SIZE(agilent_n5763a_ch), | |
918 | ARRAY_AND_SIZE(agilent_n5700a_cg), | |
919 | agilent_n5700a_cmd, | |
920 | .probe_channels = NULL, | |
7e66bf05 FS |
921 | .init_aquisition = NULL, |
922 | .update_status = NULL, | |
6cc93128 | 923 | }, |
ca314e06 | 924 | |
5c9e56c9 | 925 | /* Agilent N5767A */ |
5e7377f4 | 926 | { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0, |
5c9e56c9 AG |
927 | ARRAY_AND_SIZE(agilent_n5700a_devopts), |
928 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
929 | ARRAY_AND_SIZE(agilent_n5767a_ch), | |
6cc93128 | 930 | ARRAY_AND_SIZE(agilent_n5700a_cg), |
91ef511d | 931 | agilent_n5700a_cmd, |
5c9e56c9 | 932 | .probe_channels = NULL, |
7e66bf05 FS |
933 | .init_aquisition = NULL, |
934 | .update_status = NULL, | |
5c9e56c9 | 935 | }, |
ca314e06 | 936 | |
c3bfb959 | 937 | /* BK Precision 9310 */ |
5e7377f4 | 938 | { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0, |
c3bfb959 MW |
939 | ARRAY_AND_SIZE(bk_9130_devopts), |
940 | ARRAY_AND_SIZE(bk_9130_devopts_cg), | |
941 | ARRAY_AND_SIZE(bk_9130_ch), | |
942 | ARRAY_AND_SIZE(bk_9130_cg), | |
943 | bk_9130_cmd, | |
944 | .probe_channels = NULL, | |
7e66bf05 FS |
945 | .init_aquisition = NULL, |
946 | .update_status = NULL, | |
c3bfb959 MW |
947 | }, |
948 | ||
4ee1e2f3 | 949 | /* Chroma 61604 */ |
5e7377f4 | 950 | { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0, |
4ee1e2f3 AG |
951 | ARRAY_AND_SIZE(chroma_61604_devopts), |
952 | ARRAY_AND_SIZE(chroma_61604_devopts_cg), | |
953 | ARRAY_AND_SIZE(chroma_61604_ch), | |
954 | ARRAY_AND_SIZE(chroma_61604_cg), | |
91ef511d | 955 | chroma_61604_cmd, |
4ee1e2f3 | 956 | .probe_channels = NULL, |
7e66bf05 FS |
957 | .init_aquisition = NULL, |
958 | .update_status = NULL, | |
4ee1e2f3 | 959 | }, |
ca314e06 | 960 | |
5281993e | 961 | /* Chroma 62000 series */ |
5e7377f4 | 962 | { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0, |
5281993e AG |
963 | ARRAY_AND_SIZE(chroma_62000_devopts), |
964 | ARRAY_AND_SIZE(chroma_62000_devopts_cg), | |
9a5185c7 AG |
965 | NULL, 0, |
966 | NULL, 0, | |
91ef511d | 967 | chroma_62000_cmd, |
9a5185c7 | 968 | .probe_channels = chroma_62000p_probe_channels, |
7e66bf05 FS |
969 | .init_aquisition = NULL, |
970 | .update_status = NULL, | |
5281993e | 971 | }, |
ca314e06 | 972 | |
e76a3575 | 973 | /* HP 6633A */ |
5e7377f4 | 974 | { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0, |
e76a3575 | 975 | ARRAY_AND_SIZE(hp_6630a_devopts), |
7c517d02 | 976 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), |
e76a3575 | 977 | ARRAY_AND_SIZE(hp_6633a_ch), |
dbc519f7 | 978 | ARRAY_AND_SIZE(hp_6630a_cg), |
e76a3575 AG |
979 | hp_6630a_cmd, |
980 | .probe_channels = NULL, | |
7e66bf05 FS |
981 | .init_aquisition = NULL, |
982 | .update_status = NULL, | |
e76a3575 AG |
983 | }, |
984 | ||
a61c8cce | 985 | /* HP 6631B */ |
3d1aa50f | 986 | { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
987 | ARRAY_AND_SIZE(hp_6630b_devopts), |
988 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
989 | ARRAY_AND_SIZE(hp_6631b_ch), | |
dbc519f7 | 990 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
991 | hp_6630b_cmd, |
992 | .probe_channels = NULL, | |
fe4bb774 FS |
993 | hp_6630b_init_aquisition, |
994 | hp_6630b_update_status, | |
a61c8cce FS |
995 | }, |
996 | ||
bc4a2a46 | 997 | /* HP 6632B */ |
3d1aa50f | 998 | { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
999 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1000 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
bc4a2a46 | 1001 | ARRAY_AND_SIZE(hp_6632b_ch), |
dbc519f7 | 1002 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1003 | hp_6630b_cmd, |
1004 | .probe_channels = NULL, | |
fe4bb774 FS |
1005 | hp_6630b_init_aquisition, |
1006 | hp_6630b_update_status, | |
a61c8cce FS |
1007 | }, |
1008 | ||
1009 | /* HP 66332A */ | |
3d1aa50f | 1010 | { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1011 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1012 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1013 | ARRAY_AND_SIZE(hp_66332a_ch), | |
dbc519f7 | 1014 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1015 | hp_6630b_cmd, |
1016 | .probe_channels = NULL, | |
fe4bb774 FS |
1017 | hp_6630b_init_aquisition, |
1018 | hp_6630b_update_status, | |
a61c8cce FS |
1019 | }, |
1020 | ||
1021 | /* HP 6633B */ | |
3d1aa50f | 1022 | { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1023 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1024 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1025 | ARRAY_AND_SIZE(hp_6633b_ch), | |
dbc519f7 | 1026 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1027 | hp_6630b_cmd, |
1028 | .probe_channels = NULL, | |
fe4bb774 FS |
1029 | hp_6630b_init_aquisition, |
1030 | hp_6630b_update_status, | |
a61c8cce FS |
1031 | }, |
1032 | ||
1033 | /* HP 6634B */ | |
3d1aa50f | 1034 | { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1035 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1036 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1037 | ARRAY_AND_SIZE(hp_6634b_ch), | |
dbc519f7 | 1038 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce | 1039 | hp_6630b_cmd, |
c3eadb07 | 1040 | .probe_channels = NULL, |
fe4bb774 FS |
1041 | hp_6630b_init_aquisition, |
1042 | hp_6630b_update_status, | |
bc4a2a46 BV |
1043 | }, |
1044 | ||
319fe9ce | 1045 | /* Rigol DP700 series */ |
5e7377f4 | 1046 | { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0, |
319fe9ce UH |
1047 | ARRAY_AND_SIZE(rigol_dp700_devopts), |
1048 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
1049 | ARRAY_AND_SIZE(rigol_dp711_ch), | |
1050 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
1051 | rigol_dp700_cmd, | |
1052 | .probe_channels = NULL, | |
7e66bf05 FS |
1053 | .init_aquisition = NULL, |
1054 | .update_status = NULL, | |
319fe9ce | 1055 | }, |
5e7377f4 | 1056 | { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0, |
319fe9ce UH |
1057 | ARRAY_AND_SIZE(rigol_dp700_devopts), |
1058 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
1059 | ARRAY_AND_SIZE(rigol_dp712_ch), | |
1060 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
1061 | rigol_dp700_cmd, | |
1062 | .probe_channels = NULL, | |
7e66bf05 FS |
1063 | .init_aquisition = NULL, |
1064 | .update_status = NULL, | |
319fe9ce UH |
1065 | }, |
1066 | ||
d4eabea8 | 1067 | /* Rigol DP800 series */ |
5e7377f4 | 1068 | { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
cfcdf576 ML |
1069 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1070 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1071 | ARRAY_AND_SIZE(rigol_dp821a_ch), | |
1072 | ARRAY_AND_SIZE(rigol_dp820_cg), | |
91ef511d | 1073 | rigol_dp800_cmd, |
cfcdf576 | 1074 | .probe_channels = NULL, |
7e66bf05 FS |
1075 | .init_aquisition = NULL, |
1076 | .update_status = NULL, | |
cfcdf576 | 1077 | }, |
5e7377f4 | 1078 | { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
3222ee10 BV |
1079 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1080 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1081 | ARRAY_AND_SIZE(rigol_dp831_ch), | |
cfcdf576 | 1082 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 1083 | rigol_dp800_cmd, |
c3eadb07 | 1084 | .probe_channels = NULL, |
7e66bf05 FS |
1085 | .init_aquisition = NULL, |
1086 | .update_status = NULL, | |
3222ee10 | 1087 | }, |
5e7377f4 | 1088 | { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
3222ee10 BV |
1089 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1090 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1091 | ARRAY_AND_SIZE(rigol_dp832_ch), | |
cfcdf576 | 1092 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 1093 | rigol_dp800_cmd, |
c3eadb07 | 1094 | .probe_channels = NULL, |
7e66bf05 FS |
1095 | .init_aquisition = NULL, |
1096 | .update_status = NULL, | |
c3eadb07 BV |
1097 | }, |
1098 | ||
1099 | /* Philips/Fluke PM2800 series */ | |
5e7377f4 | 1100 | { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0, |
9d9cf1c4 | 1101 | ARRAY_AND_SIZE(philips_pm2800_devopts), |
c3eadb07 BV |
1102 | ARRAY_AND_SIZE(philips_pm2800_devopts_cg), |
1103 | NULL, 0, | |
1104 | NULL, 0, | |
91ef511d | 1105 | philips_pm2800_cmd, |
c3eadb07 | 1106 | philips_pm2800_probe_channels, |
7e66bf05 FS |
1107 | .init_aquisition = NULL, |
1108 | .update_status = NULL, | |
d4eabea8 | 1109 | }, |
81eb36d6 MS |
1110 | |
1111 | /* Rohde & Schwarz HMC8043 */ | |
5e7377f4 | 1112 | { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0, |
81eb36d6 MS |
1113 | ARRAY_AND_SIZE(rs_hmc8043_devopts), |
1114 | ARRAY_AND_SIZE(rs_hmc8043_devopts_cg), | |
1115 | ARRAY_AND_SIZE(rs_hmc8043_ch), | |
1116 | ARRAY_AND_SIZE(rs_hmc8043_cg), | |
1117 | rs_hmc8043_cmd, | |
1118 | .probe_channels = NULL, | |
7e66bf05 FS |
1119 | .init_aquisition = NULL, |
1120 | .update_status = NULL, | |
81eb36d6 | 1121 | }, |
d4eabea8 | 1122 | }; |
d4eabea8 | 1123 | |
1beccaed | 1124 | SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles); |