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Drop unneeded std_session_send_df_header() comments.
[libsigrok.git] / src / hardware / rigol-ds / api.c
CommitLineData
f4816ac6
ML		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
88e429c9 5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
bafd4890 6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
f4816ac6
ML		 7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
6ec6c43b 22#include <config.h>
e0b7d23c
ML		 23#include <fcntl.h>
24#include <unistd.h>
25#include <stdlib.h>
26#include <string.h>
ba464a12 27#include <strings.h>
2b0e4a46 28#include <math.h>
f4816ac6 29#include <glib.h>
c1aae900 30#include <libsigrok/libsigrok.h>
f4816ac6 31#include "libsigrok-internal.h"
5a1afc09 32#include "scpi.h"
f4816ac6
ML		 33#include "protocol.h"
34
a0e0bb41 35static const uint32_t scanopts[] = {
ca55277c 36 SR_CONF_CONN,
0dc7b43e 37 SR_CONF_SERIALCOMM
ca55277c
ML		 38};
39
f254bc4b 40static const uint32_t devopts[] = {
1953564a 41 SR_CONF_OSCILLOSCOPE,
5827f61b
BV		 42 SR_CONF_LIMIT_FRAMES | SR_CONF_SET,
43 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
44 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
b0c9d1d1 45 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
5827f61b 46 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
bf622e6d 47 SR_CONF_NUM_HDIV | SR_CONF_GET,
5827f61b 48 SR_CONF_SAMPLERATE | SR_CONF_GET,
f579d08b 49 SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
f48e0249
ML		 50};
51
f254bc4b 52static const uint32_t analog_devopts[] = {
5827f61b
BV		 53 SR_CONF_NUM_VDIV | SR_CONF_GET,
54 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
55 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
e0b7d23c
ML		 56};
57
f6a0ac9f 58static const uint64_t timebases[][2] = {
e0b7d23c 59 /* nanoseconds */
8e06edf5 60 { 1, 1000000000 },
e0b7d23c
ML		 61 { 2, 1000000000 },
62 { 5, 1000000000 },
63 { 10, 1000000000 },
64 { 20, 1000000000 },
65 { 50, 1000000000 },
66 { 100, 1000000000 },
67 { 500, 1000000000 },
68 /* microseconds */
69 { 1, 1000000 },
70 { 2, 1000000 },
71 { 5, 1000000 },
72 { 10, 1000000 },
73 { 20, 1000000 },
74 { 50, 1000000 },
75 { 100, 1000000 },
76 { 200, 1000000 },
77 { 500, 1000000 },
78 /* milliseconds */
79 { 1, 1000 },
80 { 2, 1000 },
81 { 5, 1000 },
82 { 10, 1000 },
83 { 20, 1000 },
84 { 50, 1000 },
85 { 100, 1000 },
86 { 200, 1000 },
87 { 500, 1000 },
88 /* seconds */
89 { 1, 1 },
90 { 2, 1 },
91 { 5, 1 },
92 { 10, 1 },
93 { 20, 1 },
94 { 50, 1 },
bafd4890
ML		 95 { 100, 1 },
96 { 200, 1 },
97 { 500, 1 },
8e06edf5 98 { 1000, 1 },
e0b7d23c
ML		 99};
100
f6a0ac9f 101static const uint64_t vdivs[][2] = {
bafd4890
ML		 102 /* microvolts */
103 { 500, 1000000 },
e0b7d23c 104 /* millivolts */
bafd4890 105 { 1, 1000 },
e0b7d23c
ML		 106 { 2, 1000 },
107 { 5, 1000 },
108 { 10, 1000 },
109 { 20, 1000 },
110 { 50, 1000 },
111 { 100, 1000 },
112 { 200, 1000 },
113 { 500, 1000 },
114 /* volts */
115 { 1, 1 },
116 { 2, 1 },
117 { 5, 1 },
118 { 10, 1 },
d50725e0
UH		 119 { 20, 1 },
120 { 50, 1 },
121 { 100, 1 },
e0b7d23c
ML		 122};
123
bafd4890
ML		 124#define NUM_TIMEBASE ARRAY_SIZE(timebases)
125#define NUM_VDIV ARRAY_SIZE(vdivs)
126
e0b7d23c
ML		 127static const char *trigger_sources[] = {
128 "CH1",
129 "CH2",
821fbcad
ML		 130 "CH3",
131 "CH4",
e0b7d23c
ML		 132 "EXT",
133 "AC Line",
6bb192bc
ML		 134 "D0",
135 "D1",
136 "D2",
137 "D3",
138 "D4",
139 "D5",
140 "D6",
141 "D7",
142 "D8",
143 "D9",
144 "D10",
145 "D11",
146 "D12",
147 "D13",
148 "D14",
149 "D15",
e0b7d23c
ML		 150};
151
5d336f11
AJ		 152static const char *trigger_slopes[] = {
153 "r",
154 "f",
155};
156
e0b7d23c
ML		 157static const char *coupling[] = {
158 "AC",
159 "DC",
160 "GND",
e0b7d23c
ML		 161};
162
babab622
ML		 163/* Do not change the order of entries */
164static const char *data_sources[] = {
165 "Live",
166 "Memory",
167 "Segmented",
168};
169
569d4dbd
ML		 170enum vendor {
171 RIGOL,
172 AGILENT,
173};
174
175enum series {
176 VS5000,
177 DS1000,
178 DS2000,
179 DS2000A,
180 DSO1000,
702f42e8 181 DS1000Z,
569d4dbd 182};
10afee13 183
569d4dbd
ML		 184/* short name, full name */
185static const struct rigol_ds_vendor supported_vendors[] = {
186 [RIGOL] = {"Rigol", "Rigol Technologies"},
14e1aa6d 187 [AGILENT] = {"Agilent", "Agilent Technologies"},
569d4dbd
ML		 188};
189
190#define VENDOR(x) &supported_vendors[x]
191/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
192 * live waveform samples, memory buffer samples */
193static const struct rigol_ds_series supported_series[] = {
194 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
195 {50, 1}, {2, 1000}, 14, 2048, 0},
196 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
197 {50, 1}, {2, 1000}, 12, 600, 1048576},
198 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
96cb7faa 199 {500, 1}, {500, 1000000}, 14, 1400, 14000},
569d4dbd
ML		 200 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
201 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
202 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
203 {50, 1}, {2, 1000}, 12, 600, 20480},
702f42e8
ML		 204 [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
205 {50, 1}, {1, 1000}, 12, 1200, 12000000},
569d4dbd 206};
10afee13 207
569d4dbd
ML		 208#define SERIES(x) &supported_series[x]
209/* series, model, min timebase, analog channels, digital */
bafd4890 210static const struct rigol_ds_model supported_models[] = {
569d4dbd
ML		 211 {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
212 {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
213 {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
214 {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
215 {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
216 {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
217 {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
218 {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
219 {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
220 {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
221 {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
222 {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
223 {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
224 {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
225 {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
226 {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
227 {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
228 {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
229 {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
230 {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
231 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
232 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
233 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
234 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
235 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
236 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
237 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
238 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
239 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
240 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
702f42e8
ML		 241 {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false},
242 {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false},
243 {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
244 {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
245 {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
246 {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
247 {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
248 {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
249 {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true},
512bb890
BV		 250};
251
3086efdd 252SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
f4816ac6 253
fa85f376 254static void clear_helper(void *priv)
f4816ac6 255{
f4816ac6 256 struct dev_context *devc;
effb9dd1 257 unsigned int i;
f4816ac6 258
ba358ffd 259 devc = priv;
babab622
ML		 260 g_free(devc->data);
261 g_free(devc->buffer);
effb9dd1
AJ		 262 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
263 g_free(devc->coupling[i]);
fa85f376
UH		 264 g_free(devc->trigger_source);
265 g_free(devc->trigger_slope);
562b7ae5 266 g_free(devc->analog_groups);
562b7ae5 267 g_free(devc);
fa85f376 268}
f4816ac6 269
4f840ce9 270static int dev_clear(const struct sr_dev_driver *di)
fa85f376
UH		 271{
272 return std_dev_clear(di, clear_helper);
f4816ac6
ML		 273}
274
4f840ce9 275static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
f4816ac6 276{
f6beaac5 277 return std_init(sr_ctx, di, LOG_PREFIX);
f4816ac6
ML		 278}
279
9d3ae01b 280static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
f4816ac6 281{
cc9fd2d2
BV		 282 struct dev_context *devc;
283 struct sr_dev_inst *sdi;
ae1bc1cc 284 struct sr_scpi_hw_info *hw_info;
ba7dd8bb 285 struct sr_channel *ch;
8dd0b290 286 long n[3];
f6a0ac9f 287 unsigned int i;
bafd4890 288 const struct rigol_ds_model *model = NULL;
569d4dbd 289 gchar *channel_name, **version;
fb6e5ba8 290
ae1bc1cc 291 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
05238d28
ML		 292 sr_info("Couldn't get IDN response, retrying.");
293 sr_scpi_close(scpi);
294 sr_scpi_open(scpi);
295 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
296 sr_info("Couldn't get IDN response.");
297 return NULL;
298 }
ca55277c 299 }
e0b7d23c 300
ca55277c 301 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
34577da6 302 if (!g_ascii_strcasecmp(hw_info->manufacturer,
569d4dbd 303 supported_models[i].series->vendor->full_name) &&
10afee13 304 !strcmp(hw_info->model, supported_models[i].name)) {
bafd4890 305 model = &supported_models[i];
ca55277c 306 break;
fb6e5ba8 307 }
ca55277c 308 }
fb6e5ba8 309
0af636be 310 if (!model) {
ae1bc1cc 311 sr_scpi_hw_info_free(hw_info);
9d3ae01b 312 return NULL;
ca55277c 313 }
fb6e5ba8 314
aac29cc1 315 sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be
UH		 316 sdi->vendor = g_strdup(model->series->vendor->name);
317 sdi->model = g_strdup(model->name);
318 sdi->version = g_strdup(hw_info->firmware_version);
ae1bc1cc 319 sdi->conn = scpi;
4f840ce9 320 sdi->driver = &rigol_ds_driver_info;
ae1bc1cc 321 sdi->inst_type = SR_INST_SCPI;
b3fccc85 322 sdi->serial_num = g_strdup(hw_info->serial_number);
f57d8ffe 323 devc = g_malloc0(sizeof(struct dev_context));
cc9fd2d2 324 devc->limit_frames = 0;
bafd4890 325 devc->model = model;
569d4dbd 326 devc->format = model->series->format;
8dd0b290 327
569d4dbd
ML		 328 /* DS1000 models with firmware before 0.2.4 used the old data format. */
329 if (model->series == SERIES(DS1000)) {
8dd0b290
BV		 330 version = g_strsplit(hw_info->firmware_version, ".", 0);
331 do {
332 if (!version[0] || !version[1] || !version[2])
333 break;
334 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
335 break;
336 for (i = 0; i < 3; i++) {
337 if (sr_atol(version[i], &n[i]) != SR_OK)
338 break;
339 }
340 if (i != 3)
341 break;
de285cce
BV		 342 scpi->firmware_version = n[0] * 100 + n[1] * 10 + n[2];
343 if (scpi->firmware_version < 24) {
344 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
345 devc->format = FORMAT_RAW;
346 }
347 break;
0c5f2abc 348 } while (0);
8dd0b290
BV		 349 g_strfreev(version);
350 }
351
352 sr_scpi_hw_info_free(hw_info);
512bb890 353
562b7ae5
SA		 354 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
355 model->analog_channels);
356
821fbcad 357 for (i = 0; i < model->analog_channels; i++) {
eac0c613 358 channel_name = g_strdup_printf("CH%d", i + 1);
5e23fcab 359 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
562b7ae5
SA		 360
361 devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
362
363 devc->analog_groups[i]->name = channel_name;
364 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
660e398f 365 sdi->channel_groups = g_slist_append(sdi->channel_groups,
562b7ae5 366 devc->analog_groups[i]);
ca55277c 367 }
512bb890 368
bafd4890 369 if (devc->model->has_digital) {
16aca766 370 devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
562b7ae5 371
effb9dd1 372 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
eac0c613 373 channel_name = g_strdup_printf("D%d", i);
5e23fcab 374 ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
ca55277c 375 g_free(channel_name);
562b7ae5
SA		 376 devc->digital_group->channels = g_slist_append(
377 devc->digital_group->channels, ch);
512bb890 378 }
562b7ae5 379 devc->digital_group->name = g_strdup("LA");
660e398f 380 sdi->channel_groups = g_slist_append(sdi->channel_groups,
562b7ae5 381 devc->digital_group);
ca55277c 382 }
bafd4890
ML		 383
384 for (i = 0; i < NUM_TIMEBASE; i++) {
385 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
386 devc->timebases = &timebases[i];
569d4dbd 387 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
bafd4890
ML		 388 devc->num_timebases = &timebases[i] - devc->timebases + 1;
389 }
390
a95f142e
UH		 391 for (i = 0; i < NUM_VDIV; i++) {
392 if (!memcmp(&devc->model->series->min_vdiv,
393 &vdivs[i], sizeof(uint64_t[2]))) {
6ff1394e 394 devc->vdivs = &vdivs[i];
81b85663
AJ		 395 devc->num_vdivs = NUM_VDIV - i;
396 }
a95f142e 397 }
bafd4890 398
a95f142e
UH		 399 devc->buffer = g_malloc(ACQ_BUFFER_SIZE);
400 devc->data = g_malloc(ACQ_BUFFER_SIZE * sizeof(float));
babab622
ML		 401
402 devc->data_source = DATA_SOURCE_LIVE;
403
cc9fd2d2
BV		 404 sdi->priv = devc;
405
9d3ae01b 406 return sdi;
ca55277c 407}
512bb890 408
4f840ce9 409static GSList *scan(struct sr_dev_driver *di, GSList *options)
ca55277c 410{
41812aca 411 return sr_scpi_scan(di->context, options, probe_device);
f4816ac6
ML		 412}
413
4f840ce9 414static GSList *dev_list(const struct sr_dev_driver *di)
f4816ac6 415{
41812aca 416 return ((struct drv_context *)(di->context))->instances;
f4816ac6
ML		 417}
418
6078d2c9 419static int dev_open(struct sr_dev_inst *sdi)
f4816ac6 420{
e1b5b7e7 421 int ret;
ae1bc1cc 422 struct sr_scpi_dev_inst *scpi = sdi->conn;
9bd4c956 423
e1b5b7e7
UH		 424 if ((ret = sr_scpi_open(scpi)) < 0) {
425 sr_err("Failed to open SCPI device: %s.", sr_strerror(ret));
e0b7d23c 426 return SR_ERR;
e1b5b7e7 427 }
e0b7d23c 428
e1b5b7e7
UH		 429 if ((ret = rigol_ds_get_dev_cfg(sdi)) < 0) {
430 sr_err("Failed to get device config: %s.", sr_strerror(ret));
254dd102 431 return SR_ERR;
e1b5b7e7 432 }
f4816ac6 433
46a743c1 434 sdi->status = SR_ST_ACTIVE;
cc9fd2d2 435
f4816ac6
ML		 436 return SR_OK;
437}
438
6078d2c9 439static int dev_close(struct sr_dev_inst *sdi)
f4816ac6 440{
ae1bc1cc 441 struct sr_scpi_dev_inst *scpi;
22c19688 442 struct dev_context *devc;
ae1bc1cc 443
83dbd9f0
AJ		 444 if (sdi->status != SR_ST_ACTIVE)
445 return SR_ERR_DEV_CLOSED;
464d4936 446
ae1bc1cc 447 scpi = sdi->conn;
22c19688
ML		 448 devc = sdi->priv;
449
6e94eb41 450 if (devc->model->series->protocol == PROTOCOL_V2)
38354d9d 451 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
e0b7d23c 452
ae1bc1cc
ML		 453 if (scpi) {
454 if (sr_scpi_close(scpi) < 0)
455 return SR_ERR;
cc9fd2d2
BV		 456 sdi->status = SR_ST_INACTIVE;
457 }
f4816ac6
ML		 458
459 return SR_OK;
460}
461
4f840ce9 462static int cleanup(const struct sr_dev_driver *di)
f4816ac6 463{
4f840ce9 464 return dev_clear(di);
f4816ac6
ML		 465}
466
5415e602
ML		 467static int analog_frame_size(const struct sr_dev_inst *sdi)
468{
469 struct dev_context *devc = sdi->priv;
ba7dd8bb
UH		 470 struct sr_channel *ch;
471 int analog_channels = 0;
5415e602
ML		 472 GSList *l;
473
ba7dd8bb
UH		 474 for (l = sdi->channels; l; l = l->next) {
475 ch = l->data;
3f239f08 476 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
ba7dd8bb 477 analog_channels++;
569d4dbd
ML		 478 }
479
ba7dd8bb 480 if (analog_channels == 0)
824eb2ac
ML		 481 return 0;
482
569d4dbd
ML		 483 switch (devc->data_source) {
484 case DATA_SOURCE_LIVE:
485 return devc->model->series->live_samples;
486 case DATA_SOURCE_MEMORY:
ba7dd8bb 487 return devc->model->series->buffer_samples / analog_channels;
470140fc 488 default:
569d4dbd 489 return 0;
5415e602
ML		 490 }
491}
492
d22250a9
ML		 493static int digital_frame_size(const struct sr_dev_inst *sdi)
494{
495 struct dev_context *devc = sdi->priv;
496
569d4dbd
ML		 497 switch (devc->data_source) {
498 case DATA_SOURCE_LIVE:
499 return devc->model->series->live_samples * 2;
500 case DATA_SOURCE_MEMORY:
501 return devc->model->series->buffer_samples * 2;
d22250a9
ML		 502 default:
503 return 0;
504 }
505}
506
584560f1 507static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 508 const struct sr_channel_group *cg)
d62d7ad1 509{
e43fdd8d 510 struct dev_context *devc;
ba7dd8bb 511 struct sr_channel *ch;
2b0e4a46 512 const char *tmp_str;
c2b394d5 513 uint64_t samplerate;
2b0e4a46 514 int analog_channel = -1;
c33ff377 515 float smallest_diff = INFINITY;
2b0e4a46
AJ		 516 int idx = -1;
517 unsigned i;
d62d7ad1 518
e43fdd8d
BV		 519 if (!sdi || !(devc = sdi->priv))
520 return SR_ERR_ARG;
521
660e398f 522 /* If a channel group is specified, it must be a valid one. */
53b4680f 523 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
660e398f 524 sr_err("Invalid channel group specified.");
969edf63 525 return SR_ERR;
be60a9e4
BV		 526 }
527
53b4680f 528 if (cg) {
ba7dd8bb
UH		 529 ch = g_slist_nth_data(cg->channels, 0);
530 if (!ch)
2b0e4a46 531 return SR_ERR;
3f239f08 532 if (ch->type == SR_CHANNEL_ANALOG) {
ba7dd8bb 533 if (ch->name[2] < '1' || ch->name[2] > '4')
2b0e4a46 534 return SR_ERR;
ba7dd8bb 535 analog_channel = ch->name[2] - '1';
2b0e4a46
AJ		 536 }
537 }
538
584560f1 539 switch (key) {
bf622e6d 540 case SR_CONF_NUM_HDIV:
569d4dbd 541 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
d62d7ad1
BV		 542 break;
543 case SR_CONF_NUM_VDIV:
81b85663 544 *data = g_variant_new_int32(devc->num_vdivs);
f44f7e61 545 break;
babab622
ML		 546 case SR_CONF_DATA_SOURCE:
547 if (devc->data_source == DATA_SOURCE_LIVE)
548 *data = g_variant_new_string("Live");
549 else if (devc->data_source == DATA_SOURCE_MEMORY)
550 *data = g_variant_new_string("Memory");
551 else
552 *data = g_variant_new_string("Segmented");
553 break;
4914dd4b
ML		 554 case SR_CONF_SAMPLERATE:
555 if (devc->data_source == DATA_SOURCE_LIVE) {
c2b394d5 556 samplerate = analog_frame_size(sdi) /
569d4dbd 557 (devc->timebase * devc->model->series->num_horizontal_divs);
4914dd4b 558 *data = g_variant_new_uint64(samplerate);
c2b394d5 559 } else {
e1b5b7e7 560 sr_dbg("Unknown data source: %d.", devc->data_source);
4914dd4b 561 return SR_ERR_NA;
c2b394d5 562 }
4914dd4b 563 break;
2b0e4a46
AJ		 564 case SR_CONF_TRIGGER_SOURCE:
565 if (!strcmp(devc->trigger_source, "ACL"))
566 tmp_str = "AC Line";
567 else if (!strcmp(devc->trigger_source, "CHAN1"))
568 tmp_str = "CH1";
569 else if (!strcmp(devc->trigger_source, "CHAN2"))
570 tmp_str = "CH2";
571 else if (!strcmp(devc->trigger_source, "CHAN3"))
572 tmp_str = "CH3";
573 else if (!strcmp(devc->trigger_source, "CHAN4"))
574 tmp_str = "CH4";
575 else
576 tmp_str = devc->trigger_source;
577 *data = g_variant_new_string(tmp_str);
578 break;
5d336f11 579 case SR_CONF_TRIGGER_SLOPE:
e1b5b7e7 580 if (!strncmp(devc->trigger_slope, "POS", 3)) {
5d336f11 581 tmp_str = "r";
e1b5b7e7 582 } else if (!strncmp(devc->trigger_slope, "NEG", 3)) {
5d336f11 583 tmp_str = "f";
e1b5b7e7
UH		 584 } else {
585 sr_dbg("Unknown trigger slope: '%s'.", devc->trigger_slope);
5d336f11 586 return SR_ERR_NA;
e1b5b7e7 587 }
5d336f11
AJ		 588 *data = g_variant_new_string(tmp_str);
589 break;
2b0e4a46
AJ		 590 case SR_CONF_TIMEBASE:
591 for (i = 0; i < devc->num_timebases; i++) {
592 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
593 float diff = fabs(devc->timebase - tb);
594 if (diff < smallest_diff) {
595 smallest_diff = diff;
596 idx = i;
597 }
598 }
e1b5b7e7
UH		 599 if (idx < 0) {
600 sr_dbg("Negative timebase index: %d.", idx);
2b0e4a46 601 return SR_ERR_NA;
e1b5b7e7 602 }
2b0e4a46
AJ		 603 *data = g_variant_new("(tt)", devc->timebases[idx][0],
604 devc->timebases[idx][1]);
605 break;
606 case SR_CONF_VDIV:
e1b5b7e7
UH		 607 if (analog_channel < 0) {
608 sr_dbg("Negative analog channel: %d.", analog_channel);
2b0e4a46 609 return SR_ERR_NA;
e1b5b7e7 610 }
2b0e4a46
AJ		 611 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
612 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
613 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
614 if (diff < smallest_diff) {
615 smallest_diff = diff;
616 idx = i;
617 }
618 }
e1b5b7e7
UH		 619 if (idx < 0) {
620 sr_dbg("Negative vdiv index: %d.", idx);
2b0e4a46 621 return SR_ERR_NA;
e1b5b7e7 622 }
2b0e4a46
AJ		 623 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
624 break;
625 case SR_CONF_COUPLING:
e1b5b7e7
UH		 626 if (analog_channel < 0) {
627 sr_dbg("Negative analog channel: %d.", analog_channel);
2b0e4a46 628 return SR_ERR_NA;
e1b5b7e7 629 }
2b0e4a46
AJ		 630 *data = g_variant_new_string(devc->coupling[analog_channel]);
631 break;
d62d7ad1 632 default:
bd6fbf62 633 return SR_ERR_NA;
d62d7ad1
BV		 634 }
635
636 return SR_OK;
637}
638
584560f1 639static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
53b4680f 640 const struct sr_channel_group *cg)
f4816ac6 641{
29d957ce 642 struct dev_context *devc;
ca9b9f48 643 uint64_t p, q;
254dd102 644 double t_dbl;
f48e0249 645 unsigned int i, j;
254dd102
BV		 646 int ret;
647 const char *tmp_str;
889ef4a0 648 char buffer[16];
f4816ac6 649
e43fdd8d
BV		 650 if (!(devc = sdi->priv))
651 return SR_ERR_ARG;
29d957ce 652
e73ffd42
BV		 653 if (sdi->status != SR_ST_ACTIVE)
654 return SR_ERR_DEV_CLOSED;
f4816ac6 655
660e398f 656 /* If a channel group is specified, it must be a valid one. */
53b4680f 657 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
660e398f 658 sr_err("Invalid channel group specified.");
969edf63 659 return SR_ERR;
be60a9e4
BV		 660 }
661
f4816ac6 662 ret = SR_OK;
584560f1 663 switch (key) {
1953564a 664 case SR_CONF_LIMIT_FRAMES:
f6a0ac9f 665 devc->limit_frames = g_variant_get_uint64(data);
e0b7d23c 666 break;
1953564a 667 case SR_CONF_TRIGGER_SLOPE:
ca9b9f48
DE		 668 tmp_str = g_variant_get_string(data, NULL);
669
e1b5b7e7
UH		 670 if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r')) {
671 sr_err("Unknown trigger slope: '%s'.",
672 (tmp_str) ? tmp_str : "NULL");
ca9b9f48 673 return SR_ERR_ARG;
e1b5b7e7 674 }
ca9b9f48 675
254dd102 676 g_free(devc->trigger_slope);
ca9b9f48 677 devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG");
38354d9d 678 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
e0b7d23c 679 break;
1953564a 680 case SR_CONF_HORIZ_TRIGGERPOS:
254dd102 681 t_dbl = g_variant_get_double(data);
e1b5b7e7
UH		 682 if (t_dbl < 0.0 || t_dbl > 1.0) {
683 sr_err("Invalid horiz. trigger position: %g.", t_dbl);
254dd102 684 return SR_ERR;
e1b5b7e7 685 }
254dd102
BV		 686 devc->horiz_triggerpos = t_dbl;
687 /* We have the trigger offset as a percentage of the frame, but
688 * need to express this in seconds. */
bafd4890 689 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
889ef4a0 690 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
38354d9d 691 ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
e0b7d23c 692 break;
1953564a 693 case SR_CONF_TIMEBASE:
f6a0ac9f 694 g_variant_get(data, "(tt)", &p, &q);
bafd4890
ML		 695 for (i = 0; i < devc->num_timebases; i++) {
696 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
254dd102 697 devc->timebase = (float)p / q;
889ef4a0
AJ		 698 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
699 devc->timebase);
38354d9d 700 ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
f6a0ac9f
BV		 701 break;
702 }
703 }
e1b5b7e7
UH		 704 if (i == devc->num_timebases) {
705 sr_err("Invalid timebase index: %d.", i);
254dd102 706 ret = SR_ERR_ARG;
e1b5b7e7 707 }
e0b7d23c 708 break;
1953564a 709 case SR_CONF_TRIGGER_SOURCE:
f6a0ac9f 710 tmp_str = g_variant_get_string(data, NULL);
254dd102
BV		 711 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
712 if (!strcmp(trigger_sources[i], tmp_str)) {
713 g_free(devc->trigger_source);
714 devc->trigger_source = g_strdup(trigger_sources[i]);
715 if (!strcmp(devc->trigger_source, "AC Line"))
716 tmp_str = "ACL";
717 else if (!strcmp(devc->trigger_source, "CH1"))
718 tmp_str = "CHAN1";
719 else if (!strcmp(devc->trigger_source, "CH2"))
720 tmp_str = "CHAN2";
821fbcad
ML		 721 else if (!strcmp(devc->trigger_source, "CH3"))
722 tmp_str = "CHAN3";
723 else if (!strcmp(devc->trigger_source, "CH4"))
724 tmp_str = "CHAN4";
254dd102
BV		 725 else
726 tmp_str = (char *)devc->trigger_source;
38354d9d 727 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
254dd102
BV		 728 break;
729 }
4e108ace 730 }
e1b5b7e7
UH		 731 if (i == ARRAY_SIZE(trigger_sources)) {
732 sr_err("Invalid trigger source index: %d.", i);
254dd102 733 ret = SR_ERR_ARG;
e1b5b7e7 734 }
e0b7d23c 735 break;
1953564a 736 case SR_CONF_VDIV:
53b4680f 737 if (!cg) {
660e398f
UH		 738 sr_err("No channel group specified.");
739 return SR_ERR_CHANNEL_GROUP;
be60a9e4 740 }
f6a0ac9f 741 g_variant_get(data, "(tt)", &p, &q);
effb9dd1 742 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 743 if (cg == devc->analog_groups[i]) {
78bcc55a 744 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
f48e0249
ML		 745 if (vdivs[j][0] != p || vdivs[j][1] != q)
746 continue;
747 devc->vdiv[i] = (float)p / q;
889ef4a0
AJ		 748 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
749 devc->vdiv[i]);
38354d9d 750 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
889ef4a0 751 buffer);
f48e0249 752 }
e1b5b7e7 753 sr_err("Invalid vdiv index: %d.", j);
f48e0249
ML		 754 return SR_ERR_ARG;
755 }
e0b7d23c 756 }
e1b5b7e7 757 sr_dbg("Didn't set vdiv, unknown channel(group).");
f48e0249 758 return SR_ERR_NA;
1953564a 759 case SR_CONF_COUPLING:
53b4680f 760 if (!cg) {
660e398f
UH		 761 sr_err("No channel group specified.");
762 return SR_ERR_CHANNEL_GROUP;
78bcc55a 763 }
f6a0ac9f 764 tmp_str = g_variant_get_string(data, NULL);
effb9dd1 765 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 766 if (cg == devc->analog_groups[i]) {
78bcc55a
BV		 767 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
768 if (!strcmp(tmp_str, coupling[j])) {
f48e0249
ML		 769 g_free(devc->coupling[i]);
770 devc->coupling[i] = g_strdup(coupling[j]);
38354d9d 771 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
f48e0249
ML		 772 devc->coupling[i]);
773 }
774 }
e1b5b7e7 775 sr_err("Invalid coupling index: %d.", j);
f48e0249 776 return SR_ERR_ARG;
e0b7d23c
ML		 777 }
778 }
e1b5b7e7 779 sr_dbg("Didn't set coupling, unknown channel(group).");
f48e0249 780 return SR_ERR_NA;
babab622
ML		 781 case SR_CONF_DATA_SOURCE:
782 tmp_str = g_variant_get_string(data, NULL);
783 if (!strcmp(tmp_str, "Live"))
784 devc->data_source = DATA_SOURCE_LIVE;
569d4dbd
ML		 785 else if (devc->model->series->protocol >= PROTOCOL_V2
786 && !strcmp(tmp_str, "Memory"))
babab622 787 devc->data_source = DATA_SOURCE_MEMORY;
569d4dbd 788 else if (devc->model->series->protocol >= PROTOCOL_V3
babab622
ML		 789 && !strcmp(tmp_str, "Segmented"))
790 devc->data_source = DATA_SOURCE_SEGMENTED;
e1b5b7e7
UH		 791 else {
792 sr_err("Unknown data source: '%s'.", tmp_str);
babab622 793 return SR_ERR;
e1b5b7e7 794 }
babab622 795 break;
f4816ac6 796 default:
dcd438ee 797 return SR_ERR_NA;
f4816ac6
ML		 798 }
799
800 return ret;
801}
802
584560f1 803static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 804 const struct sr_channel_group *cg)
a1c743fc 805{
861c447b
BV		 806 GVariant *tuple, *rational[2];
807 GVariantBuilder gvb;
808 unsigned int i;
7cc1a550
ML		 809 struct dev_context *devc = NULL;
810
e43fdd8d 811 if (key == SR_CONF_SCAN_OPTIONS) {
584560f1 812 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
a0e0bb41 813 scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
e43fdd8d 814 return SR_OK;
0c5f2abc 815 } else if (key == SR_CONF_DEVICE_OPTIONS && !cg) {
584560f1 816 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 817 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
e43fdd8d
BV		 818 return SR_OK;
819 }
820
821 /* Every other option requires a valid device instance. */
822 if (!sdi || !(devc = sdi->priv))
823 return SR_ERR_ARG;
824
660e398f 825 /* If a channel group is specified, it must be a valid one. */
40c2c915
ML		 826 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
827 sr_err("Invalid channel group specified.");
828 return SR_ERR;
be60a9e4
BV		 829 }
830
e43fdd8d 831 switch (key) {
9a6517d1 832 case SR_CONF_DEVICE_OPTIONS:
53b4680f 833 if (!cg) {
660e398f
UH		 834 sr_err("No channel group specified.");
835 return SR_ERR_CHANNEL_GROUP;
be60a9e4 836 }
562b7ae5 837 if (cg == devc->digital_group) {
584560f1
BV		 838 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
839 NULL, 0, sizeof(uint32_t));
f48e0249
ML		 840 return SR_OK;
841 } else {
effb9dd1 842 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 843 if (cg == devc->analog_groups[i]) {
584560f1 844 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 845 analog_devopts, ARRAY_SIZE(analog_devopts), sizeof(uint32_t));
f48e0249
ML		 846 return SR_OK;
847 }
848 }
849 return SR_ERR_NA;
850 }
5f77dffc 851 break;
2a7b113d 852 case SR_CONF_COUPLING:
53b4680f 853 if (!cg) {
660e398f
UH		 854 sr_err("No channel group specified.");
855 return SR_ERR_CHANNEL_GROUP;
f48e0249 856 }
58f43369
BV		 857 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
858 break;
e4f2b2ad 859 case SR_CONF_VDIV:
7cc1a550
ML		 860 if (!devc)
861 /* Can't know this until we have the exact model. */
862 return SR_ERR_ARG;
53b4680f 863 if (!cg) {
660e398f
UH		 864 sr_err("No channel group specified.");
865 return SR_ERR_CHANNEL_GROUP;
861c447b 866 }
58f43369 867 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
81b85663 868 for (i = 0; i < devc->num_vdivs; i++) {
bafd4890
ML		 869 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
870 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
58f43369
BV		 871 tuple = g_variant_new_tuple(rational, 2);
872 g_variant_builder_add_value(&gvb, tuple);
873 }
874 *data = g_variant_builder_end(&gvb);
875 break;
41f5bd09 876 case SR_CONF_TIMEBASE:
7cc1a550
ML		 877 if (!devc)
878 /* Can't know this until we have the exact model. */
879 return SR_ERR_ARG;
a31b2ccb
AJ		 880 if (devc->num_timebases <= 0)
881 return SR_ERR_NA;
861c447b 882 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
bafd4890
ML		 883 for (i = 0; i < devc->num_timebases; i++) {
884 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
885 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
861c447b
BV		 886 tuple = g_variant_new_tuple(rational, 2);
887 g_variant_builder_add_value(&gvb, tuple);
888 }
889 *data = g_variant_builder_end(&gvb);
41f5bd09 890 break;
328bafab 891 case SR_CONF_TRIGGER_SOURCE:
7cc1a550
ML		 892 if (!devc)
893 /* Can't know this until we have the exact model. */
894 return SR_ERR_ARG;
f6a0ac9f 895 *data = g_variant_new_strv(trigger_sources,
bafd4890 896 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
328bafab 897 break;
5d336f11
AJ		 898 case SR_CONF_TRIGGER_SLOPE:
899 *data = g_variant_new_strv(trigger_slopes, ARRAY_SIZE(trigger_slopes));
900 break;
babab622
ML		 901 case SR_CONF_DATA_SOURCE:
902 if (!devc)
903 /* Can't know this until we have the exact model. */
904 return SR_ERR_ARG;
569d4dbd
ML		 905 switch (devc->model->series->protocol) {
906 case PROTOCOL_V1:
907 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
908 break;
909 case PROTOCOL_V2:
babab622 910 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
569d4dbd
ML		 911 break;
912 default:
913 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
914 break;
915 }
babab622 916 break;
a1c743fc 917 default:
bd6fbf62 918 return SR_ERR_NA;
a1c743fc
BV		 919 }
920
921 return SR_OK;
922}
923
254dd102 924static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
f4816ac6 925{
ae1bc1cc 926 struct sr_scpi_dev_inst *scpi;
29d957ce 927 struct dev_context *devc;
ba7dd8bb 928 struct sr_channel *ch;
f76c24f6 929 struct sr_datafeed_packet packet;
702f42e8 930 gboolean some_digital;
254dd102 931 GSList *l;
29d957ce 932
e73ffd42
BV		 933 if (sdi->status != SR_ST_ACTIVE)
934 return SR_ERR_DEV_CLOSED;
e0b7d23c 935
ae1bc1cc 936 scpi = sdi->conn;
29d957ce
UH		 937 devc = sdi->priv;
938
51b294cd
ML		 939 devc->num_frames = 0;
940
702f42e8 941 some_digital = FALSE;
ba7dd8bb
UH		 942 for (l = sdi->channels; l; l = l->next) {
943 ch = l->data;
944 sr_dbg("handling channel %s", ch->name);
3f239f08 945 if (ch->type == SR_CHANNEL_ANALOG) {
ba7dd8bb 946 if (ch->enabled)
702f42e8
ML		 947 devc->enabled_channels = g_slist_append(
948 devc->enabled_channels, ch);
ba7dd8bb 949 if (ch->enabled != devc->analog_channels[ch->index]) {
6bb192bc 950 /* Enabled channel is currently disabled, or vice versa. */
ba7dd8bb
UH		 951 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
952 ch->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 953 return SR_ERR;
ba7dd8bb 954 devc->analog_channels[ch->index] = ch->enabled;
6bb192bc 955 }
3f239f08 956 } else if (ch->type == SR_CHANNEL_LOGIC) {
702f42e8
ML		 957 /* Only one list entry for DS1000D series. All channels are retrieved
958 * together when this entry is processed. */
959 if (ch->enabled && (
960 devc->model->series->protocol > PROTOCOL_V2 ||
961 !some_digital))
962 devc->enabled_channels = g_slist_append(
963 devc->enabled_channels, ch);
ba7dd8bb 964 if (ch->enabled) {
702f42e8 965 some_digital = TRUE;
04e8e01e
ML		 966 /* Turn on LA module if currently off. */
967 if (!devc->la_enabled) {
702f42e8
ML		 968 if (rigol_ds_config_set(sdi,
969 devc->model->series->protocol >= PROTOCOL_V4 ?
970 ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
04e8e01e
ML		 971 return SR_ERR;
972 devc->la_enabled = TRUE;
973 }
974 }
ba7dd8bb 975 if (ch->enabled != devc->digital_channels[ch->index]) {
6bb192bc 976 /* Enabled channel is currently disabled, or vice versa. */
702f42e8
ML		 977 if (rigol_ds_config_set(sdi,
978 devc->model->series->protocol >= PROTOCOL_V4 ?
979 ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index,
ba7dd8bb 980 ch->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 981 return SR_ERR;
ba7dd8bb 982 devc->digital_channels[ch->index] = ch->enabled;
6bb192bc 983 }
254dd102
BV		 984 }
985 }
1fed20cb 986
702f42e8 987 if (!devc->enabled_channels)
254dd102 988 return SR_ERR;
e0b7d23c 989
ba7dd8bb 990 /* Turn off LA module if on and no digital channels selected. */
702f42e8
ML		 991 if (devc->la_enabled && !some_digital)
992 if (rigol_ds_config_set(sdi,
993 devc->model->series->protocol >= PROTOCOL_V4 ?
994 ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
04e8e01e
ML		 995 return SR_ERR;
996
e086b750
ML		 997 /* Set memory mode. */
998 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
999 sr_err("Data source 'Segmented' not yet supported");
1000 return SR_ERR;
1001 }
1002
1003 devc->analog_frame_size = analog_frame_size(sdi);
1004 devc->digital_frame_size = digital_frame_size(sdi);
1005
569d4dbd
ML		 1006 switch (devc->model->series->protocol) {
1007 case PROTOCOL_V2:
99af83b7 1008 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
e086b750 1009 return SR_ERR;
569d4dbd
ML		 1010 break;
1011 case PROTOCOL_V3:
e086b750
ML		 1012 /* Apparently for the DS2000 the memory
1013 * depth can only be set in Running state -
1014 * this matches the behaviour of the UI. */
38354d9d 1015 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1fed20cb 1016 return SR_ERR;
e086b750
ML		 1017 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
1018 devc->analog_frame_size) != SR_OK)
1019 return SR_ERR;
1020 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
1fed20cb 1021 return SR_ERR;
569d4dbd
ML		 1022 break;
1023 default:
1024 break;
1fed20cb
ML		 1025 }
1026
e086b750
ML		 1027 if (devc->data_source == DATA_SOURCE_LIVE)
1028 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1029 return SR_ERR;
1030
102f1239
BV		 1031 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
1032 rigol_ds_receive, (void *)sdi);
e0b7d23c 1033
29a27196 1034 std_session_send_df_header(cb_data, LOG_PREFIX);
e0b7d23c 1035
702f42e8 1036 devc->channel_entry = devc->enabled_channels;
821fbcad 1037
e086b750
ML		 1038 if (rigol_ds_capture_start(sdi) != SR_OK)
1039 return SR_ERR;
f4816ac6 1040
f76c24f6
ML		 1041 /* Start of first frame. */
1042 packet.type = SR_DF_FRAME_BEGIN;
1043 sr_session_send(cb_data, &packet);
1044
f4816ac6
ML		 1045 return SR_OK;
1046}
1047
254dd102 1048static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
f4816ac6 1049{
29d957ce 1050 struct dev_context *devc;
ae1bc1cc 1051 struct sr_scpi_dev_inst *scpi;
29d957ce 1052
f4816ac6
ML		 1053 (void)cb_data;
1054
29d957ce
UH		 1055 devc = sdi->priv;
1056
f4816ac6
ML		 1057 if (sdi->status != SR_ST_ACTIVE) {
1058 sr_err("Device inactive, can't stop acquisition.");
1059 return SR_ERR;
1060 }
1061
3be42bc2 1062 std_session_send_df_end(sdi, LOG_PREFIX);
b751cf7a 1063
702f42e8
ML		 1064 g_slist_free(devc->enabled_channels);
1065 devc->enabled_channels = NULL;
ae1bc1cc 1066 scpi = sdi->conn;
102f1239 1067 sr_scpi_source_remove(sdi->session, scpi);
f4816ac6
ML		 1068
1069 return SR_OK;
1070}
1071
3086efdd
ML		 1072SR_PRIV struct sr_dev_driver rigol_ds_driver_info = {
1073 .name = "rigol-ds",
1074 .longname = "Rigol DS",
f4816ac6 1075 .api_version = 1,
6078d2c9
UH		 1076 .init = init,
1077 .cleanup = cleanup,
1078 .scan = scan,
1079 .dev_list = dev_list,
3b412e3a 1080 .dev_clear = dev_clear,
d62d7ad1 1081 .config_get = config_get,
035a1078 1082 .config_set = config_set,
a1c743fc 1083 .config_list = config_list,
6078d2c9
UH		 1084 .dev_open = dev_open,
1085 .dev_close = dev_close,
254dd102
BV		 1086 .dev_acquisition_start = dev_acquisition_start,
1087 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 1088 .context = NULL,
f4816ac6 1089};
Hardware access and backend lib