[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"

/*
 * This should be larger than the FPGA bitstream image so that it'll get
 * uploaded in one big operation. There seem to be issues when uploading
 * it in chunks.
 */
#define FW_BUFSIZE (1024 * 1024)

#define FPGA_UPLOAD_DELAY (10 * 1000)

#define USB_TIMEOUT (3 * 1000)

SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
{
	struct sr_usb_dev_inst *usb;
	int ret;
	uint8_t cmd;

	usb = sdi->conn;

	cmd = (vth / 5.0) * 255;

	/* Send the control command. */
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), 3000);
	if (ret < 0) {
		sr_err("Unable to send VTH command: %s.",
		libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *name)
{
	uint64_t sum;
	struct sr_resource bitstream;
	struct drv_context *drvc;
	struct sr_usb_dev_inst *usb;
	unsigned char *buf;
	ssize_t chunksize;
	int transferred;
	int result, ret;
	uint8_t cmd[3];

	drvc = sdi->driver->context;
	usb = sdi->conn;

	sr_dbg("Uploading FPGA firmware '%s'.", name);

	result = sr_resource_open(drvc->sr_ctx, &bitstream,
			SR_RESOURCE_FIRMWARE, name);
	if (result != SR_OK)
		return result;

	/* Tell the device firmware is coming. */
	memset(cmd, 0, sizeof(cmd));
	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
			(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
		sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
		sr_resource_close(drvc->sr_ctx, &bitstream);
		return SR_ERR;
	}

	/* Give the FX2 time to get ready for FPGA firmware upload. */
	g_usleep(FPGA_UPLOAD_DELAY);

	buf = g_malloc(FW_BUFSIZE);
	sum = 0;
	result = SR_OK;
	while (1) {
		chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
				buf, FW_BUFSIZE);
		if (chunksize < 0)
			result = SR_ERR;
		if (chunksize <= 0)
			break;

		if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
				buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
			sr_err("Unable to configure FPGA firmware: %s.",
					libusb_error_name(ret));
			result = SR_ERR;
			break;
		}
		sum += transferred;
		sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
			sum, bitstream.size);

		if (transferred != chunksize) {
			sr_err("Short transfer while uploading FPGA firmware.");
			result = SR_ERR;
			break;
		}
	}
	g_free(buf);
	sr_resource_close(drvc->sr_ctx, &bitstream);

	if (result == SR_OK)
		sr_dbg("FPGA firmware upload done.");

	return result;
}

SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	devc = sdi->priv;
	mode.flags = DS_START_FLAGS_MODE_LA;
	mode.sample_delay_h = mode.sample_delay_l = 0;
	if (devc->sample_wide)
		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send start command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;
	struct dslogic_mode mode;
	int ret;

	mode.flags = DS_START_FLAGS_STOP;
	mode.sample_delay_h = mode.sample_delay_l = 0;

	usb = sdi->conn;
	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
			(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

/*
 * Get the session trigger and configure the FPGA structure
 * accordingly.
 */
static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	struct dslogic_fpga_config *cfg)
{
	struct sr_trigger *trigger;
	struct sr_trigger_stage *stage;
	struct sr_trigger_match *match;
	struct dev_context *devc;
	const GSList *l, *m;
	int channelbit, i = 0;
	uint16_t v16;

	devc = sdi->priv;

	cfg->trig_mask0[0] = 0xffff;
	cfg->trig_mask1[0] = 0xffff;

	cfg->trig_value0[0] = 0;
	cfg->trig_value1[0] = 0;

	cfg->trig_edge0[0] = 0;
	cfg->trig_edge1[0] = 0;

	cfg->trig_logic0[0] = 0;
	cfg->trig_logic1[0] = 0;

	cfg->trig_count0[0] = 0;
	cfg->trig_count1[0] = 0;

	cfg->trig_pos = 0;
	cfg->trig_sda = 0;
	cfg->trig_glb = 0;
	cfg->trig_adp = cfg->count - cfg->trig_pos - 1;

	for (i = 1; i < 16; i++) {
		cfg->trig_mask0[i] = 0xff;
		cfg->trig_mask1[i] = 0xff;
		cfg->trig_value0[i] = 0;
		cfg->trig_value1[i] = 0;
		cfg->trig_edge0[i] = 0;
		cfg->trig_edge1[i] = 0;
		cfg->trig_count0[i] = 0;
		cfg->trig_count1[i] = 0;
		cfg->trig_logic0[i] = 2;
		cfg->trig_logic1[i] = 2;
	}

	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	sr_dbg("pos: %d", cfg->trig_pos);

	sr_dbg("configuring trigger");

	if (!(trigger = sr_session_trigger_get(sdi->session))) {
		sr_dbg("No session trigger found");
		return SR_OK;
	}

	for (l = trigger->stages; l; l = l->next) {
		stage = l->data;
		for (m = stage->matches; m; m = m->next) {
			match = m->data;
			if (!match->channel->enabled)
				/* Ignore disabled channels with a trigger. */
				continue;
			channelbit = 1 << (match->channel->index);
			/* Simple trigger support (event). */
			if (match->match == SR_TRIGGER_ONE) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_ZERO) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
			} else if (match->match == SR_TRIGGER_FALLING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_RISING) {
				cfg->trig_mask0[0] &= ~channelbit;
				cfg->trig_mask1[0] &= ~channelbit;
				cfg->trig_value0[0] |= channelbit;
				cfg->trig_value1[0] |= channelbit;
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			} else if (match->match == SR_TRIGGER_EDGE) {
				cfg->trig_edge0[0] |= channelbit;
				cfg->trig_edge1[0] |= channelbit;
			}
		}
	}

	v16 = RL16(&cfg->mode);
	v16 |= 1 << 0;
	WL16(&cfg->mode, v16);

	return SR_OK;
}

SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_usb_dev_inst *usb;
	uint8_t c[3];
	struct dslogic_fpga_config cfg;
	uint16_t v16;
	uint32_t v32;
	int transferred, len, ret;

	sr_dbg("Configuring FPGA.");

	usb = sdi->conn;
	devc = sdi->priv;

	WL32(&cfg.sync, DS_CFG_START);
	WL16(&cfg.mode_header, DS_CFG_MODE);
	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	WL32(&cfg.count_header, DS_CFG_COUNT);
	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	WL32(&cfg.end_sync, DS_CFG_END);

	/* Pass in the length of a fixed-size struct. Really. */
	len = sizeof(struct dslogic_fpga_config) / 2;
	c[0] = len & 0xff;
	c[1] = (len >> 8) & 0xff;
	c[2] = (len >> 16) & 0xff;

	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
			LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
			c, 3, USB_TIMEOUT);
	if (ret < 0) {
		sr_err("Failed to send FPGA configure command: %s.",
			libusb_error_name(ret));
		return SR_ERR;
	}

	/*
	 * 15	1 = internal test mode
	 * 14	1 = external test mode
	 * 13	1 = loopback test mode
	 * 12	1 = stream mode
	 * 11	1 = serial trigger
	 * 8-10 unused
	 * 7	1 = analog mode
	 * 6	1 = samplerate 400MHz
	 * 5	1 = samplerate 200MHz or analog mode
	 * 4	0 = logic, 1 = dso or analog
	 * 3	1 = RLE encoding (enable for more than 16 Megasamples)
	 * 1-2	00 = internal clock,
	 * 	01 = external clock rising,
	 * 	11 = external clock falling
	 * 0	1 = trigger enabled
	 */
	v16 = 0x0000;
	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
		v16 = 1 << 15;
	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
		v16 = 1 << 14;
	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
		v16 = 1 << 13;
	if (devc->dslogic_continuous_mode)
		v16 |= 1 << 12;
	if (devc->dslogic_external_clock) {
		v16 |= 1 << 1;
		if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
			v16 |= 1 << 2;
	}
	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
		ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
		&& !devc->dslogic_continuous_mode) {
		/* Enable RLE for long captures.
		 * Without this, captured data present errors.
		 */
		v16 |= 1 << 3;
	}

	WL16(&cfg.mode, v16);
	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
	WL32(&cfg.divider, v32);
	WL32(&cfg.count, devc->limit_samples);

	dslogic_set_trigger(sdi, &cfg);

	len = sizeof(struct dslogic_fpga_config);
	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
	if (ret < 0 || transferred != len) {
		sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
		return SR_ERR;
	}

	return SR_OK;
}

static int to_bytes_per_ms(struct dev_context *devc)
{
	if (devc->cur_samplerate > SR_MHZ(100))
		return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);

	return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
}

static size_t get_buffer_size(struct dev_context *devc)
{
	size_t s;

	/*
	 * The buffer should be large enough to hold 10ms of data and
	 * a multiple of 512.
	 */
	s = 10 * to_bytes_per_ms(devc);
	// s = to_bytes_per_ms(devc->cur_samplerate);
	return (s + 511) & ~511;
}

SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
{
	unsigned int n;

	/* Total buffer size should be able to hold about 100ms of data. */
	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
	sr_info("New calculation: %d", n);

	if (n > NUM_SIMUL_TRANSFERS)
		return NUM_SIMUL_TRANSFERS;

	return n;
}
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6ec6c43b	21	#include <config.h>
b9d53092 BV	22	#include <math.h>
	23	#include <glib.h>
	24	#include <glib/gstdio.h>
	25	#include "protocol.h"
	26	#include "dslogic.h"
	27
3f0ff412 DA	28	/*
	29	* This should be larger than the FPGA bitstream image so that it'll get
	30	* uploaded in one big operation. There seem to be issues when uploading
	31	* it in chunks.
	32	*/
	33	#define FW_BUFSIZE (1024 * 1024)
1a46cc62	34
4df5739a UH	35	#define FPGA_UPLOAD_DELAY (10 * 1000)
	36
	37	#define USB_TIMEOUT (3 * 1000)
	38
3fc3fbe4 DA	39	SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
	40	{
	41	struct sr_usb_dev_inst *usb;
3fc3fbe4 DA	42	int ret;
	43	uint8_t cmd;
	44
9803346f UH	45	usb = sdi->conn;
	46
	47	cmd = (vth / 5.0) * 255;
	48
3fc3fbe4 DA	49	/* Send the control command. */
3fc3fbe4 DA	50	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
9803346f UH	51	LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
9803346f UH	52	(unsigned char *)&cmd, sizeof(cmd), 3000);
3fc3fbe4 DA	53	if (ret < 0) {
	54	sr_err("Unable to send VTH command: %s.",
	55	libusb_error_name(ret));
	56	return SR_ERR;
	57	}
	58
	59	return SR_OK;
	60	}
	61
8e2d6c9d DE	62	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
8e2d6c9d DE	63	const char *name)
b9d53092	64	{
8e2d6c9d DE	65	uint64_t sum;
	66	struct sr_resource bitstream;
	67	struct drv_context *drvc;
b9d53092	68	struct sr_usb_dev_inst *usb;
b9d53092	69	unsigned char *buf;
8e2d6c9d DE	70	ssize_t chunksize;
	71	int transferred;
	72	int result, ret;
d93c1470	73	uint8_t cmd[3];
b9d53092	74
8e2d6c9d	75	drvc = sdi->driver->context;
b9d53092	76	usb = sdi->conn;
8e2d6c9d DE	77
	78	sr_dbg("Uploading FPGA firmware '%s'.", name);
	79
	80	result = sr_resource_open(drvc->sr_ctx, &bitstream,
	81	SR_RESOURCE_FIRMWARE, name);
	82	if (result != SR_OK)
	83	return result;
b9d53092 BV	84
b9d53092 BV	85	/* Tell the device firmware is coming. */
d93c1470	86	memset(cmd, 0, sizeof(cmd));
b9d53092 BV	87	if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
b9d53092 BV	88	LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
d93c1470	89	(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
b9d53092	90	sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
8e2d6c9d	91	sr_resource_close(drvc->sr_ctx, &bitstream);
b9d53092 BV	92	return SR_ERR;
	93	}
	94
	95	/* Give the FX2 time to get ready for FPGA firmware upload. */
4df5739a	96	g_usleep(FPGA_UPLOAD_DELAY);
b9d53092	97
8e2d6c9d	98	buf = g_malloc(FW_BUFSIZE);
b9d53092 BV	99	sum = 0;
	100	result = SR_OK;
	101	while (1) {
8e2d6c9d DE	102	chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
	103	buf, FW_BUFSIZE);
	104	if (chunksize < 0)
	105	result = SR_ERR;
	106	if (chunksize <= 0)
b9d53092 BV	107	break;
	108
	109	if ((ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	110	buf, chunksize, &transferred, USB_TIMEOUT)) < 0) {
b9d53092 BV	111	sr_err("Unable to configure FPGA firmware: %s.",
	112	libusb_error_name(ret));
	113	result = SR_ERR;
	114	break;
	115	}
	116	sum += transferred;
8e2d6c9d DE	117	sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
8e2d6c9d DE	118	sum, bitstream.size);
b9d53092 BV	119
	120	if (transferred != chunksize) {
	121	sr_err("Short transfer while uploading FPGA firmware.");
	122	result = SR_ERR;
	123	break;
	124	}
	125	}
b9d53092	126	g_free(buf);
8e2d6c9d DE	127	sr_resource_close(drvc->sr_ctx, &bitstream);
8e2d6c9d DE	128
b9d53092 BV	129	if (result == SR_OK)
	130	sr_dbg("FPGA firmware upload done.");
	131
	132	return result;
	133	}
	134
8e2d6c9d	135	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	136	{
	137	struct dev_context *devc;
	138	struct sr_usb_dev_inst *usb;
	139	struct dslogic_mode mode;
	140	int ret;
	141
	142	devc = sdi->priv;
62974b23	143	mode.flags = DS_START_FLAGS_MODE_LA;
b9d53092 BV	144	mode.sample_delay_h = mode.sample_delay_l = 0;
	145	if (devc->sample_wide)
	146	mode.flags \|= DS_START_FLAGS_SAMPLE_WIDE;
	147
	148	usb = sdi->conn;
	149	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	150	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	151	(unsigned char *)&mode, sizeof(mode), USB_TIMEOUT);
b9d53092 BV	152	if (ret < 0) {
	153	sr_err("Failed to send start command: %s.", libusb_error_name(ret));
	154	return SR_ERR;
	155	}
	156
	157	return SR_OK;
	158	}
	159
8e2d6c9d	160	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
b9d53092 BV	161	{
	162	struct sr_usb_dev_inst *usb;
	163	struct dslogic_mode mode;
	164	int ret;
	165
	166	mode.flags = DS_START_FLAGS_STOP;
	167	mode.sample_delay_h = mode.sample_delay_l = 0;
	168
	169	usb = sdi->conn;
	170	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	171	LIBUSB_ENDPOINT_OUT, DS_CMD_START, 0x0000, 0x0000,
4df5739a	172	(unsigned char *)&mode, sizeof(struct dslogic_mode), USB_TIMEOUT);
b9d53092 BV	173	if (ret < 0) {
	174	sr_err("Failed to send stop command: %s.", libusb_error_name(ret));
	175	return SR_ERR;
	176	}
	177
	178	return SR_OK;
	179	}
	180
3db03efa DA	181	/*
	182	* Get the session trigger and configure the FPGA structure
	183	* accordingly.
	184	*/
	185	static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
	186	struct dslogic_fpga_config *cfg)
	187	{
	188	struct sr_trigger *trigger;
	189	struct sr_trigger_stage *stage;
	190	struct sr_trigger_match *match;
	191	struct dev_context *devc;
	192	const GSList l, m;
	193	int channelbit, i = 0;
	194	uint16_t v16;
	195
9803346f UH	196	devc = sdi->priv;
9803346f UH	197
3db03efa DA	198	cfg->trig_mask0[0] = 0xffff;
	199	cfg->trig_mask1[0] = 0xffff;
	200
	201	cfg->trig_value0[0] = 0;
	202	cfg->trig_value1[0] = 0;
	203
	204	cfg->trig_edge0[0] = 0;
	205	cfg->trig_edge1[0] = 0;
	206
	207	cfg->trig_logic0[0] = 0;
	208	cfg->trig_logic1[0] = 0;
	209
	210	cfg->trig_count0[0] = 0;
	211	cfg->trig_count1[0] = 0;
	212
4237fbca DA	213	cfg->trig_pos = 0;
	214	cfg->trig_sda = 0;
	215	cfg->trig_glb = 0;
	216	cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
	217
	218	for (i = 1; i < 16; i++) {
	219	cfg->trig_mask0[i] = 0xff;
	220	cfg->trig_mask1[i] = 0xff;
	221	cfg->trig_value0[i] = 0;
	222	cfg->trig_value1[i] = 0;
	223	cfg->trig_edge0[i] = 0;
	224	cfg->trig_edge1[i] = 0;
	225	cfg->trig_count0[i] = 0;
	226	cfg->trig_count1[i] = 0;
	227	cfg->trig_logic0[i] = 2;
	228	cfg->trig_logic1[i] = 2;
	229	}
	230
	231	cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
	232	sr_dbg("pos: %d", cfg->trig_pos);
	233
	234	sr_dbg("configuring trigger");
	235
9803346f	236	if (!(trigger = sr_session_trigger_get(sdi->session))) {
4237fbca	237	sr_dbg("No session trigger found");
3db03efa	238	return SR_OK;
4237fbca	239	}
3db03efa DA	240
	241	for (l = trigger->stages; l; l = l->next) {
	242	stage = l->data;
	243	for (m = stage->matches; m; m = m->next) {
	244	match = m->data;
	245	if (!match->channel->enabled)
	246	/* Ignore disabled channels with a trigger. */
	247	continue;
	248	channelbit = 1 << (match->channel->index);
3db03efa DA	249	/* Simple trigger support (event). */
	250	if (match->match == SR_TRIGGER_ONE) {
	251	cfg->trig_mask0[0] &= ~channelbit;
	252	cfg->trig_mask1[0] &= ~channelbit;
	253	cfg->trig_value0[0] \|= channelbit;
	254	cfg->trig_value1[0] \|= channelbit;
	255	} else if (match->match == SR_TRIGGER_ZERO) {
	256	cfg->trig_mask0[0] &= ~channelbit;
	257	cfg->trig_mask1[0] &= ~channelbit;
	258	} else if (match->match == SR_TRIGGER_FALLING) {
	259	cfg->trig_mask0[0] &= ~channelbit;
	260	cfg->trig_mask1[0] &= ~channelbit;
	261	cfg->trig_edge0[0] \|= channelbit;
	262	cfg->trig_edge1[0] \|= channelbit;
	263	} else if (match->match == SR_TRIGGER_RISING) {
	264	cfg->trig_mask0[0] &= ~channelbit;
	265	cfg->trig_mask1[0] &= ~channelbit;
	266	cfg->trig_value0[0] \|= channelbit;
	267	cfg->trig_value1[0] \|= channelbit;
	268	cfg->trig_edge0[0] \|= channelbit;
	269	cfg->trig_edge1[0] \|= channelbit;
9803346f	270	} else if (match->match == SR_TRIGGER_EDGE) {
3db03efa DA	271	cfg->trig_edge0[0] \|= channelbit;
	272	cfg->trig_edge1[0] \|= channelbit;
	273	}
	274	}
	275	}
9803346f	276
4237fbca DA	277	v16 = RL16(&cfg->mode);
	278	v16 \|= 1 << 0;
	279	WL16(&cfg->mode, v16);
9803346f	280
3db03efa DA	281	return SR_OK;
	282	}
	283
8e2d6c9d	284	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
b9d53092 BV	285	{
	286	struct dev_context *devc;
	287	struct sr_usb_dev_inst *usb;
	288	uint8_t c[3];
	289	struct dslogic_fpga_config cfg;
	290	uint16_t v16;
	291	uint32_t v32;
	292	int transferred, len, ret;
	293
	294	sr_dbg("Configuring FPGA.");
9803346f	295
b9d53092 BV	296	usb = sdi->conn;
	297	devc = sdi->priv;
	298
	299	WL32(&cfg.sync, DS_CFG_START);
	300	WL16(&cfg.mode_header, DS_CFG_MODE);
	301	WL32(&cfg.divider_header, DS_CFG_DIVIDER);
	302	WL32(&cfg.count_header, DS_CFG_COUNT);
	303	WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
	304	WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
	305	WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP);
	306	WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA);
	307	WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
	308	WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
	309	WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
	310	WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
	311	WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
	312	WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
	313	WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
	314	WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
	315	WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
	316	WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
	317	WL32(&cfg.end_sync, DS_CFG_END);
	318
	319	/* Pass in the length of a fixed-size struct. Really. */
	320	len = sizeof(struct dslogic_fpga_config) / 2;
	321	c[0] = len & 0xff;
	322	c[1] = (len >> 8) & 0xff;
	323	c[2] = (len >> 16) & 0xff;
	324
	325	ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR \|
	326	LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
4df5739a	327	c, 3, USB_TIMEOUT);
b9d53092	328	if (ret < 0) {
9803346f UH	329	sr_err("Failed to send FPGA configure command: %s.",
9803346f UH	330	libusb_error_name(ret));
b9d53092 BV	331	return SR_ERR;
	332	}
	333
	334	/*
	335	* 15 1 = internal test mode
	336	* 14 1 = external test mode
	337	* 13 1 = loopback test mode
3db03efa DA	338	* 12 1 = stream mode
3db03efa DA	339	* 11 1 = serial trigger
41dc2547	340	* 8-10 unused
b9d53092 BV	341	* 7 1 = analog mode
	342	* 6 1 = samplerate 400MHz
	343	* 5 1 = samplerate 200MHz or analog mode
	344	* 4 0 = logic, 1 = dso or analog
a9a9bfaa	345	* 3 1 = RLE encoding (enable for more than 16 Megasamples)
9803346f UH	346	* 1-2 00 = internal clock,
	347	* 01 = external clock rising,
	348	* 11 = external clock falling
b9d53092 BV	349	* 0 1 = trigger enabled
	350	*/
	351	v16 = 0x0000;
	352	if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
	353	v16 = 1 << 15;
	354	else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
	355	v16 = 1 << 14;
	356	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
	357	v16 = 1 << 13;
41dc2547 DA	358	if (devc->dslogic_continuous_mode)
41dc2547 DA	359	v16 \|= 1 << 12;
9803346f	360	if (devc->dslogic_external_clock) {
4237fbca	361	v16 \|= 1 << 1;
9803346f	362	if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
d9a58763	363	v16 \|= 1 << 2;
d9a58763	364	}
9803346f	365	if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
176d785d	366	ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
9803346f UH	367	&& !devc->dslogic_continuous_mode) {
	368	/* Enable RLE for long captures.
	369	* Without this, captured data present errors.
	370	*/
	371	v16 \|= 1 << 3;
a9a9bfaa	372	}
3fc3fbe4	373
b9d53092	374	WL16(&cfg.mode, v16);
a04b28ce	375	v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
b9d53092 BV	376	WL32(&cfg.divider, v32);
	377	WL32(&cfg.count, devc->limit_samples);
	378
3db03efa DA	379	dslogic_set_trigger(sdi, &cfg);
3db03efa DA	380
b9d53092 BV	381	len = sizeof(struct dslogic_fpga_config);
b9d53092 BV	382	ret = libusb_bulk_transfer(usb->devhdl, 2 \| LIBUSB_ENDPOINT_OUT,
4df5739a	383	(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
b9d53092 BV	384	if (ret < 0 \|\| transferred != len) {
	385	sr_err("Failed to send FPGA configuration: %s.", libusb_error_name(ret));
	386	return SR_ERR;
	387	}
	388
	389	return SR_OK;
	390	}
a04b28ce	391
9803346f UH	392	static int to_bytes_per_ms(struct dev_context *devc)
9803346f UH	393	{
a04b28ce	394	if (devc->cur_samplerate > SR_MHZ(100))
9803346f UH	395	return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
	396
	397	return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
a04b28ce DA	398	}
	399
	400	static size_t get_buffer_size(struct dev_context *devc)
	401	{
9803346f UH	402	size_t s;
	403
	404	/*
	405	* The buffer should be large enough to hold 10ms of data and
	406	* a multiple of 512.
	407	*/
	408	s = 10 * to_bytes_per_ms(devc);
	409	// s = to_bytes_per_ms(devc->cur_samplerate);
	410	return (s + 511) & ~511;
a04b28ce DA	411	}
a04b28ce DA	412
9803346f UH	413	SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
9803346f UH	414	{
a04b28ce	415	unsigned int n;
9803346f	416
a04b28ce	417	/* Total buffer size should be able to hold about 100ms of data. */
9803346f	418	n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
a04b28ce DA	419	sr_info("New calculation: %d", n);
	420
	421	if (n > NUM_SIMUL_TRANSFERS)
	422	return NUM_SIMUL_TRANSFERS;
	423
	424	return n;
	425	}