]> sigrok.org Git - libsigrok.git/blame - hardware/openbench-logic-sniffer/ols.c
ols: fix device discovery
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
fe1c50fb
BV
49#define SERIALCOMM "115200/8n1"
50
915f7cc8 51static const int hwcaps[] = {
5a2326a7
UH
52 SR_HWCAP_LOGIC_ANALYZER,
53 SR_HWCAP_SAMPLERATE,
54 SR_HWCAP_CAPTURE_RATIO,
55 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 56 SR_HWCAP_RLE,
43fc7885 57 0,
a1bb33af
UH
58};
59
d261dbbf 60/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 61static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
62 "0",
63 "1",
64 "2",
65 "3",
66 "4",
67 "5",
68 "6",
69 "7",
70 "8",
71 "9",
72 "10",
73 "11",
74 "12",
75 "13",
76 "14",
77 "15",
78 "16",
79 "17",
80 "18",
81 "19",
82 "20",
83 "21",
84 "22",
85 "23",
86 "24",
87 "25",
88 "26",
89 "27",
90 "28",
91 "29",
92 "30",
93 "31",
94 NULL,
95};
96
4fe9a6da 97/* default supported samplerates, can be overridden by device metadata */
a533743d 98static const struct sr_samplerates samplerates = {
c9140419 99 SR_HZ(10),
59df0c77 100 SR_MHZ(200),
c9140419
UH
101 SR_HZ(1),
102 NULL,
a1bb33af
UH
103};
104
e5e81856
BV
105SR_PRIV struct sr_dev_driver ols_driver_info;
106static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 107
6937bb75 108static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
109{
110 char buf[1];
111
b08024a8 112 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 113 buf[0] = command;
2119ab03 114 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 115 return SR_ERR;
a1bb33af 116
e46b8fb1 117 return SR_OK;
a1bb33af
UH
118}
119
6937bb75 120static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
121{
122 char buf[5];
123
b08024a8 124 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 125 buf[0] = command;
6937bb75
BV
126 buf[1] = (data & 0xff000000) >> 24;
127 buf[2] = (data & 0xff0000) >> 16;
128 buf[3] = (data & 0xff00) >> 8;
129 buf[4] = data & 0xff;
2119ab03 130 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 131 return SR_ERR;
a1bb33af 132
e46b8fb1 133 return SR_OK;
a1bb33af
UH
134}
135
014359e3 136static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 137{
014359e3 138 struct dev_context *devc;
1b79df2f
JH
139 const struct sr_probe *probe;
140 const GSList *l;
6937bb75 141 int probe_bit, stage, i;
a1bb33af
UH
142 char *tc;
143
014359e3
BV
144 devc = sdi->priv;
145
fefc4b85 146 devc->probe_mask = 0;
43fc7885 147 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
148 devc->trigger_mask[i] = 0;
149 devc->trigger_value[i] = 0;
a1bb33af
UH
150 }
151
fefc4b85 152 devc->num_stages = 0;
014359e3 153 for (l = sdi->probes; l; l = l->next) {
1b79df2f 154 probe = (const struct sr_probe *)l->data;
43fc7885 155 if (!probe->enabled)
6937bb75
BV
156 continue;
157
43fc7885
UH
158 /*
159 * Set up the probe mask for later configuration into the
160 * flag register.
161 */
b35c8293 162 probe_bit = 1 << (probe->index);
fefc4b85 163 devc->probe_mask |= probe_bit;
6937bb75 164
a803c0db 165 if (!probe->trigger)
6937bb75
BV
166 continue;
167
43fc7885 168 /* Configure trigger mask and value. */
6937bb75 169 stage = 0;
43fc7885 170 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 171 devc->trigger_mask[stage] |= probe_bit;
43fc7885 172 if (*tc == '1')
fefc4b85 173 devc->trigger_value[stage] |= probe_bit;
6937bb75 174 stage++;
43fc7885
UH
175 if (stage > 3)
176 /*
177 * TODO: Only supporting parallel mode, with
178 * up to 4 stages.
179 */
e46b8fb1 180 return SR_ERR;
a1bb33af 181 }
fefc4b85
BV
182 if (stage > devc->num_stages)
183 devc->num_stages = stage;
a1bb33af
UH
184 }
185
e46b8fb1 186 return SR_OK;
a1bb33af
UH
187}
188
a803c0db 189static uint32_t reverse16(uint32_t in)
6937bb75
BV
190{
191 uint32_t out;
192
a803c0db
BV
193 out = (in & 0xff) << 8;
194 out |= (in & 0xff00) >> 8;
195 out |= (in & 0xff0000) << 8;
196 out |= (in & 0xff000000) >> 8;
197
198 return out;
199}
200
201static uint32_t reverse32(uint32_t in)
202{
203 uint32_t out;
204
205 out = (in & 0xff) << 24;
206 out |= (in & 0xff00) << 8;
207 out |= (in & 0xff0000) >> 8;
208 out |= (in & 0xff000000) >> 24;
209
210 return out;
6937bb75
BV
211}
212
fefc4b85 213static struct dev_context *ols_dev_new(void)
4fe9a6da 214{
fefc4b85 215 struct dev_context *devc;
4fe9a6da 216
fefc4b85
BV
217 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
218 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
219 return NULL;
220 }
221
fefc4b85
BV
222 devc->trigger_at = -1;
223 devc->probe_mask = 0xffffffff;
224 devc->cur_samplerate = SR_KHZ(200);
225 devc->serial = NULL;
4fe9a6da 226
fefc4b85 227 return devc;
4fe9a6da
BV
228}
229
d68e2d1a 230static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 231{
d68e2d1a 232 struct sr_dev_inst *sdi;
fefc4b85 233 struct dev_context *devc;
10e5cbed
BV
234 struct sr_probe *probe;
235 uint32_t tmp_int, ui;
4fe9a6da 236 uint8_t key, type, token;
bb7ef793 237 GString *tmp_str, *devname, *version;
10e5cbed 238 guchar tmp_c;
4fe9a6da 239
d3683c42 240 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 241 sdi->driver = odi;
fefc4b85
BV
242 devc = ols_dev_new();
243 sdi->priv = devc;
4fe9a6da 244
bb7ef793 245 devname = g_string_new("");
4fe9a6da
BV
246 version = g_string_new("");
247
248 key = 0xff;
249 while (key) {
250 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
251 break;
252 type = key >> 5;
253 token = key & 0x1f;
254 switch (type) {
255 case 0:
256 /* NULL-terminated string */
257 tmp_str = g_string_new("");
258 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
259 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
260 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
261 key, tmp_str->str);
4fe9a6da
BV
262 switch (token) {
263 case 0x01:
264 /* Device name */
bb7ef793 265 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
266 break;
267 case 0x02:
268 /* FPGA firmware version */
269 if (version->len)
270 g_string_append(version, ", ");
271 g_string_append(version, "FPGA version ");
272 g_string_append(version, tmp_str->str);
273 break;
274 case 0x03:
275 /* Ancillary version */
276 if (version->len)
277 g_string_append(version, ", ");
278 g_string_append(version, "Ancillary version ");
279 g_string_append(version, tmp_str->str);
280 break;
281 default:
b08024a8
UH
282 sr_info("ols: unknown token 0x%.2x: '%s'",
283 token, tmp_str->str);
4fe9a6da
BV
284 break;
285 }
286 g_string_free(tmp_str, TRUE);
287 break;
288 case 1:
289 /* 32-bit unsigned integer */
290 if (serial_read(fd, &tmp_int, 4) != 4)
291 break;
292 tmp_int = reverse32(tmp_int);
b08024a8
UH
293 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
294 key, tmp_int);
4fe9a6da
BV
295 switch (token) {
296 case 0x00:
297 /* Number of usable probes */
10e5cbed
BV
298 for (ui = 0; ui < tmp_int; ui++) {
299 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
300 probe_names[ui])))
301 return 0;
302 sdi->probes = g_slist_append(sdi->probes, probe);
303 }
4fe9a6da
BV
304 break;
305 case 0x01:
306 /* Amount of sample memory available (bytes) */
fefc4b85 307 devc->max_samples = tmp_int;
4fe9a6da
BV
308 break;
309 case 0x02:
310 /* Amount of dynamic memory available (bytes) */
311 /* what is this for? */
312 break;
313 case 0x03:
314 /* Maximum sample rate (hz) */
fefc4b85 315 devc->max_samplerate = tmp_int;
4fe9a6da
BV
316 break;
317 case 0x04:
318 /* protocol version */
fefc4b85 319 devc->protocol_version = tmp_int;
4fe9a6da
BV
320 break;
321 default:
b08024a8
UH
322 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
323 token, tmp_int);
4fe9a6da
BV
324 break;
325 }
326 break;
327 case 2:
328 /* 8-bit unsigned integer */
329 if (serial_read(fd, &tmp_c, 1) != 1)
330 break;
b08024a8
UH
331 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
332 key, tmp_c);
4fe9a6da
BV
333 switch (token) {
334 case 0x00:
335 /* Number of usable probes */
10e5cbed
BV
336 for (ui = 0; ui < tmp_c; ui++) {
337 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
338 probe_names[ui])))
339 return 0;
340 sdi->probes = g_slist_append(sdi->probes, probe);
341 }
4fe9a6da
BV
342 break;
343 case 0x01:
344 /* protocol version */
fefc4b85 345 devc->protocol_version = tmp_c;
4fe9a6da
BV
346 break;
347 default:
b08024a8
UH
348 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
349 token, tmp_c);
4fe9a6da
BV
350 break;
351 }
352 break;
353 default:
354 /* unknown type */
355 break;
356 }
357 }
358
bb7ef793 359 sdi->model = devname->str;
4fe9a6da 360 sdi->version = version->str;
bb7ef793 361 g_string_free(devname, FALSE);
4fe9a6da
BV
362 g_string_free(version, FALSE);
363
364 return sdi;
365}
366
40dda2c3 367static int hw_init(void)
61136ea6 368{
fefc4b85 369 struct drv_context *drvc;
61136ea6 370
fefc4b85
BV
371 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
372 sr_err("ols: driver context malloc failed.");
886a52b6 373 return SR_ERR_MALLOC;
fefc4b85
BV
374 }
375 odi->priv = drvc;
61136ea6
BV
376
377 return SR_OK;
378}
379
10e5cbed 380static GSList *hw_scan(GSList *options)
a1bb33af 381{
a99e0d2a 382 struct sr_hwopt *opt;
d68e2d1a 383 struct sr_dev_inst *sdi;
fefc4b85
BV
384 struct drv_context *drvc;
385 struct dev_context *devc;
10e5cbed 386 struct sr_probe *probe;
a99e0d2a 387 GPollFD probefd;
fe1c50fb
BV
388 GSList *l, *devices;
389 int fd, ret, i;
390 const char *conn, *serialcomm;
a99e0d2a 391 char buf[8];
a1bb33af 392
10e5cbed 393 (void)options;
fefc4b85 394 drvc = odi->priv;
10e5cbed 395 devices = NULL;
c0a4b971 396
a99e0d2a
AG
397 conn = serialcomm = NULL;
398 for (l = options; l; l = l->next) {
399 opt = l->data;
400 switch (opt->hwopt) {
401 case SR_HWOPT_CONN:
402 conn = opt->value;
403 break;
404 case SR_HWOPT_SERIALCOMM:
405 serialcomm = opt->value;
406 break;
407 }
408 }
409 if (!conn) {
410 sr_err("ols: No serial port specified.");
411 return NULL;
c0a4b971
UH
412 }
413
fe1c50fb
BV
414 if (serialcomm == NULL)
415 serialcomm = g_strdup(SERIALCOMM);
c0a4b971 416
a99e0d2a
AG
417 /* The discovery procedure is like this: first send the Reset
418 * command (0x00) 5 times, since the device could be anywhere
419 * in a 5-byte command. Then send the ID command (0x02).
420 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
421 * have a match.
a99e0d2a
AG
422 */
423 sr_info("ols: probing %s .", conn);
424 fd = serial_open(conn, O_RDWR | O_NONBLOCK);
425 if (fd < 0) {
426 sr_err("ols: could not open port %s .", conn);
427 return NULL;
c0a4b971
UH
428 }
429
a99e0d2a
AG
430 serial_set_paramstr(fd, serialcomm);
431 ret = SR_OK;
432 for (i = 0; i < 5; i++) {
433 if ((ret = send_shortcommand(fd, CMD_RESET)) != SR_OK) {
a99e0d2a 434 sr_err("ols: port %s is not writable.", conn);
fe1c50fb 435 break;
a1bb33af
UH
436 }
437 }
a99e0d2a
AG
438 if (ret != SR_OK) {
439 serial_close(fd);
440 sr_err("ols: Could not use port %s. Quitting.", conn);
441 return NULL;
442 }
443 send_shortcommand(fd, CMD_ID);
a1bb33af 444
fe1c50fb 445 /* Wait 10ms for a response. */
5b15b41e 446 usleep(10000);
a1bb33af 447
fe1c50fb
BV
448 probefd.fd = fd;
449 probefd.events = G_IO_IN;
450 g_poll(&probefd, 1, 1);
4fe9a6da 451
a99e0d2a
AG
452 if (probefd.revents != G_IO_IN)
453 return NULL;
454 if (serial_read(probefd.fd, buf, 4) != 4)
455 return NULL;
456 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
457 return NULL;
4fe9a6da 458
fe1c50fb
BV
459 /* Definitely using the OLS protocol, check if it supports
460 * the metadata command.
a99e0d2a
AG
461 */
462 send_shortcommand(probefd.fd, CMD_METADATA);
a99e0d2a 463 if (g_poll(&probefd, 1, 10) > 0) {
fe1c50fb 464 /* Got metadata. */
a99e0d2a 465 sdi = get_metadata(fd);
fe1c50fb 466 sdi->index = 0;
a99e0d2a
AG
467 devc = sdi->priv;
468 } else {
fe1c50fb
BV
469 /* Not an OLS -- some other board that uses the sump protocol. */
470 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE,
a99e0d2a
AG
471 "Sump", "Logic Analyzer", "v1.0");
472 sdi->driver = odi;
473 devc = ols_dev_new();
474 for (i = 0; i < 32; i++) {
475 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
476 probe_names[i])))
477 return 0;
478 sdi->probes = g_slist_append(sdi->probes, probe);
a1bb33af 479 }
a99e0d2a 480 sdi->priv = devc;
4fe9a6da 481 }
fe1c50fb 482 devc->serial = sr_serial_dev_inst_new(conn, -1);
a99e0d2a
AG
483 drvc->instances = g_slist_append(drvc->instances, sdi);
484 devices = g_slist_append(devices, sdi);
485
fe1c50fb 486 serial_close(fd);
a1bb33af 487
10e5cbed 488 return devices;
a1bb33af
UH
489}
490
811deee4
BV
491static GSList *hw_dev_list(void)
492{
493 struct drv_context *drvc;
494
495 drvc = odi->priv;
496
497 return drvc->instances;
498}
499
25a0f108 500static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 501{
fefc4b85 502 struct dev_context *devc;
a1bb33af 503
fefc4b85 504 devc = sdi->priv;
69890f73 505
fefc4b85
BV
506 devc->serial->fd = serial_open(devc->serial->port, O_RDWR);
507 if (devc->serial->fd == -1)
e46b8fb1 508 return SR_ERR;
a1bb33af 509
5a2326a7 510 sdi->status = SR_ST_ACTIVE;
a1bb33af 511
e46b8fb1 512 return SR_OK;
a1bb33af
UH
513}
514
25a0f108 515static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 516{
fefc4b85 517 struct dev_context *devc;
a1bb33af 518
fefc4b85 519 devc = sdi->priv;
69890f73 520
fefc4b85
BV
521 if (devc->serial->fd != -1) {
522 serial_close(devc->serial->fd);
523 devc->serial->fd = -1;
5a2326a7 524 sdi->status = SR_ST_INACTIVE;
a1bb33af 525 }
697785d1
UH
526
527 return SR_OK;
a1bb33af
UH
528}
529
57ab7d9f 530static int hw_cleanup(void)
a1bb33af
UH
531{
532 GSList *l;
d68e2d1a 533 struct sr_dev_inst *sdi;
fefc4b85
BV
534 struct drv_context *drvc;
535 struct dev_context *devc;
57ab7d9f 536 int ret = SR_OK;
a1bb33af 537
fefc4b85
BV
538 if (!(drvc = odi->priv))
539 return SR_OK;
540
8722c31e 541 /* Properly close and free all devices. */
fefc4b85 542 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
543 if (!(sdi = l->data)) {
544 /* Log error, but continue cleaning up the rest. */
545 sr_err("ols: %s: sdi was NULL, continuing", __func__);
546 ret = SR_ERR_BUG;
547 continue;
548 }
fefc4b85 549 if (!(devc = sdi->priv)) {
57ab7d9f
UH
550 /* Log error, but continue cleaning up the rest. */
551 sr_err("ols: %s: sdi->priv was NULL, continuing",
552 __func__);
553 ret = SR_ERR_BUG;
554 continue;
555 }
556 /* TODO: Check for serial != NULL. */
fefc4b85
BV
557 if (devc->serial->fd != -1)
558 serial_close(devc->serial->fd);
559 sr_serial_dev_inst_free(devc->serial);
d3683c42 560 sr_dev_inst_free(sdi);
a1bb33af 561 }
fefc4b85
BV
562 g_slist_free(drvc->instances);
563 drvc->instances = NULL;
57ab7d9f
UH
564
565 return ret;
a1bb33af
UH
566}
567
dddfb3db
BV
568static int hw_info_get(int info_id, const void **data,
569 const struct sr_dev_inst *sdi)
a1bb33af 570{
fefc4b85 571 struct dev_context *devc;
a1bb33af 572
dddfb3db 573 switch (info_id) {
2ca4465b
BV
574 case SR_DI_HWCAPS:
575 *data = hwcaps;
576 break;
5a2326a7 577 case SR_DI_NUM_PROBES:
dddfb3db 578 *data = GINT_TO_POINTER(1);
a1bb33af 579 break;
464d12c7 580 case SR_DI_PROBE_NAMES:
dddfb3db 581 *data = probe_names;
464d12c7 582 break;
5a2326a7 583 case SR_DI_SAMPLERATES:
dddfb3db 584 *data = &samplerates;
a1bb33af 585 break;
5a2326a7 586 case SR_DI_TRIGGER_TYPES:
dddfb3db 587 *data = (char *)TRIGGER_TYPES;
a1bb33af 588 break;
5a2326a7 589 case SR_DI_CUR_SAMPLERATE:
dddfb3db 590 if (sdi) {
fefc4b85
BV
591 devc = sdi->priv;
592 *data = &devc->cur_samplerate;
dddfb3db
BV
593 } else
594 return SR_ERR;
a1bb33af 595 break;
dddfb3db
BV
596 default:
597 return SR_ERR_ARG;
a1bb33af
UH
598 }
599
dddfb3db 600 return SR_OK;
a1bb33af
UH
601}
602
6f4b1868 603static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 604{
fefc4b85 605 struct dev_context *devc;
a1bb33af 606
fefc4b85
BV
607 devc = sdi->priv;
608 if (devc->max_samplerate) {
609 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
610 return SR_ERR_SAMPLERATE;
611 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 612 return SR_ERR_SAMPLERATE;
a1bb33af 613
43fc7885 614 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
615 devc->flag_reg |= FLAG_DEMUX;
616 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 617 } else {
fefc4b85
BV
618 devc->flag_reg &= ~FLAG_DEMUX;
619 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 620 }
a1bb33af 621
7583b99d
GM
622 /* Calculate actual samplerate used and complain if it is different
623 * from the requested.
624 */
fefc4b85
BV
625 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
626 if (devc->flag_reg & FLAG_DEMUX)
627 devc->cur_samplerate *= 2;
628 if (devc->cur_samplerate != samplerate)
133a37bf 629 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 630 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 631
e46b8fb1 632 return SR_OK;
a1bb33af
UH
633}
634
6f4b1868
BV
635static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
636 const void *value)
a1bb33af 637{
fefc4b85 638 struct dev_context *devc;
a1bb33af 639 int ret;
1b79df2f 640 const uint64_t *tmp_u64;
a1bb33af 641
fefc4b85 642 devc = sdi->priv;
a1bb33af 643
5a2326a7 644 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 645 return SR_ERR;
a1bb33af 646
ffedd0bf 647 switch (hwcap) {
5a2326a7 648 case SR_HWCAP_SAMPLERATE:
1b79df2f 649 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 650 break;
5a2326a7 651 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 652 tmp_u64 = value;
574ce498 653 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 654 return SR_ERR;
fefc4b85 655 if (*tmp_u64 > devc->max_samples)
133a37bf 656 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
657 devc->limit_samples = *tmp_u64;
658 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 659 ret = SR_OK;
a803c0db 660 break;
5a2326a7 661 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
662 devc->capture_ratio = *(const uint64_t *)value;
663 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
664 devc->capture_ratio = 0;
e46b8fb1 665 ret = SR_ERR;
43fc7885 666 } else
e46b8fb1 667 ret = SR_OK;
a803c0db 668 break;
3a4d09c0 669 case SR_HWCAP_RLE:
4d436e71 670 if (GPOINTER_TO_INT(value)) {
3a4d09c0 671 sr_info("ols: enabling RLE");
fefc4b85 672 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
673 }
674 ret = SR_OK;
675 break;
a803c0db 676 default:
e46b8fb1 677 ret = SR_ERR;
43fc7885 678 }
a1bb33af
UH
679
680 return ret;
681}
682
26bf9d56
BV
683static void abort_acquisition(const struct sr_dev_inst *sdi)
684{
685 struct sr_datafeed_packet packet;
686 struct dev_context *devc;
687
688 devc = sdi->priv;
689 sr_source_remove(devc->serial->fd);
690
691 /* Terminate session */
692 packet.type = SR_DF_END;
693 sr_session_send(sdi, &packet);
694
695}
696
697
698
1f9813eb 699static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 700{
b9c735a2 701 struct sr_datafeed_packet packet;
9c939c51 702 struct sr_datafeed_logic logic;
d68e2d1a 703 struct sr_dev_inst *sdi;
fefc4b85
BV
704 struct drv_context *drvc;
705 struct dev_context *devc;
4fe9a6da 706 GSList *l;
3a4d09c0
GM
707 int num_channels, offset, i, j;
708 unsigned char byte;
a1bb33af 709
fefc4b85
BV
710 drvc = odi->priv;
711
712 /* Find this device's devc struct by its fd. */
713 devc = NULL;
714 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 715 sdi = l->data;
fefc4b85
BV
716 devc = sdi->priv;
717 if (devc->serial->fd == fd) {
4fe9a6da
BV
718 break;
719 }
fefc4b85 720 devc = NULL;
4fe9a6da 721 }
fefc4b85 722 if (!devc)
ea9cfed7 723 /* Shouldn't happen. */
4fe9a6da
BV
724 return TRUE;
725
fefc4b85 726 if (devc->num_transfers++ == 0) {
43fc7885
UH
727 /*
728 * First time round, means the device started sending data,
729 * and will not stop until done. If it stops sending for
730 * longer than it takes to send a byte, that means it's
731 * finished. We'll double that to 30ms to be sure...
a1bb33af 732 */
6f1be0a2 733 sr_source_remove(fd);
1f9813eb 734 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
886a52b6 735 /* TODO: Check malloc return code. */
fefc4b85
BV
736 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
737 if (!devc->raw_sample_buf) {
738 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
739 __func__);
740 return FALSE;
741 }
a803c0db 742 /* fill with 1010... for debugging */
fefc4b85 743 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
744 }
745
6937bb75 746 num_channels = 0;
43fc7885 747 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 748 if ((devc->flag_reg & i) == 0)
6937bb75 749 num_channels++;
43fc7885 750 }
6937bb75 751
3a4d09c0 752 if (revents == G_IO_IN) {
2119ab03 753 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
754 return FALSE;
755
baf1d714 756 /* Ignore it if we've read enough. */
fefc4b85 757 if (devc->num_samples >= devc->limit_samples)
baf1d714 758 return TRUE;
3a4d09c0 759
fefc4b85 760 devc->sample[devc->num_bytes++] = byte;
b08024a8 761 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 762 if (devc->num_bytes == num_channels) {
43fc7885 763 /* Got a full sample. */
b08024a8 764 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
765 devc->num_bytes * 2, *(int *)devc->sample);
766 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
767 /*
768 * In RLE mode -1 should never come in as a
769 * sample, because bit 31 is the "count" flag.
43fc7885 770 */
fefc4b85
BV
771 if (devc->sample[devc->num_bytes - 1] & 0x80) {
772 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
773 /*
774 * FIXME: This will only work on
775 * little-endian systems.
a1bb33af 776 */
fefc4b85
BV
777 devc->rle_count = *(int *)(devc->sample);
778 sr_dbg("ols: RLE count = %d", devc->rle_count);
779 devc->num_bytes = 0;
3a4d09c0 780 return TRUE;
baf1d714 781 }
3a4d09c0 782 }
fefc4b85
BV
783 devc->num_samples += devc->rle_count + 1;
784 if (devc->num_samples > devc->limit_samples) {
baf1d714 785 /* Save us from overrunning the buffer. */
fefc4b85
BV
786 devc->rle_count -= devc->num_samples - devc->limit_samples;
787 devc->num_samples = devc->limit_samples;
a1bb33af
UH
788 }
789
43fc7885
UH
790 if (num_channels < 4) {
791 /*
792 * Some channel groups may have been turned
793 * off, to speed up transfer between the
794 * hardware and the PC. Expand that here before
795 * submitting it over the session bus --
796 * whatever is listening on the bus will be
797 * expecting a full 32-bit sample, based on
798 * the number of probes.
6937bb75
BV
799 */
800 j = 0;
fefc4b85 801 memset(devc->tmp_sample, 0, 4);
43fc7885 802 for (i = 0; i < 4; i++) {
fefc4b85 803 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
804 /*
805 * This channel group was
806 * enabled, copy from received
807 * sample.
808 */
fefc4b85 809 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
810 }
811 }
fefc4b85
BV
812 memcpy(devc->sample, devc->tmp_sample, 4);
813 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
814 }
815
a803c0db
BV
816 /* the OLS sends its sample buffer backwards.
817 * store it in reverse order here, so we can dump
818 * this on the session bus later.
819 */
fefc4b85
BV
820 offset = (devc->limit_samples - devc->num_samples) * 4;
821 for (i = 0; i <= devc->rle_count; i++) {
822 memcpy(devc->raw_sample_buf + offset + (i * 4),
823 devc->sample, 4);
baf1d714 824 }
fefc4b85
BV
825 memset(devc->sample, 0, 4);
826 devc->num_bytes = 0;
827 devc->rle_count = 0;
a1bb33af 828 }
43fc7885
UH
829 } else {
830 /*
831 * This is the main loop telling us a timeout was reached, or
832 * we've acquired all the samples we asked for -- we're done.
a803c0db 833 * Send the (properly-ordered) buffer to the frontend.
43fc7885 834 */
fefc4b85 835 if (devc->trigger_at != -1) {
a803c0db
BV
836 /* a trigger was set up, so we need to tell the frontend
837 * about it.
838 */
fefc4b85 839 if (devc->trigger_at > 0) {
a803c0db 840 /* there are pre-trigger samples, send those first */
5a2326a7 841 packet.type = SR_DF_LOGIC;
9c939c51 842 packet.payload = &logic;
fefc4b85 843 logic.length = devc->trigger_at * 4;
9c939c51 844 logic.unitsize = 4;
fefc4b85
BV
845 logic.data = devc->raw_sample_buf +
846 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 847 sr_session_send(cb_data, &packet);
a803c0db
BV
848 }
849
9c939c51 850 /* send the trigger */
5a2326a7 851 packet.type = SR_DF_TRIGGER;
1f9813eb 852 sr_session_send(cb_data, &packet);
a803c0db 853
9c939c51 854 /* send post-trigger samples */
5a2326a7 855 packet.type = SR_DF_LOGIC;
9c939c51 856 packet.payload = &logic;
fefc4b85 857 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 858 logic.unitsize = 4;
fefc4b85
BV
859 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
860 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 861 sr_session_send(cb_data, &packet);
a803c0db 862 } else {
9c939c51 863 /* no trigger was used */
5a2326a7 864 packet.type = SR_DF_LOGIC;
9c939c51 865 packet.payload = &logic;
fefc4b85 866 logic.length = devc->num_samples * 4;
9c939c51 867 logic.unitsize = 4;
fefc4b85
BV
868 logic.data = devc->raw_sample_buf +
869 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 870 sr_session_send(cb_data, &packet);
a803c0db 871 }
fefc4b85 872 g_free(devc->raw_sample_buf);
a803c0db 873
06d64eb8 874 serial_flush(fd);
d02a535e 875 serial_close(fd);
26bf9d56
BV
876
877 abort_acquisition(sdi);
a1bb33af
UH
878 }
879
880 return TRUE;
881}
882
5d9ed643
BV
883static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
884 void *cb_data)
a1bb33af 885{
b9c735a2
UH
886 struct sr_datafeed_packet *packet;
887 struct sr_datafeed_header *header;
f366e86c 888 struct sr_datafeed_meta_logic meta;
fefc4b85 889 struct dev_context *devc;
a803c0db 890 uint32_t trigger_config[4];
a1bb33af 891 uint32_t data;
6937bb75
BV
892 uint16_t readcount, delaycount;
893 uint8_t changrp_mask;
22130421 894 int num_channels;
4fe9a6da 895 int i;
a1bb33af 896
fefc4b85 897 devc = sdi->priv;
a1bb33af 898
5a2326a7 899 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 900 return SR_ERR;
a1bb33af 901
014359e3
BV
902 if (configure_probes(sdi) != SR_OK) {
903 sr_err("ols: failed to configured probes");
904 return SR_ERR;
905 }
906
22130421
GM
907 /*
908 * Enable/disable channel groups in the flag register according to the
baf1d714 909 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
910 * to limit readcount.
911 */
912 changrp_mask = 0;
913 num_channels = 0;
914 for (i = 0; i < 4; i++) {
fefc4b85 915 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
916 changrp_mask |= (1 << i);
917 num_channels++;
918 }
919 }
920
baf1d714
UH
921 /*
922 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
923 * buffer.
924 */
fefc4b85 925 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
926
927 memset(trigger_config, 0, 16);
fefc4b85
BV
928 trigger_config[devc->num_stages - 1] |= 0x08;
929 if (devc->trigger_mask[0]) {
930 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
931 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 932
fefc4b85
BV
933 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
934 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 935 return SR_ERR;
fefc4b85
BV
936 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
937 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 938 return SR_ERR;
fefc4b85 939 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
940 trigger_config[0]) != SR_OK)
941 return SR_ERR;
6937bb75 942
fefc4b85
BV
943 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_1,
944 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 945 return SR_ERR;
fefc4b85
BV
946 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_1,
947 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 948 return SR_ERR;
fefc4b85 949 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
950 trigger_config[1]) != SR_OK)
951 return SR_ERR;
6937bb75 952
fefc4b85
BV
953 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_2,
954 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 955 return SR_ERR;
fefc4b85
BV
956 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_2,
957 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 958 return SR_ERR;
fefc4b85 959 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
960 trigger_config[2]) != SR_OK)
961 return SR_ERR;
a803c0db 962
fefc4b85
BV
963 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_3,
964 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 965 return SR_ERR;
fefc4b85
BV
966 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_3,
967 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 968 return SR_ERR;
fefc4b85 969 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
970 trigger_config[3]) != SR_OK)
971 return SR_ERR;
6937bb75 972 } else {
fefc4b85
BV
973 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
974 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 975 return SR_ERR;
fefc4b85
BV
976 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
977 devc->trigger_value[0]) != SR_OK)
e46b8fb1 978 return SR_ERR;
fefc4b85 979 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
980 0x00000008) != SR_OK)
981 return SR_ERR;
a803c0db 982 delaycount = readcount;
6937bb75 983 }
a1bb33af 984
b08024a8 985 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
986 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
987 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
988 if (send_longcommand(devc->serial->fd, CMD_SET_DIVIDER,
989 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 990 return SR_ERR;
a1bb33af 991
43fc7885 992 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
993 data = ((readcount - 1) & 0xffff) << 16;
994 data |= (delaycount - 1) & 0xffff;
fefc4b85 995 if (send_longcommand(devc->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 996 return SR_ERR;
a1bb33af 997
43fc7885 998 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
999 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1000 devc->flag_reg |= FLAG_FILTER;
1001 devc->rle_count = 0;
1002 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
1003 if (send_longcommand(devc->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 1004 return SR_ERR;
a1bb33af 1005
43fc7885 1006 /* Start acquisition on the device. */
fefc4b85 1007 if (send_shortcommand(devc->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 1008 return SR_ERR;
a1bb33af 1009
fefc4b85 1010 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1011 cb_data);
a1bb33af 1012
b53738ba
UH
1013 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1014 sr_err("ols: %s: packet malloc failed", __func__);
1015 return SR_ERR_MALLOC;
1016 }
1017
1018 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1019 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1020 g_free(packet);
b53738ba
UH
1021 return SR_ERR_MALLOC;
1022 }
1023
43fc7885 1024 /* Send header packet to the session bus. */
5a2326a7 1025 packet->type = SR_DF_HEADER;
43fc7885 1026 packet->payload = (unsigned char *)header;
a1bb33af
UH
1027 header->feed_version = 1;
1028 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1029 sr_session_send(cb_data, packet);
1030
1031 /* Send metadata about the SR_DF_LOGIC packets to come. */
1032 packet->type = SR_DF_META_LOGIC;
1033 packet->payload = &meta;
fefc4b85 1034 meta.samplerate = devc->cur_samplerate;
f366e86c 1035 meta.num_probes = NUM_PROBES;
3cd3a20b 1036 sr_session_send(cb_data, packet);
c0a4b971 1037
a1bb33af
UH
1038 g_free(header);
1039 g_free(packet);
1040
e46b8fb1 1041 return SR_OK;
a1bb33af
UH
1042}
1043
3cd3a20b 1044/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
69b07d14 1045static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
a1bb33af 1046{
17e1afcb 1047 /* Avoid compiler warnings. */
26bf9d56 1048 (void)cb_data;
afc8e4de 1049
26bf9d56 1050 abort_acquisition(sdi);
3010f21c
UH
1051
1052 return SR_OK;
a1bb33af
UH
1053}
1054
c09f0b57 1055SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1056 .name = "ols",
1057 .longname = "Openbench Logic Sniffer",
1058 .api_version = 1,
1059 .init = hw_init,
1060 .cleanup = hw_cleanup,
61136ea6 1061 .scan = hw_scan,
811deee4
BV
1062 .dev_list = hw_dev_list,
1063 .dev_clear = hw_cleanup,
e7eb703f
UH
1064 .dev_open = hw_dev_open,
1065 .dev_close = hw_dev_close,
dddfb3db 1066 .info_get = hw_info_get,
a9a245b4 1067 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1068 .dev_acquisition_start = hw_dev_acquisition_start,
1069 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1070 .priv = NULL,
a1bb33af 1071};