[sigrok-dumps.git] / uart / lin / lin_generated / README

-------------------------------------------------------------------------------
LIN bus traffic
-------------------------------------------------------------------------------

Synthetically generated LIN bus traffic from a debugging session.

UART settings on LIN are always 19200/8n1, lsb-first; LIN protocol version: 2.


Logic analyzer setup
--------------------

The logic analyzer used was a DreamSourceLab DSLogic Plus (various samplerates):

  Probe       LIN
  ---------------
  0           LIN-Bus


single_frame.sr
---------------

This shows one valid single LIN frame consisting of a header and a response
of 2 data bytes.

PID is 0xC1 -> ID: 0x01 Parity: 3
Data 1: 0x11
Data 2: 0x11
Checksum: 0x1C


lin_burst.sr
------------

10 valid LIN frames consisting of a header and a response of 3 data bytes each.
The frames are all sent at the highest possible load UART can handle.

PID is 0xA3 -> ID: 0x23 Parity: 2
Data 1: 0x11
Data 2: 0x22
Checksum: 0x29


lin_malformed.sr
----------------

Contains complete and incomplete LIN frames. Sometimes the PID is not sent
after the sync. The goal is testing the correct behaviour of the state machine
on protocol violations.


lin_malformed2.sr
-----------------

Same as lin_malformed.sr but more traffic.


lin_stress.sr
-------------

Different messages with different lengths and a changing bus load.
No protocol violations.
Commit	Line	Data
ce8fbd59	1	-------------------------------------------------------------------------------
	2	LIN bus traffic
	3	-------------------------------------------------------------------------------
	4
	5	Synthetically generated LIN bus traffic from a debugging session.
	6
	7	UART settings on LIN are always 19200/8n1, lsb-first; LIN protocol version: 2.
	8
	9
	10	Logic analyzer setup
	11	--------------------
	12
	13	The logic analyzer used was a DreamSourceLab DSLogic Plus (various samplerates):
	14
	15	Probe LIN
	16	---------------
	17	0 LIN-Bus
	18
	19
	20	single_frame.sr
	21	---------------
	22
	23	This shows one valid single LIN frame consisting of a header and a response
	24	of 2 data bytes.
	25
	26	PID is 0xC1 -> ID: 0x01 Parity: 3
	27	Data 1: 0x11
	28	Data 2: 0x11
	29	Checksum: 0x1C
	30
	31
	32	lin_burst.sr
	33	------------
	34
	35	10 valid LIN frames consisting of a header and a response of 3 data bytes each.
	36	The frames are all sent at the highest possible load UART can handle.
	37
	38	PID is 0xA3 -> ID: 0x23 Parity: 2
	39	Data 1: 0x11
	40	Data 2: 0x22
	41	Checksum: 0x29
	42
	43
	44	lin_malformed.sr
	45	----------------
	46
	47	Contains complete and incomplete LIN frames. Sometimes the PID is not sent
	48	after the sync. The goal is testing the correct behaviour of the state machine
	49	on protocol violations.
	50
	51
	52	lin_malformed2.sr
	53	-----------------
	54
	55	Same as lin_malformed.sr but more traffic.
	56
	57
	58	lin_stress.sr
	59	-------------
	60
	61	Different messages with different lengths and a changing bus load.
	62	No protocol violations.