enc28j60: Adds trace and README master
authorJiahao Li <reg@ljh.me>
Wed, 20 Feb 2019 23:12:56 +0000 (18:12 -0500)
committerUwe Hermann <uwe@hermann-uwe.de>
Tue, 14 May 2019 22:32:32 +0000 (00:32 +0200)
spi/enc28j60/README [new file with mode: 0644]
spi/enc28j60/enc28j60-init-and-ping.sr [new file with mode: 0644]

diff --git a/spi/enc28j60/README b/spi/enc28j60/README
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+-------------------------------------------------------------------------------
+Microchip ENC28J60
+-------------------------------------------------------------------------------
+
+This is an example capture of the Microchip ENC28J60 SPI Ethernet chip.
+
+Details:
+http://ww1.microchip.com/downloads/en/DeviceDoc/39662e.pdf
+
+
+enc28j60-init-and-ping.sr
+-------------------------
+
+Capture contains the following 3 stages:
+
+1) Initialization phase where control registers are written.
+2) Polling phase that waits for the Ethernet link to be up.
+3) Two round-trips of ping packets (each consists of 1 RX of ICMP Echo Request
+   packet and 1 TX of ICMP Echo Reply packet).
+
+The chip was driven by a custom STM32F446 board running custom bare-metal
+firmware.
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a DSLogic Plus (at 50MHz, with SPI clock at 16MHz):
+
+  Probe       ENC28J60
+  --------------------
+  0           CS#
+  1           MISO
+  2           CLK
+  3           MOSI
diff --git a/spi/enc28j60/enc28j60-init-and-ping.sr b/spi/enc28j60/enc28j60-init-and-ping.sr
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Binary files /dev/null and b/spi/enc28j60/enc28j60-init-and-ping.sr differ