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204b1629 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
204b1629 | 3 | * |
3ba56876 | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
204b1629 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
204b1629 UH |
8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
3ba56876 | 23 | #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H |
24 | #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
25 | ||
26 | #include <stdint.h> | |
4154a516 | 27 | #include <stdlib.h> |
3ba56876 | 28 | #include <glib.h> |
29 | #include <ftdi.h> | |
30 | #include <string.h> | |
31 | #include <libsigrok/libsigrok.h> | |
32 | #include "libsigrok-internal.h" | |
28a35d8a | 33 | |
f272d7dd UH |
34 | #define LOG_PREFIX "asix-sigma" |
35 | ||
53a939ab GS |
36 | /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ |
37 | #define ASIX_WITH_OMEGA 0 | |
38 | ||
39 | #define USB_VENDOR_ASIX 0xa600 | |
40 | #define USB_PRODUCT_SIGMA 0xa000 | |
41 | #define USB_PRODUCT_OMEGA 0xa004 | |
42 | ||
43 | enum asix_device_type { | |
44 | ASIX_TYPE_NONE, | |
45 | ASIX_TYPE_SIGMA, | |
46 | ASIX_TYPE_OMEGA, | |
47 | }; | |
3ba56876 | 48 | |
3f5f5484 GS |
49 | /* Mask to isolate one bit, mask to span a number of bits. */ |
50 | #define BIT(pos) (1UL << (pos)) | |
51 | #define BITS_MASK(count) ((1UL << (count)) - 1) | |
52 | ||
53 | #define HI4(b) (((b) >> 4) & 0x0f) | |
54 | #define LO4(b) (((b) >> 0) & 0x0f) | |
55 | ||
7c41c420 GS |
56 | /* |
57 | * FPGA commands are 8bits wide. The upper nibble is a command opcode, | |
58 | * the lower nibble can carry operand values. 8bit register addresses | |
59 | * and 8bit data values get communicated in two steps. | |
60 | */ | |
61 | ||
62 | /* Register access. */ | |
63 | #define REG_ADDR_LOW (0x0 << 4) | |
64 | #define REG_ADDR_HIGH (0x1 << 4) | |
65 | #define REG_DATA_LOW (0x2 << 4) | |
66 | #define REG_DATA_HIGH_WRITE (0x3 << 4) | |
67 | #define REG_READ_ADDR (0x4 << 4) | |
3f5f5484 GS |
68 | #define REG_ADDR_ADJUST BIT(0) /* Auto adjust register address. */ |
69 | #define REG_ADDR_DOWN BIT(1) /* 1 decrement, 0 increment. */ | |
7c41c420 GS |
70 | #define REG_ADDR_INC (REG_ADDR_ADJUST) |
71 | #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) | |
72 | ||
73 | /* Sample memory access. */ | |
74 | #define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ | |
75 | #define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ | |
76 | #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ | |
77 | #define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ | |
78 | #define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ | |
79 | #define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) | |
80 | ||
81 | /* | |
82 | * Registers at a specific address can have different meanings depending | |
83 | * on whether data is read or written. This is why direction is part of | |
84 | * the programming language identifiers. | |
85 | * | |
86 | * The vendor documentation suggests that in addition to the first 16 | |
87 | * register addresses which implement the logic analyzer's feature set, | |
88 | * there are 240 more registers in the 16 to 255 address range which | |
89 | * are available to applications and plugin features. Can libsigrok's | |
90 | * asix-sigma driver store configuration data there, to avoid expensive | |
91 | * operations (think: firmware re-load). | |
53c8a99c GS |
92 | * |
93 | * Update: The documentation may be incorrect, or the FPGA netlist may | |
94 | * be incomplete. Experiments show that registers beyond 0x0f can get | |
95 | * accessed, USB communication passes, but data bytes are always 0xff. | |
96 | * Are several firmware versions around, and the documentation does not | |
97 | * match the one that ships with sigrok? | |
7c41c420 GS |
98 | */ |
99 | ||
fefa1800 | 100 | enum sigma_write_register { |
28a35d8a | 101 | WRITE_CLOCK_SELECT = 0, |
9fb4c632 GS |
102 | WRITE_TRIGGER_SELECT = 1, |
103 | WRITE_TRIGGER_SELECT2 = 2, | |
28a35d8a HE |
104 | WRITE_MODE = 3, |
105 | WRITE_MEMROW = 4, | |
106 | WRITE_POST_TRIGGER = 5, | |
107 | WRITE_TRIGGER_OPTION = 6, | |
108 | WRITE_PIN_VIEW = 7, | |
9fb4c632 | 109 | /* Unassigned register locations. */ |
fefa1800 | 110 | WRITE_TEST = 15, |
53c8a99c GS |
111 | /* Reserved for plugin features. */ |
112 | REG_PLUGIN_START = 16, | |
113 | REG_PLUGIN_STOP = 256, | |
28a35d8a HE |
114 | }; |
115 | ||
fefa1800 | 116 | enum sigma_read_register { |
28a35d8a HE |
117 | READ_ID = 0, |
118 | READ_TRIGGER_POS_LOW = 1, | |
119 | READ_TRIGGER_POS_HIGH = 2, | |
120 | READ_TRIGGER_POS_UP = 3, | |
121 | READ_STOP_POS_LOW = 4, | |
122 | READ_STOP_POS_HIGH = 5, | |
123 | READ_STOP_POS_UP = 6, | |
124 | READ_MODE = 7, | |
125 | READ_PIN_CHANGE_LOW = 8, | |
126 | READ_PIN_CHANGE_HIGH = 9, | |
127 | READ_BLOCK_LAST_TS_LOW = 10, | |
128 | READ_BLOCK_LAST_TS_HIGH = 11, | |
9fb4c632 GS |
129 | READ_BLOCK_TS_OVERRUN = 12, |
130 | READ_PIN_VIEW = 13, | |
131 | /* Unassigned register location. */ | |
fefa1800 | 132 | READ_TEST = 15, |
53c8a99c | 133 | /* Reserved for plugin features. See above. */ |
28a35d8a HE |
134 | }; |
135 | ||
3f5f5484 GS |
136 | #define CLKSEL_CLKSEL8 BIT(0) |
137 | #define CLKSEL_PINMASK BITS_MASK(4) | |
138 | #define CLKSEL_RISING BIT(4) | |
139 | #define CLKSEL_FALLING BIT(5) | |
2d8a5089 | 140 | |
3f5f5484 | 141 | #define TRGSEL_SELINC_MASK BITS_MASK(2) |
0f017b7d | 142 | #define TRGSEL_SELINC_SHIFT 0 |
3f5f5484 | 143 | #define TRGSEL_SELRES_MASK BITS_MASK(2) |
0f017b7d | 144 | #define TRGSEL_SELRES_SHIFT 2 |
3f5f5484 | 145 | #define TRGSEL_SELA_MASK BITS_MASK(2) |
0f017b7d | 146 | #define TRGSEL_SELA_SHIFT 4 |
3f5f5484 | 147 | #define TRGSEL_SELB_MASK BITS_MASK(2) |
0f017b7d | 148 | #define TRGSEL_SELB_SHIFT 6 |
3f5f5484 | 149 | #define TRGSEL_SELC_MASK BITS_MASK(2) |
16791da9 | 150 | #define TRGSEL_SELC_SHIFT 8 |
3f5f5484 | 151 | #define TRGSEL_SELPRESC_MASK BITS_MASK(4) |
16791da9 GS |
152 | #define TRGSEL_SELPRESC_SHIFT 12 |
153 | ||
154 | enum trgsel_selcode_t { | |
155 | TRGSEL_SELCODE_LEVEL = 0, | |
156 | TRGSEL_SELCODE_FALL = 1, | |
157 | TRGSEL_SELCODE_RISE = 2, | |
158 | TRGSEL_SELCODE_EVENT = 3, | |
159 | TRGSEL_SELCODE_NEVER = 3, | |
160 | }; | |
0f017b7d | 161 | |
3f5f5484 GS |
162 | #define TRGSEL2_PINS_MASK BITS_MASK(3) |
163 | #define TRGSEL2_PINPOL_RISE BIT(3) | |
164 | #define TRGSEL2_LUT_ADDR_MASK BITS_MASK(4) | |
165 | #define TRGSEL2_LUT_WRITE BIT(4) | |
166 | #define TRGSEL2_RESET BIT(5) | |
167 | #define TRGSEL2_LEDSEL0 BIT(6) | |
168 | #define TRGSEL2_LEDSEL1 BIT(7) | |
57bbf56b | 169 | |
22f64ed8 | 170 | /* WRITE_MODE register fields. */ |
3f5f5484 GS |
171 | #define WMR_SDRAMWRITEEN BIT(0) |
172 | #define WMR_SDRAMREADEN BIT(1) | |
173 | #define WMR_TRGRES BIT(2) | |
174 | #define WMR_TRGEN BIT(3) | |
175 | #define WMR_FORCESTOP BIT(4) | |
176 | #define WMR_TRGSW BIT(5) | |
22f64ed8 | 177 | /* not used: bit position 6 */ |
3f5f5484 | 178 | #define WMR_SDRAMINIT BIT(7) |
22f64ed8 GS |
179 | |
180 | /* READ_MODE register fields. */ | |
3f5f5484 GS |
181 | #define RMR_SDRAMWRITEEN BIT(0) |
182 | #define RMR_SDRAMREADEN BIT(1) | |
22f64ed8 | 183 | /* not used: bit position 2 */ |
3f5f5484 GS |
184 | #define RMR_TRGEN BIT(3) |
185 | #define RMR_ROUND BIT(4) | |
186 | #define RMR_TRIGGERED BIT(5) | |
187 | #define RMR_POSTTRIGGERED BIT(6) | |
22f64ed8 GS |
188 | /* not used: bit position 7 */ |
189 | ||
a53b8e4d GS |
190 | /* |
191 | * Trigger options. First and second write are similar, but _some_ | |
192 | * positions change their meaning. | |
193 | */ | |
3f5f5484 GS |
194 | #define TRGOPT_TRGIEN BIT(7) |
195 | #define TRGOPT_TRGOEN BIT(6) | |
196 | #define TRGOPT_TRGOINEN BIT(5) /* 1st write */ | |
a53b8e4d | 197 | #define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */ |
3f5f5484 | 198 | #define TRGOPT_TRGOEVNTEN BIT(4) /* 1st write */ |
a53b8e4d | 199 | #define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */ |
3f5f5484 | 200 | #define TRGOPT_TRGOOUTEN BIT(3) /* 1st write */ |
a53b8e4d | 201 | #define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */ |
3f5f5484 GS |
202 | #define TRGOPT_TRGOUTR_OUT BIT(1) |
203 | #define TRGOPT_TRGOUTR_EN BIT(0) | |
a53b8e4d GS |
204 | #define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN) |
205 | ||
fd830beb | 206 | /* |
5b1d15ef GS |
207 | * Layout of the sample data DRAM, which will be downloaded to the PC: |
208 | * | |
209 | * Sigma memory is organized in 32K rows. Each row contains 64 clusters. | |
2c33b092 GS |
210 | * Each cluster contains a timestamp (16bit) and 7 events (16bits each). |
211 | * Events contain 16 bits of sample data (potentially taken at multiple | |
212 | * sample points, see below). | |
213 | * | |
214 | * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The | |
215 | * size of a memory row is 1024 bytes. Assuming x16 organization of the | |
216 | * memory array, address specs (sample count, trigger position) are kept | |
217 | * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit | |
218 | * refer to the "event" within the row. Because there is one timestamp for | |
219 | * seven events each, one memory row can hold up to 64x7 == 448 events. | |
5b1d15ef GS |
220 | * |
221 | * Sample data is represented in 16bit quantities. The first sample in | |
222 | * the cluster corresponds to the cluster's timestamp. Each next sample | |
223 | * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is | |
224 | * one sample period, according to the samplerate). In the absence of | |
225 | * pin level changes, no data is provided (RLE compression). A cluster | |
226 | * is enforced for each 64K ticks of the timestamp, to reliably handle | |
2c33b092 | 227 | * rollover and determine the next timestamp of the next cluster. |
5b1d15ef | 228 | * |
2c33b092 GS |
229 | * For samplerates up to 50MHz, an event directly translates to one set |
230 | * of sample data at a single sample point, spanning up to 16 channels. | |
5b1d15ef GS |
231 | * For samplerates of 100MHz, there is one 16 bit entity for each 20ns |
232 | * period (50MHz rate). The 16 bit memory contains 2 samples of up to | |
233 | * 8 channels. Bits of multiple samples are interleaved. For samplerates | |
234 | * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, | |
235 | * each 5ns apart. | |
fd830beb MV |
236 | */ |
237 | ||
2c33b092 GS |
238 | #define ROW_COUNT 32768 |
239 | #define ROW_LENGTH_BYTES 1024 | |
240 | #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) | |
241 | #define ROW_SHIFT 9 /* log2 of u16 count */ | |
3f5f5484 | 242 | #define ROW_MASK BITS_MASK(ROW_SHIFT) |
2c33b092 GS |
243 | #define EVENTS_PER_CLUSTER 7 |
244 | #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) | |
245 | #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) | |
fd830beb | 246 | |
fd830beb | 247 | struct sigma_dram_line { |
2c33b092 | 248 | struct sigma_dram_cluster { |
2a62a9c4 GS |
249 | uint16_t timestamp; |
250 | uint16_t samples[EVENTS_PER_CLUSTER]; | |
2c33b092 | 251 | } cluster[CLUSTERS_PER_ROW]; |
fd830beb MV |
252 | }; |
253 | ||
57bbf56b HE |
254 | /* The effect of all these are still a bit unclear. */ |
255 | struct triggerinout { | |
8bd4dc87 GS |
256 | gboolean trgout_resistor_enable, trgout_resistor_pullup; |
257 | gboolean trgout_resistor_enable2, trgout_resistor_pullup2; | |
258 | gboolean trgout_bytrigger, trgout_byevent, trgout_bytriggerin; | |
259 | gboolean trgout_long, trgout_pin; /* 1ms pulse, 1k resistor */ | |
260 | gboolean trgin_negate, trgout_enable, trgin_enable; | |
57bbf56b HE |
261 | }; |
262 | ||
ee492173 | 263 | struct triggerlut { |
ee492173 | 264 | uint16_t m0d[4], m1d[4], m2d[4]; |
16791da9 | 265 | uint16_t m3q, m3s, m4; |
ee492173 | 266 | struct { |
8bd4dc87 GS |
267 | uint8_t selpresc; |
268 | uint8_t sela, selb, selc; | |
269 | uint8_t selinc, selres; | |
270 | uint16_t cmpa, cmpb; | |
ee492173 HE |
271 | } params; |
272 | }; | |
273 | ||
c53d793f HE |
274 | /* Trigger configuration */ |
275 | struct sigma_trigger { | |
ba7dd8bb | 276 | /* Only two channels can be used in mask. */ |
a42aec7f HE |
277 | uint16_t risingmask; |
278 | uint16_t fallingmask; | |
c53d793f HE |
279 | |
280 | /* Simple trigger support (<= 50 MHz). */ | |
281 | uint16_t simplemask; | |
282 | uint16_t simplevalue; | |
283 | ||
c53d793f HE |
284 | /* TODO: Advanced trigger support (boolean expressions). */ |
285 | }; | |
286 | ||
287 | /* Events for trigger operation. */ | |
288 | enum triggerop { | |
289 | OP_LEVEL = 1, | |
290 | OP_NOT, | |
291 | OP_RISE, | |
292 | OP_FALL, | |
293 | OP_RISEFALL, | |
294 | OP_NOTRISE, | |
295 | OP_NOTFALL, | |
296 | OP_NOTRISEFALL, | |
297 | }; | |
298 | ||
299 | /* Logical functions for trigger operation. */ | |
300 | enum triggerfunc { | |
301 | FUNC_AND = 1, | |
302 | FUNC_NAND, | |
303 | FUNC_OR, | |
304 | FUNC_NOR, | |
305 | FUNC_XOR, | |
306 | FUNC_NXOR, | |
307 | }; | |
308 | ||
80e717b3 GS |
309 | enum sigma_firmware_idx { |
310 | SIGMA_FW_NONE, | |
311 | SIGMA_FW_50MHZ, | |
312 | SIGMA_FW_100MHZ, | |
313 | SIGMA_FW_200MHZ, | |
314 | SIGMA_FW_SYNC, | |
315 | SIGMA_FW_FREQ, | |
316 | }; | |
317 | ||
2d8a5089 GS |
318 | enum ext_clock_edge_t { |
319 | SIGMA_CLOCK_EDGE_RISING, | |
320 | SIGMA_CLOCK_EDGE_FALLING, | |
321 | SIGMA_CLOCK_EDGE_EITHER, | |
322 | }; | |
323 | ||
98b43eb3 GS |
324 | struct submit_buffer; |
325 | ||
0e1357e8 | 326 | struct dev_context { |
53a939ab GS |
327 | struct { |
328 | uint16_t vid, pid; | |
329 | uint32_t serno; | |
330 | uint16_t prefix; | |
331 | enum asix_device_type type; | |
332 | } id; | |
eabf9ca6 | 333 | char **channel_names; |
7fe1f91f GS |
334 | struct { |
335 | struct ftdi_context ctx; | |
336 | gboolean is_open, must_close; | |
337 | } ftdi; | |
2d8a5089 GS |
338 | struct { |
339 | uint64_t samplerate; | |
340 | gboolean use_ext_clock; | |
341 | size_t clock_pin; | |
342 | enum ext_clock_edge_t clock_edge; | |
343 | } clock; | |
156b6879 GS |
344 | struct { |
345 | /* | |
346 | * User specified configuration values, in contrast to | |
347 | * internal arrangement of acquisition, and submission | |
348 | * to the session feed. | |
349 | */ | |
350 | struct sr_sw_limits config; | |
351 | struct sr_sw_limits acquire; | |
352 | struct sr_sw_limits submit; | |
353 | } limit; | |
80e717b3 | 354 | enum sigma_firmware_idx firmware_idx; |
ee5cef71 | 355 | struct sigma_sample_interp { |
de4c29fa GS |
356 | /* Interpretation of sample memory. */ |
357 | size_t num_channels; | |
358 | size_t samples_per_event; | |
ee5cef71 GS |
359 | struct { |
360 | uint16_t ts; | |
361 | uint16_t sample; | |
362 | } last; | |
16a5d5ac GS |
363 | struct sigma_location { |
364 | size_t raw, line, cluster, event; | |
66d1790c | 365 | } start, stop, trig, iter, trig_arm; |
ee5cef71 | 366 | struct { |
16a5d5ac | 367 | size_t lines_total, lines_done; |
ee5cef71 | 368 | size_t lines_per_read; /* USB transfer limit */ |
16a5d5ac | 369 | size_t lines_rcvd; |
ee5cef71 GS |
370 | struct sigma_dram_line *rcvd_lines; |
371 | struct sigma_dram_line *curr_line; | |
372 | } fetch; | |
66d1790c GS |
373 | struct { |
374 | gboolean armed; | |
375 | gboolean matched; | |
376 | size_t evt_remain; | |
377 | } trig_chk; | |
de4c29fa | 378 | } interp; |
efad7ccc | 379 | uint64_t capture_ratio; |
99965709 | 380 | struct sigma_trigger trigger; |
3d9373af | 381 | gboolean use_triggers; |
f14e6f7e | 382 | gboolean late_trigger_timeout; |
de4c29fa GS |
383 | enum { |
384 | SIGMA_UNINITIALIZED = 0, | |
385 | SIGMA_CONFIG, | |
386 | SIGMA_IDLE, | |
387 | SIGMA_CAPTURE, | |
388 | SIGMA_STOPPING, | |
389 | SIGMA_DOWNLOAD, | |
390 | } state; | |
98b43eb3 | 391 | struct submit_buffer *buffer; |
99965709 HE |
392 | }; |
393 | ||
7fe1f91f GS |
394 | /* "Automatic" and forced USB connection open/close support. */ |
395 | SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi); | |
396 | SR_PRIV int sigma_check_close(struct dev_context *devc); | |
397 | SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi); | |
398 | SR_PRIV int sigma_force_close(struct dev_context *devc); | |
399 | ||
53c8a99c GS |
400 | /* Save configuration across sessions, to reduce cost of continuation. */ |
401 | SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi); | |
402 | SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi); | |
403 | ||
a426f74a | 404 | /* Send register content (simple and complex) to the hardware. */ |
9b4d261f GS |
405 | SR_PRIV int sigma_write_register(struct dev_context *devc, |
406 | uint8_t reg, uint8_t *data, size_t len); | |
407 | SR_PRIV int sigma_set_register(struct dev_context *devc, | |
408 | uint8_t reg, uint8_t value); | |
409 | SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, | |
410 | struct triggerlut *lut); | |
a426f74a GS |
411 | |
412 | /* Samplerate constraints check, get/set/list helpers. */ | |
5e78a564 | 413 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); |
abcd4771 | 414 | SR_PRIV GVariant *sigma_get_samplerates_list(void); |
a426f74a GS |
415 | |
416 | /* Preparation of data acquisition, spec conversion, hardware configuration. */ | |
5e78a564 GS |
417 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); |
418 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); | |
3ba56876 | 419 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); |
9b4d261f GS |
420 | SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, |
421 | struct triggerlut *lut); | |
3ba56876 | 422 | |
a426f74a GS |
423 | /* Callback to periodically drive acuisition progress. */ |
424 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); | |
425 | ||
204b1629 | 426 | #endif |