]>
Commit | Line | Data |
---|---|---|
3ba56876 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
3ba56876 | 8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
3ba56876 | 23 | #include <config.h> |
24 | #include "protocol.h" | |
25 | ||
3ba56876 | 26 | /* |
7718f3ca GS |
27 | * Channels are labelled 1-16, see this vendor's image of the cable: |
28 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg (TI/TO are | |
29 | * additional trigger in/out signals). | |
3ba56876 | 30 | */ |
31 | static const char *channel_names[] = { | |
32 | "1", "2", "3", "4", "5", "6", "7", "8", | |
33 | "9", "10", "11", "12", "13", "14", "15", "16", | |
34 | }; | |
35 | ||
53a939ab GS |
36 | static const uint32_t scanopts[] = { |
37 | SR_CONF_CONN, | |
eabf9ca6 | 38 | SR_CONF_PROBE_NAMES, |
53a939ab GS |
39 | }; |
40 | ||
3ba56876 | 41 | static const uint32_t drvopts[] = { |
42 | SR_CONF_LOGIC_ANALYZER, | |
43 | }; | |
44 | ||
45 | static const uint32_t devopts[] = { | |
46 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
2f7e529c | 47 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
53a939ab | 48 | SR_CONF_CONN | SR_CONF_GET, |
3ba56876 | 49 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
2d8a5089 GS |
50 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, |
51 | SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
52 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
3ba56876 | 53 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, |
54 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
5cc292b3 | 55 | /* Consider SR_CONF_TRIGGER_PATTERN (SR_T_STRING, GET/SET) support. */ |
3ba56876 | 56 | }; |
57 | ||
2d8a5089 GS |
58 | static const char *ext_clock_edges[] = { |
59 | [SIGMA_CLOCK_EDGE_RISING] = "rising", | |
60 | [SIGMA_CLOCK_EDGE_FALLING] = "falling", | |
61 | [SIGMA_CLOCK_EDGE_EITHER] = "either", | |
62 | }; | |
63 | ||
3ba56876 | 64 | static const int32_t trigger_matches[] = { |
65 | SR_TRIGGER_ZERO, | |
66 | SR_TRIGGER_ONE, | |
67 | SR_TRIGGER_RISING, | |
68 | SR_TRIGGER_FALLING, | |
69 | }; | |
3ba56876 | 70 | |
3553451f | 71 | static void clear_helper(struct dev_context *devc) |
53279f13 | 72 | { |
7fe1f91f | 73 | (void)sigma_force_close(devc); |
53279f13 UH |
74 | } |
75 | ||
3ba56876 | 76 | static int dev_clear(const struct sr_dev_driver *di) |
77 | { | |
9b4d261f GS |
78 | return std_dev_clear_with_callback(di, |
79 | (std_dev_clear_callback)clear_helper); | |
3ba56876 | 80 | } |
81 | ||
53a939ab | 82 | static gboolean bus_addr_in_devices(int bus, int addr, GSList *devs) |
3ba56876 | 83 | { |
53a939ab | 84 | struct sr_usb_dev_inst *usb; |
3ba56876 | 85 | |
53a939ab GS |
86 | for (/* EMPTY */; devs; devs = devs->next) { |
87 | usb = devs->data; | |
88 | if (usb->bus == bus && usb->address == addr) | |
89 | return TRUE; | |
90 | } | |
3ba56876 | 91 | |
53a939ab GS |
92 | return FALSE; |
93 | } | |
3ba56876 | 94 | |
53a939ab GS |
95 | static gboolean known_vid_pid(const struct libusb_device_descriptor *des) |
96 | { | |
9b4d261f GS |
97 | gboolean is_sigma, is_omega; |
98 | ||
53a939ab GS |
99 | if (des->idVendor != USB_VENDOR_ASIX) |
100 | return FALSE; | |
9b4d261f GS |
101 | is_sigma = des->idProduct == USB_PRODUCT_SIGMA; |
102 | is_omega = des->idProduct == USB_PRODUCT_OMEGA; | |
103 | if (!is_sigma && !is_omega) | |
53a939ab GS |
104 | return FALSE; |
105 | return TRUE; | |
106 | } | |
3ba56876 | 107 | |
53a939ab GS |
108 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
109 | { | |
110 | struct drv_context *drvc; | |
111 | libusb_context *usbctx; | |
112 | const char *conn; | |
eabf9ca6 | 113 | const char *probe_names; |
53a939ab GS |
114 | GSList *l, *conn_devices; |
115 | struct sr_config *src; | |
116 | GSList *devices; | |
117 | libusb_device **devlist, *devitem; | |
118 | int bus, addr; | |
119 | struct libusb_device_descriptor des; | |
120 | struct libusb_device_handle *hdl; | |
121 | int ret; | |
122 | char conn_id[20]; | |
123 | char serno_txt[16]; | |
124 | char *end; | |
d7ce5452 | 125 | unsigned long serno_num, serno_pre; |
53a939ab GS |
126 | enum asix_device_type dev_type; |
127 | const char *dev_text; | |
128 | struct sr_dev_inst *sdi; | |
129 | struct dev_context *devc; | |
130 | size_t devidx, chidx; | |
eabf9ca6 | 131 | size_t count; |
53a939ab GS |
132 | |
133 | drvc = di->context; | |
134 | usbctx = drvc->sr_ctx->libusb_ctx; | |
135 | ||
136 | /* Find all devices which match an (optional) conn= spec. */ | |
137 | conn = NULL; | |
eabf9ca6 | 138 | probe_names = NULL; |
53a939ab GS |
139 | for (l = options; l; l = l->next) { |
140 | src = l->data; | |
141 | switch (src->key) { | |
142 | case SR_CONF_CONN: | |
143 | conn = g_variant_get_string(src->data, NULL); | |
144 | break; | |
eabf9ca6 GS |
145 | case SR_CONF_PROBE_NAMES: |
146 | probe_names = g_variant_get_string(src->data, NULL); | |
147 | break; | |
53a939ab | 148 | } |
3ba56876 | 149 | } |
53a939ab GS |
150 | conn_devices = NULL; |
151 | if (conn) | |
152 | conn_devices = sr_usb_find(usbctx, conn); | |
153 | if (conn && !conn_devices) | |
154 | return NULL; | |
155 | ||
156 | /* Find all ASIX logic analyzers (which match the connection spec). */ | |
157 | devices = NULL; | |
158 | libusb_get_device_list(usbctx, &devlist); | |
159 | for (devidx = 0; devlist[devidx]; devidx++) { | |
160 | devitem = devlist[devidx]; | |
161 | ||
162 | /* Check for connection match if a user spec was given. */ | |
163 | bus = libusb_get_bus_number(devitem); | |
164 | addr = libusb_get_device_address(devitem); | |
165 | if (conn && !bus_addr_in_devices(bus, addr, conn_devices)) | |
166 | continue; | |
167 | snprintf(conn_id, sizeof(conn_id), "%d.%d", bus, addr); | |
168 | ||
169 | /* | |
170 | * Check for known VID:PID pairs. Get the serial number, | |
171 | * to then derive the device type from it. | |
172 | */ | |
173 | libusb_get_device_descriptor(devitem, &des); | |
174 | if (!known_vid_pid(&des)) | |
175 | continue; | |
176 | if (!des.iSerialNumber) { | |
177 | sr_warn("Cannot get serial number (index 0)."); | |
178 | continue; | |
179 | } | |
180 | ret = libusb_open(devitem, &hdl); | |
181 | if (ret < 0) { | |
182 | sr_warn("Cannot open USB device %04x.%04x: %s.", | |
183 | des.idVendor, des.idProduct, | |
184 | libusb_error_name(ret)); | |
185 | continue; | |
186 | } | |
187 | ret = libusb_get_string_descriptor_ascii(hdl, | |
188 | des.iSerialNumber, | |
189 | (unsigned char *)serno_txt, sizeof(serno_txt)); | |
190 | if (ret < 0) { | |
191 | sr_warn("Cannot get serial number (%s).", | |
192 | libusb_error_name(ret)); | |
193 | libusb_close(hdl); | |
194 | continue; | |
195 | } | |
196 | libusb_close(hdl); | |
197 | ||
198 | /* | |
199 | * All ASIX logic analyzers have a serial number, which | |
200 | * reads as a hex number, and tells the device type. | |
201 | */ | |
d7ce5452 | 202 | ret = sr_atoul_base(serno_txt, &serno_num, &end, 16); |
53a939ab GS |
203 | if (ret != SR_OK || !end || *end) { |
204 | sr_warn("Cannot interpret serial number %s.", serno_txt); | |
205 | continue; | |
206 | } | |
207 | dev_type = ASIX_TYPE_NONE; | |
208 | dev_text = NULL; | |
209 | serno_pre = serno_num >> 16; | |
210 | switch (serno_pre) { | |
211 | case 0xa601: | |
212 | dev_type = ASIX_TYPE_SIGMA; | |
213 | dev_text = "SIGMA"; | |
214 | sr_info("Found SIGMA, serno %s.", serno_txt); | |
215 | break; | |
216 | case 0xa602: | |
217 | dev_type = ASIX_TYPE_SIGMA; | |
218 | dev_text = "SIGMA2"; | |
219 | sr_info("Found SIGMA2, serno %s.", serno_txt); | |
220 | break; | |
221 | case 0xa603: | |
222 | dev_type = ASIX_TYPE_OMEGA; | |
223 | dev_text = "OMEGA"; | |
224 | sr_info("Found OMEGA, serno %s.", serno_txt); | |
225 | if (!ASIX_WITH_OMEGA) { | |
226 | sr_warn("OMEGA support is not implemented yet."); | |
227 | continue; | |
228 | } | |
229 | break; | |
230 | default: | |
231 | sr_warn("Unknown serno %s, skipping.", serno_txt); | |
232 | continue; | |
233 | } | |
234 | ||
235 | /* Create a device instance, add it to the result set. */ | |
236 | ||
237 | sdi = g_malloc0(sizeof(*sdi)); | |
238 | devices = g_slist_append(devices, sdi); | |
239 | sdi->status = SR_ST_INITIALIZING; | |
240 | sdi->vendor = g_strdup("ASIX"); | |
241 | sdi->model = g_strdup(dev_text); | |
242 | sdi->serial_num = g_strdup(serno_txt); | |
243 | sdi->connection_id = g_strdup(conn_id); | |
53a939ab GS |
244 | devc = g_malloc0(sizeof(*devc)); |
245 | sdi->priv = devc; | |
eabf9ca6 GS |
246 | devc->channel_names = sr_parse_probe_names(probe_names, |
247 | channel_names, ARRAY_SIZE(channel_names), | |
248 | ARRAY_SIZE(channel_names), &count); | |
249 | for (chidx = 0; chidx < count; chidx++) | |
250 | sr_channel_new(sdi, chidx, SR_CHANNEL_LOGIC, | |
251 | TRUE, devc->channel_names[chidx]); | |
53a939ab GS |
252 | devc->id.vid = des.idVendor; |
253 | devc->id.pid = des.idProduct; | |
254 | devc->id.serno = serno_num; | |
255 | devc->id.prefix = serno_pre; | |
256 | devc->id.type = dev_type; | |
156b6879 | 257 | sr_sw_limits_init(&devc->limit.config); |
53a939ab | 258 | devc->capture_ratio = 50; |
3d9373af | 259 | devc->use_triggers = FALSE; |
7fe1f91f | 260 | |
53c8a99c GS |
261 | /* Get current hardware configuration (or use defaults). */ |
262 | (void)sigma_fetch_hw_config(sdi); | |
3ba56876 | 263 | } |
53a939ab GS |
264 | libusb_free_device_list(devlist, 1); |
265 | g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free); | |
3ba56876 | 266 | |
53a939ab | 267 | return std_scan_complete(di, devices); |
3ba56876 | 268 | } |
269 | ||
3ba56876 | 270 | static int dev_open(struct sr_dev_inst *sdi) |
271 | { | |
272 | struct dev_context *devc; | |
3ba56876 | 273 | |
274 | devc = sdi->priv; | |
275 | ||
53a939ab GS |
276 | if (devc->id.type == ASIX_TYPE_OMEGA && !ASIX_WITH_OMEGA) { |
277 | sr_err("OMEGA support is not implemented yet."); | |
278 | return SR_ERR_NA; | |
279 | } | |
3ba56876 | 280 | |
7fe1f91f | 281 | return sigma_force_open(sdi); |
3ba56876 | 282 | } |
283 | ||
284 | static int dev_close(struct sr_dev_inst *sdi) | |
285 | { | |
286 | struct dev_context *devc; | |
287 | ||
288 | devc = sdi->priv; | |
289 | ||
7fe1f91f | 290 | return sigma_force_close(devc); |
3ba56876 | 291 | } |
292 | ||
dd7a72ea UH |
293 | static int config_get(uint32_t key, GVariant **data, |
294 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 295 | { |
296 | struct dev_context *devc; | |
2d8a5089 | 297 | const char *clock_text; |
3ba56876 | 298 | |
299 | (void)cg; | |
300 | ||
301 | if (!sdi) | |
302 | return SR_ERR; | |
303 | devc = sdi->priv; | |
304 | ||
305 | switch (key) { | |
53a939ab GS |
306 | case SR_CONF_CONN: |
307 | *data = g_variant_new_string(sdi->connection_id); | |
308 | break; | |
3ba56876 | 309 | case SR_CONF_SAMPLERATE: |
2d8a5089 GS |
310 | *data = g_variant_new_uint64(devc->clock.samplerate); |
311 | break; | |
312 | case SR_CONF_EXTERNAL_CLOCK: | |
313 | *data = g_variant_new_boolean(devc->clock.use_ext_clock); | |
314 | break; | |
315 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
eabf9ca6 | 316 | clock_text = devc->channel_names[devc->clock.clock_pin]; |
2d8a5089 GS |
317 | *data = g_variant_new_string(clock_text); |
318 | break; | |
319 | case SR_CONF_CLOCK_EDGE: | |
320 | clock_text = ext_clock_edges[devc->clock.clock_edge]; | |
321 | *data = g_variant_new_string(clock_text); | |
3ba56876 | 322 | break; |
323 | case SR_CONF_LIMIT_MSEC: | |
2f7e529c | 324 | case SR_CONF_LIMIT_SAMPLES: |
156b6879 | 325 | return sr_sw_limits_config_get(&devc->limit.config, key, data); |
3ba56876 | 326 | case SR_CONF_CAPTURE_RATIO: |
327 | *data = g_variant_new_uint64(devc->capture_ratio); | |
328 | break; | |
329 | default: | |
330 | return SR_ERR_NA; | |
331 | } | |
332 | ||
333 | return SR_OK; | |
334 | } | |
335 | ||
dd7a72ea UH |
336 | static int config_set(uint32_t key, GVariant *data, |
337 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 338 | { |
339 | struct dev_context *devc; | |
5e78a564 GS |
340 | int ret; |
341 | uint64_t want_rate, have_rate; | |
eabf9ca6 GS |
342 | const char **names; |
343 | size_t count; | |
2d8a5089 | 344 | int idx; |
3ba56876 | 345 | |
346 | (void)cg; | |
347 | ||
3ba56876 | 348 | devc = sdi->priv; |
349 | ||
3ba56876 | 350 | switch (key) { |
351 | case SR_CONF_SAMPLERATE: | |
5e78a564 GS |
352 | want_rate = g_variant_get_uint64(data); |
353 | ret = sigma_normalize_samplerate(want_rate, &have_rate); | |
354 | if (ret != SR_OK) | |
355 | return ret; | |
356 | if (have_rate != want_rate) { | |
357 | char *text_want, *text_have; | |
358 | text_want = sr_samplerate_string(want_rate); | |
359 | text_have = sr_samplerate_string(have_rate); | |
360 | sr_info("Adjusted samplerate %s to %s.", | |
361 | text_want, text_have); | |
362 | g_free(text_want); | |
363 | g_free(text_have); | |
364 | } | |
2d8a5089 GS |
365 | devc->clock.samplerate = have_rate; |
366 | break; | |
367 | case SR_CONF_EXTERNAL_CLOCK: | |
368 | devc->clock.use_ext_clock = g_variant_get_boolean(data); | |
369 | break; | |
370 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
eabf9ca6 GS |
371 | names = (const char **)devc->channel_names; |
372 | count = g_strv_length(devc->channel_names); | |
373 | idx = std_str_idx(data, names, count); | |
2d8a5089 GS |
374 | if (idx < 0) |
375 | return SR_ERR_ARG; | |
376 | devc->clock.clock_pin = idx; | |
377 | break; | |
378 | case SR_CONF_CLOCK_EDGE: | |
379 | idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges)); | |
380 | if (idx < 0) | |
381 | return SR_ERR_ARG; | |
382 | devc->clock.clock_edge = idx; | |
3ba56876 | 383 | break; |
5e78a564 | 384 | case SR_CONF_LIMIT_MSEC: |
3ba56876 | 385 | case SR_CONF_LIMIT_SAMPLES: |
156b6879 | 386 | return sr_sw_limits_config_set(&devc->limit.config, key, data); |
3ba56876 | 387 | case SR_CONF_CAPTURE_RATIO: |
efad7ccc | 388 | devc->capture_ratio = g_variant_get_uint64(data); |
3ba56876 | 389 | break; |
390 | default: | |
758906aa | 391 | return SR_ERR_NA; |
3ba56876 | 392 | } |
393 | ||
758906aa | 394 | return SR_OK; |
3ba56876 | 395 | } |
396 | ||
dd7a72ea UH |
397 | static int config_list(uint32_t key, GVariant **data, |
398 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 399 | { |
eabf9ca6 GS |
400 | struct dev_context *devc; |
401 | const char **names; | |
402 | size_t count; | |
403 | ||
05a8a5f3 | 404 | devc = sdi ? sdi->priv : NULL; |
3ba56876 | 405 | switch (key) { |
53a939ab | 406 | case SR_CONF_SCAN_OPTIONS: |
3ba56876 | 407 | case SR_CONF_DEVICE_OPTIONS: |
53a939ab GS |
408 | if (cg) |
409 | return SR_ERR_NA; | |
9b4d261f GS |
410 | return STD_CONFIG_LIST(key, data, sdi, cg, |
411 | scanopts, drvopts, devopts); | |
3ba56876 | 412 | case SR_CONF_SAMPLERATE: |
abcd4771 | 413 | *data = sigma_get_samplerates_list(); |
3ba56876 | 414 | break; |
2d8a5089 | 415 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: |
05a8a5f3 GS |
416 | if (!devc) |
417 | return SR_ERR_ARG; | |
eabf9ca6 GS |
418 | names = (const char **)devc->channel_names; |
419 | count = g_strv_length(devc->channel_names); | |
420 | *data = g_variant_new_strv(names, count); | |
2d8a5089 GS |
421 | break; |
422 | case SR_CONF_CLOCK_EDGE: | |
423 | *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges)); | |
424 | break; | |
3ba56876 | 425 | case SR_CONF_TRIGGER_MATCH: |
53012da6 | 426 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); |
3ba56876 | 427 | break; |
428 | default: | |
429 | return SR_ERR_NA; | |
430 | } | |
431 | ||
432 | return SR_OK; | |
433 | } | |
434 | ||
695dc859 | 435 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
3ba56876 | 436 | { |
437 | struct dev_context *devc; | |
419f1095 GS |
438 | uint16_t pindis_mask; |
439 | uint8_t async, div; | |
3d9373af GS |
440 | int ret; |
441 | size_t triggerpin; | |
419f1095 | 442 | uint8_t trigsel2; |
3ba56876 | 443 | struct triggerinout triggerinout_conf; |
444 | struct triggerlut lut; | |
3d9373af | 445 | uint8_t regval, cmd_bytes[4], *wrptr; |
3ba56876 | 446 | |
3ba56876 | 447 | devc = sdi->priv; |
448 | ||
f14e6f7e GS |
449 | /* Convert caller's trigger spec to driver's internal format. */ |
450 | ret = sigma_convert_trigger(sdi); | |
451 | if (ret != SR_OK) { | |
452 | sr_err("Could not configure triggers."); | |
453 | return ret; | |
454 | } | |
455 | ||
5e78a564 GS |
456 | /* |
457 | * Setup the device's samplerate from the value which up to now | |
458 | * just got checked and stored. As a byproduct this can pick and | |
459 | * send firmware to the device, reduce the number of available | |
460 | * logic channels, etc. | |
461 | * | |
462 | * Determine an acquisition timeout from optionally configured | |
463 | * sample count or time limits. Which depends on the samplerate. | |
2d8a5089 | 464 | * Force 50MHz samplerate when external clock is in use. |
5e78a564 | 465 | */ |
2d8a5089 GS |
466 | if (devc->clock.use_ext_clock) { |
467 | if (devc->clock.samplerate != SR_MHZ(50)) | |
468 | sr_info("External clock, forcing 50MHz samplerate."); | |
469 | devc->clock.samplerate = SR_MHZ(50); | |
470 | } | |
5e78a564 GS |
471 | ret = sigma_set_samplerate(sdi); |
472 | if (ret != SR_OK) | |
473 | return ret; | |
474 | ret = sigma_set_acquire_timeout(devc); | |
475 | if (ret != SR_OK) | |
476 | return ret; | |
477 | ||
3ba56876 | 478 | /* Enter trigger programming mode. */ |
0f017b7d GS |
479 | trigsel2 = TRGSEL2_RESET; |
480 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); | |
88a5f9ea GS |
481 | if (ret != SR_OK) |
482 | return ret; | |
3ba56876 | 483 | |
419f1095 | 484 | trigsel2 = 0; |
2d8a5089 | 485 | if (devc->clock.samplerate >= SR_MHZ(100)) { |
f06fb3e9 | 486 | /* 100 and 200 MHz mode. */ |
419f1095 | 487 | /* TODO Decipher the 0x81 magic number's purpose. */ |
88a5f9ea GS |
488 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81); |
489 | if (ret != SR_OK) | |
490 | return ret; | |
3ba56876 | 491 | |
492 | /* Find which pin to trigger on from mask. */ | |
9b4d261f | 493 | for (triggerpin = 0; triggerpin < 8; triggerpin++) { |
3f5f5484 | 494 | if (devc->trigger.risingmask & BIT(triggerpin)) |
9b4d261f | 495 | break; |
3f5f5484 | 496 | if (devc->trigger.fallingmask & BIT(triggerpin)) |
3ba56876 | 497 | break; |
9b4d261f | 498 | } |
3ba56876 | 499 | |
500 | /* Set trigger pin and light LED on trigger. */ | |
419f1095 GS |
501 | trigsel2 = triggerpin & TRGSEL2_PINS_MASK; |
502 | trigsel2 |= TRGSEL2_LEDSEL1; | |
3ba56876 | 503 | |
504 | /* Default rising edge. */ | |
419f1095 | 505 | /* TODO Documentation disagrees, bit set means _rising_ edge. */ |
3ba56876 | 506 | if (devc->trigger.fallingmask) |
419f1095 | 507 | trigsel2 |= TRGSEL2_PINPOL_RISE; |
3ba56876 | 508 | |
2d8a5089 | 509 | } else if (devc->clock.samplerate <= SR_MHZ(50)) { |
419f1095 GS |
510 | /* 50MHz firmware modes. */ |
511 | ||
512 | /* Translate application specs to hardware perspective. */ | |
88a5f9ea GS |
513 | ret = sigma_build_basic_trigger(devc, &lut); |
514 | if (ret != SR_OK) | |
515 | return ret; | |
3ba56876 | 516 | |
419f1095 | 517 | /* Communicate resulting register values to the device. */ |
88a5f9ea GS |
518 | ret = sigma_write_trigger_lut(devc, &lut); |
519 | if (ret != SR_OK) | |
520 | return ret; | |
3ba56876 | 521 | |
419f1095 | 522 | trigsel2 = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0; |
3ba56876 | 523 | } |
524 | ||
525 | /* Setup trigger in and out pins to default values. */ | |
5c231fc4 | 526 | memset(&triggerinout_conf, 0, sizeof(triggerinout_conf)); |
3d9373af GS |
527 | triggerinout_conf.trgout_bytrigger = TRUE; |
528 | triggerinout_conf.trgout_enable = TRUE; | |
a53b8e4d GS |
529 | /* TODO |
530 | * Verify the correctness of this implementation. The previous | |
531 | * version used to assign to a C language struct with bit fields | |
532 | * which is highly non-portable and hard to guess the resulting | |
533 | * raw memory layout or wire transfer content. The C struct's | |
534 | * field names did not match the vendor documentation's names. | |
535 | * Which means that I could not verify "on paper" either. Let's | |
536 | * re-visit this code later during research for trigger support. | |
537 | */ | |
3d9373af | 538 | wrptr = cmd_bytes; |
a53b8e4d GS |
539 | regval = 0; |
540 | if (triggerinout_conf.trgout_bytrigger) | |
541 | regval |= TRGOPT_TRGOOUTEN; | |
542 | write_u8_inc(&wrptr, regval); | |
543 | regval &= ~TRGOPT_CLEAR_MASK; | |
544 | if (triggerinout_conf.trgout_enable) | |
545 | regval |= TRGOPT_TRGOEN; | |
546 | write_u8_inc(&wrptr, regval); | |
88a5f9ea | 547 | ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION, |
3d9373af | 548 | cmd_bytes, wrptr - cmd_bytes); |
88a5f9ea GS |
549 | if (ret != SR_OK) |
550 | return ret; | |
a53b8e4d GS |
551 | |
552 | /* Leave trigger programming mode. */ | |
419f1095 | 553 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); |
88a5f9ea GS |
554 | if (ret != SR_OK) |
555 | return ret; | |
3ba56876 | 556 | |
419f1095 GS |
557 | /* |
558 | * Samplerate dependent clock and channels configuration. Some | |
559 | * channels by design are not available at higher clock rates. | |
560 | * Register layout differs between firmware variants (depth 1 | |
561 | * with LSB channel mask above 50MHz, depth 4 with more details | |
562 | * up to 50MHz). | |
563 | * | |
564 | * Derive a mask where bits are set for unavailable channels. | |
565 | * Either send the single byte, or the full byte sequence. | |
566 | */ | |
de4c29fa | 567 | pindis_mask = ~BITS_MASK(devc->interp.num_channels); |
2d8a5089 | 568 | if (devc->clock.samplerate > SR_MHZ(50)) { |
419f1095 GS |
569 | ret = sigma_set_register(devc, WRITE_CLOCK_SELECT, |
570 | pindis_mask & 0xff); | |
8256ed15 | 571 | } else { |
3d9373af | 572 | wrptr = cmd_bytes; |
419f1095 GS |
573 | /* Select 50MHz base clock, and divider. */ |
574 | async = 0; | |
2d8a5089 GS |
575 | div = SR_MHZ(50) / devc->clock.samplerate - 1; |
576 | if (devc->clock.use_ext_clock) { | |
577 | async = CLKSEL_CLKSEL8; | |
578 | div = devc->clock.clock_pin + 1; | |
579 | switch (devc->clock.clock_edge) { | |
580 | case SIGMA_CLOCK_EDGE_RISING: | |
581 | div |= CLKSEL_RISING; | |
582 | break; | |
583 | case SIGMA_CLOCK_EDGE_FALLING: | |
584 | div |= CLKSEL_FALLING; | |
585 | break; | |
586 | case SIGMA_CLOCK_EDGE_EITHER: | |
587 | div |= CLKSEL_RISING; | |
588 | div |= CLKSEL_FALLING; | |
589 | break; | |
590 | } | |
591 | } | |
419f1095 GS |
592 | write_u8_inc(&wrptr, async); |
593 | write_u8_inc(&wrptr, div); | |
594 | write_u16be_inc(&wrptr, pindis_mask); | |
595 | ret = sigma_write_register(devc, WRITE_CLOCK_SELECT, | |
3d9373af | 596 | cmd_bytes, wrptr - cmd_bytes); |
3ba56876 | 597 | } |
88a5f9ea GS |
598 | if (ret != SR_OK) |
599 | return ret; | |
3ba56876 | 600 | |
601 | /* Setup maximum post trigger time. */ | |
88a5f9ea | 602 | ret = sigma_set_register(devc, WRITE_POST_TRIGGER, |
9b4d261f | 603 | (devc->capture_ratio * 255) / 100); |
88a5f9ea GS |
604 | if (ret != SR_OK) |
605 | return ret; | |
3ba56876 | 606 | |
607 | /* Start acqusition. */ | |
9b4d261f | 608 | regval = WMR_TRGRES | WMR_SDRAMWRITEEN; |
e0926713 | 609 | if (devc->use_triggers) |
fb65ca09 | 610 | regval |= WMR_TRGEN; |
88a5f9ea GS |
611 | ret = sigma_set_register(devc, WRITE_MODE, regval); |
612 | if (ret != SR_OK) | |
613 | return ret; | |
3ba56876 | 614 | |
88a5f9ea GS |
615 | ret = std_session_send_df_header(sdi); |
616 | if (ret != SR_OK) | |
617 | return ret; | |
3ba56876 | 618 | |
619 | /* Add capture source. */ | |
88a5f9ea | 620 | ret = sr_session_source_add(sdi->session, -1, 0, 10, |
9b4d261f | 621 | sigma_receive_data, (void *)sdi); |
88a5f9ea GS |
622 | if (ret != SR_OK) |
623 | return ret; | |
3ba56876 | 624 | |
de4c29fa | 625 | devc->state = SIGMA_CAPTURE; |
3ba56876 | 626 | |
627 | return SR_OK; | |
628 | } | |
629 | ||
695dc859 | 630 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
3ba56876 | 631 | { |
632 | struct dev_context *devc; | |
633 | ||
3ba56876 | 634 | devc = sdi->priv; |
3ba56876 | 635 | |
dde0175d GS |
636 | /* |
637 | * When acquisition is currently running, keep the receive | |
638 | * routine registered and have it stop the acquisition upon the | |
639 | * next invocation. Else unregister the receive routine here | |
640 | * already. The detour is required to have sample data retrieved | |
641 | * for forced acquisition stops. | |
642 | */ | |
de4c29fa GS |
643 | if (devc->state == SIGMA_CAPTURE) { |
644 | devc->state = SIGMA_STOPPING; | |
dde0175d | 645 | } else { |
de4c29fa | 646 | devc->state = SIGMA_IDLE; |
88a5f9ea | 647 | (void)sr_session_source_remove(sdi->session, -1); |
dde0175d | 648 | } |
3ba56876 | 649 | |
650 | return SR_OK; | |
651 | } | |
652 | ||
dd5c48a6 | 653 | static struct sr_dev_driver asix_sigma_driver_info = { |
3ba56876 | 654 | .name = "asix-sigma", |
655 | .longname = "ASIX SIGMA/SIGMA2", | |
656 | .api_version = 1, | |
c2fdcc25 | 657 | .init = std_init, |
700d6b64 | 658 | .cleanup = std_cleanup, |
3ba56876 | 659 | .scan = scan, |
c01bf34c | 660 | .dev_list = std_dev_list, |
3ba56876 | 661 | .dev_clear = dev_clear, |
662 | .config_get = config_get, | |
663 | .config_set = config_set, | |
664 | .config_list = config_list, | |
665 | .dev_open = dev_open, | |
666 | .dev_close = dev_close, | |
667 | .dev_acquisition_start = dev_acquisition_start, | |
668 | .dev_acquisition_stop = dev_acquisition_stop, | |
669 | .context = NULL, | |
670 | }; | |
dd5c48a6 | 671 | SR_REGISTER_DEV_DRIVER(asix_sigma_driver_info); |