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ols: Do not randomly probe serial ports
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
915f7cc8 49static const int hwcaps[] = {
5a2326a7
UH
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 54 SR_HWCAP_RLE,
43fc7885 55 0,
a1bb33af
UH
56};
57
d261dbbf 58/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 59static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
4fe9a6da 95/* default supported samplerates, can be overridden by device metadata */
a533743d 96static const struct sr_samplerates samplerates = {
c9140419 97 SR_HZ(10),
59df0c77 98 SR_MHZ(200),
c9140419
UH
99 SR_HZ(1),
100 NULL,
a1bb33af
UH
101};
102
e5e81856
BV
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 105
6937bb75 106static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
107{
108 char buf[1];
109
b08024a8 110 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 111 buf[0] = command;
2119ab03 112 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 113 return SR_ERR;
a1bb33af 114
e46b8fb1 115 return SR_OK;
a1bb33af
UH
116}
117
6937bb75 118static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
2119ab03 128 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
014359e3 134static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 135{
014359e3 136 struct dev_context *devc;
1b79df2f
JH
137 const struct sr_probe *probe;
138 const GSList *l;
6937bb75 139 int probe_bit, stage, i;
a1bb33af
UH
140 char *tc;
141
014359e3
BV
142 devc = sdi->priv;
143
fefc4b85 144 devc->probe_mask = 0;
43fc7885 145 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
146 devc->trigger_mask[i] = 0;
147 devc->trigger_value[i] = 0;
a1bb33af
UH
148 }
149
fefc4b85 150 devc->num_stages = 0;
014359e3 151 for (l = sdi->probes; l; l = l->next) {
1b79df2f 152 probe = (const struct sr_probe *)l->data;
43fc7885 153 if (!probe->enabled)
6937bb75
BV
154 continue;
155
43fc7885
UH
156 /*
157 * Set up the probe mask for later configuration into the
158 * flag register.
159 */
b35c8293 160 probe_bit = 1 << (probe->index);
fefc4b85 161 devc->probe_mask |= probe_bit;
6937bb75 162
a803c0db 163 if (!probe->trigger)
6937bb75
BV
164 continue;
165
43fc7885 166 /* Configure trigger mask and value. */
6937bb75 167 stage = 0;
43fc7885 168 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 169 devc->trigger_mask[stage] |= probe_bit;
43fc7885 170 if (*tc == '1')
fefc4b85 171 devc->trigger_value[stage] |= probe_bit;
6937bb75 172 stage++;
43fc7885
UH
173 if (stage > 3)
174 /*
175 * TODO: Only supporting parallel mode, with
176 * up to 4 stages.
177 */
e46b8fb1 178 return SR_ERR;
a1bb33af 179 }
fefc4b85
BV
180 if (stage > devc->num_stages)
181 devc->num_stages = stage;
a1bb33af
UH
182 }
183
e46b8fb1 184 return SR_OK;
a1bb33af
UH
185}
186
a803c0db 187static uint32_t reverse16(uint32_t in)
6937bb75
BV
188{
189 uint32_t out;
190
a803c0db
BV
191 out = (in & 0xff) << 8;
192 out |= (in & 0xff00) >> 8;
193 out |= (in & 0xff0000) << 8;
194 out |= (in & 0xff000000) >> 8;
195
196 return out;
197}
198
199static uint32_t reverse32(uint32_t in)
200{
201 uint32_t out;
202
203 out = (in & 0xff) << 24;
204 out |= (in & 0xff00) << 8;
205 out |= (in & 0xff0000) >> 8;
206 out |= (in & 0xff000000) >> 24;
207
208 return out;
6937bb75
BV
209}
210
fefc4b85 211static struct dev_context *ols_dev_new(void)
4fe9a6da 212{
fefc4b85 213 struct dev_context *devc;
4fe9a6da 214
fefc4b85
BV
215 /* TODO: Is 'devc' ever g_free()'d? */
216 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
217 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
218 return NULL;
219 }
220
fefc4b85
BV
221 devc->trigger_at = -1;
222 devc->probe_mask = 0xffffffff;
223 devc->cur_samplerate = SR_KHZ(200);
224 devc->serial = NULL;
4fe9a6da 225
fefc4b85 226 return devc;
4fe9a6da
BV
227}
228
d68e2d1a 229static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 230{
d68e2d1a 231 struct sr_dev_inst *sdi;
fefc4b85 232 struct dev_context *devc;
10e5cbed
BV
233 struct sr_probe *probe;
234 uint32_t tmp_int, ui;
4fe9a6da 235 uint8_t key, type, token;
bb7ef793 236 GString *tmp_str, *devname, *version;
10e5cbed 237 guchar tmp_c;
4fe9a6da 238
d3683c42 239 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 240 sdi->driver = odi;
fefc4b85
BV
241 devc = ols_dev_new();
242 sdi->priv = devc;
4fe9a6da 243
bb7ef793 244 devname = g_string_new("");
4fe9a6da
BV
245 version = g_string_new("");
246
247 key = 0xff;
248 while (key) {
249 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
250 break;
251 type = key >> 5;
252 token = key & 0x1f;
253 switch (type) {
254 case 0:
255 /* NULL-terminated string */
256 tmp_str = g_string_new("");
257 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
258 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
259 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
260 key, tmp_str->str);
4fe9a6da
BV
261 switch (token) {
262 case 0x01:
263 /* Device name */
bb7ef793 264 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
265 break;
266 case 0x02:
267 /* FPGA firmware version */
268 if (version->len)
269 g_string_append(version, ", ");
270 g_string_append(version, "FPGA version ");
271 g_string_append(version, tmp_str->str);
272 break;
273 case 0x03:
274 /* Ancillary version */
275 if (version->len)
276 g_string_append(version, ", ");
277 g_string_append(version, "Ancillary version ");
278 g_string_append(version, tmp_str->str);
279 break;
280 default:
b08024a8
UH
281 sr_info("ols: unknown token 0x%.2x: '%s'",
282 token, tmp_str->str);
4fe9a6da
BV
283 break;
284 }
285 g_string_free(tmp_str, TRUE);
286 break;
287 case 1:
288 /* 32-bit unsigned integer */
289 if (serial_read(fd, &tmp_int, 4) != 4)
290 break;
291 tmp_int = reverse32(tmp_int);
b08024a8
UH
292 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
293 key, tmp_int);
4fe9a6da
BV
294 switch (token) {
295 case 0x00:
296 /* Number of usable probes */
10e5cbed
BV
297 for (ui = 0; ui < tmp_int; ui++) {
298 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
299 probe_names[ui])))
300 return 0;
301 sdi->probes = g_slist_append(sdi->probes, probe);
302 }
4fe9a6da
BV
303 break;
304 case 0x01:
305 /* Amount of sample memory available (bytes) */
fefc4b85 306 devc->max_samples = tmp_int;
4fe9a6da
BV
307 break;
308 case 0x02:
309 /* Amount of dynamic memory available (bytes) */
310 /* what is this for? */
311 break;
312 case 0x03:
313 /* Maximum sample rate (hz) */
fefc4b85 314 devc->max_samplerate = tmp_int;
4fe9a6da
BV
315 break;
316 case 0x04:
317 /* protocol version */
fefc4b85 318 devc->protocol_version = tmp_int;
4fe9a6da
BV
319 break;
320 default:
b08024a8
UH
321 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
322 token, tmp_int);
4fe9a6da
BV
323 break;
324 }
325 break;
326 case 2:
327 /* 8-bit unsigned integer */
328 if (serial_read(fd, &tmp_c, 1) != 1)
329 break;
b08024a8
UH
330 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
331 key, tmp_c);
4fe9a6da
BV
332 switch (token) {
333 case 0x00:
334 /* Number of usable probes */
10e5cbed
BV
335 for (ui = 0; ui < tmp_c; ui++) {
336 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
337 probe_names[ui])))
338 return 0;
339 sdi->probes = g_slist_append(sdi->probes, probe);
340 }
4fe9a6da
BV
341 break;
342 case 0x01:
343 /* protocol version */
fefc4b85 344 devc->protocol_version = tmp_c;
4fe9a6da
BV
345 break;
346 default:
b08024a8
UH
347 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
348 token, tmp_c);
4fe9a6da
BV
349 break;
350 }
351 break;
352 default:
353 /* unknown type */
354 break;
355 }
356 }
357
bb7ef793 358 sdi->model = devname->str;
4fe9a6da 359 sdi->version = version->str;
bb7ef793 360 g_string_free(devname, FALSE);
4fe9a6da
BV
361 g_string_free(version, FALSE);
362
363 return sdi;
364}
365
40dda2c3 366static int hw_init(void)
61136ea6 367{
fefc4b85 368 struct drv_context *drvc;
61136ea6 369
fefc4b85
BV
370 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
371 sr_err("ols: driver context malloc failed.");
886a52b6 372 return SR_ERR_MALLOC;
fefc4b85
BV
373 }
374 odi->priv = drvc;
61136ea6
BV
375
376 return SR_OK;
377}
378
10e5cbed 379static GSList *hw_scan(GSList *options)
a1bb33af 380{
a99e0d2a
AG
381 struct sr_hwopt *opt;
382 GSList *l, *devices;
383 const char *conn, *serialcomm;
d68e2d1a 384 struct sr_dev_inst *sdi;
fefc4b85
BV
385 struct drv_context *drvc;
386 struct dev_context *devc;
10e5cbed 387 struct sr_probe *probe;
a99e0d2a
AG
388 GPollFD probefd;
389 int final_devcnt, fd, ret, i;
390 char buf[8];
a1bb33af 391
10e5cbed 392 (void)options;
fefc4b85 393 drvc = odi->priv;
c0a4b971 394 final_devcnt = 0;
10e5cbed 395 devices = NULL;
c0a4b971 396
a99e0d2a
AG
397 conn = serialcomm = NULL;
398 for (l = options; l; l = l->next) {
399 opt = l->data;
400 switch (opt->hwopt) {
401 case SR_HWOPT_CONN:
402 conn = opt->value;
403 break;
404 case SR_HWOPT_SERIALCOMM:
405 serialcomm = opt->value;
406 break;
407 }
408 }
409 if (!conn) {
410 sr_err("ols: No serial port specified.");
411 return NULL;
c0a4b971
UH
412 }
413
a99e0d2a
AG
414 if (serialcomm == NULL) {
415 serialcomm = g_strdup("115200/8n1");
c0a4b971
UH
416 }
417
a99e0d2a
AG
418 /* The discovery procedure is like this: first send the Reset
419 * command (0x00) 5 times, since the device could be anywhere
420 * in a 5-byte command. Then send the ID command (0x02).
421 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
422 * have a match.
423 *
424 * Since it may take the device a while to respond at 115Kb/s,
425 * we do all the sending first, then wait for all of them to
426 * respond with g_poll().
427 */
428 sr_info("ols: probing %s .", conn);
429 fd = serial_open(conn, O_RDWR | O_NONBLOCK);
430 if (fd < 0) {
431 sr_err("ols: could not open port %s .", conn);
432 return NULL;
c0a4b971
UH
433 }
434
a99e0d2a
AG
435 serial_set_paramstr(fd, serialcomm);
436 ret = SR_OK;
437 for (i = 0; i < 5; i++) {
438 if ((ret = send_shortcommand(fd, CMD_RESET)) != SR_OK) {
439 /* Serial port is not writable. */
440 sr_err("ols: port %s is not writable.", conn);
a1bb33af
UH
441 }
442 }
a99e0d2a
AG
443 if (ret != SR_OK) {
444 serial_close(fd);
445 sr_err("ols: Could not use port %s. Quitting.", conn);
446 return NULL;
447 }
448 send_shortcommand(fd, CMD_ID);
a1bb33af 449
5b15b41e
PS
450 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
451 usleep(10000);
a1bb33af 452
a99e0d2a 453 g_poll(&probefd/*fds*/, 1/*devcnt*/, 1);
4fe9a6da 454
a99e0d2a
AG
455 if (probefd.revents != G_IO_IN)
456 return NULL;
457 if (serial_read(probefd.fd, buf, 4) != 4)
458 return NULL;
459 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
460 return NULL;
4fe9a6da 461
a99e0d2a
AG
462 /* definitely using the OLS protocol, check if it supports
463 * the metadata command
464 */
465 send_shortcommand(probefd.fd, CMD_METADATA);
466 probefd.fd = fd;
467 probefd.events = G_IO_IN;
468 if (g_poll(&probefd, 1, 10) > 0) {
469 /* got metadata */
470 sdi = get_metadata(fd);
471 sdi->index = final_devcnt;
472 devc = sdi->priv;
473 } else {
474 /* not an OLS -- some other board that uses the sump protocol */
475 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
476 "Sump", "Logic Analyzer", "v1.0");
477 sdi->driver = odi;
478 devc = ols_dev_new();
479 for (i = 0; i < 32; i++) {
480 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
481 probe_names[i])))
482 return 0;
483 sdi->probes = g_slist_append(sdi->probes, probe);
a1bb33af 484 }
a99e0d2a 485 sdi->priv = devc;
4fe9a6da 486 }
a99e0d2a
AG
487 devc->serial = sr_serial_dev_inst_new("FIXME", -1);
488 drvc->instances = g_slist_append(drvc->instances, sdi);
489 devices = g_slist_append(devices, sdi);
490
491 final_devcnt++;
492 serial_close(probefd.fd);
4fe9a6da
BV
493
494 /* clean up after all the probing */
a99e0d2a
AG
495 if (fd != 0) {
496 serial_close(fd);
a1bb33af
UH
497 }
498
10e5cbed 499 return devices;
a1bb33af
UH
500}
501
811deee4
BV
502static GSList *hw_dev_list(void)
503{
504 struct drv_context *drvc;
505
506 drvc = odi->priv;
507
508 return drvc->instances;
509}
510
25a0f108 511static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 512{
fefc4b85 513 struct dev_context *devc;
a1bb33af 514
fefc4b85 515 devc = sdi->priv;
69890f73 516
fefc4b85
BV
517 devc->serial->fd = serial_open(devc->serial->port, O_RDWR);
518 if (devc->serial->fd == -1)
e46b8fb1 519 return SR_ERR;
a1bb33af 520
5a2326a7 521 sdi->status = SR_ST_ACTIVE;
a1bb33af 522
e46b8fb1 523 return SR_OK;
a1bb33af
UH
524}
525
25a0f108 526static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 527{
fefc4b85 528 struct dev_context *devc;
a1bb33af 529
fefc4b85 530 devc = sdi->priv;
69890f73 531
fefc4b85
BV
532 if (devc->serial->fd != -1) {
533 serial_close(devc->serial->fd);
534 devc->serial->fd = -1;
5a2326a7 535 sdi->status = SR_ST_INACTIVE;
a1bb33af 536 }
697785d1
UH
537
538 return SR_OK;
a1bb33af
UH
539}
540
57ab7d9f 541static int hw_cleanup(void)
a1bb33af
UH
542{
543 GSList *l;
d68e2d1a 544 struct sr_dev_inst *sdi;
fefc4b85
BV
545 struct drv_context *drvc;
546 struct dev_context *devc;
57ab7d9f 547 int ret = SR_OK;
a1bb33af 548
fefc4b85
BV
549 if (!(drvc = odi->priv))
550 return SR_OK;
551
8722c31e 552 /* Properly close and free all devices. */
fefc4b85 553 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
554 if (!(sdi = l->data)) {
555 /* Log error, but continue cleaning up the rest. */
556 sr_err("ols: %s: sdi was NULL, continuing", __func__);
557 ret = SR_ERR_BUG;
558 continue;
559 }
fefc4b85 560 if (!(devc = sdi->priv)) {
57ab7d9f
UH
561 /* Log error, but continue cleaning up the rest. */
562 sr_err("ols: %s: sdi->priv was NULL, continuing",
563 __func__);
564 ret = SR_ERR_BUG;
565 continue;
566 }
567 /* TODO: Check for serial != NULL. */
fefc4b85
BV
568 if (devc->serial->fd != -1)
569 serial_close(devc->serial->fd);
570 sr_serial_dev_inst_free(devc->serial);
d3683c42 571 sr_dev_inst_free(sdi);
a1bb33af 572 }
fefc4b85
BV
573 g_slist_free(drvc->instances);
574 drvc->instances = NULL;
57ab7d9f
UH
575
576 return ret;
a1bb33af
UH
577}
578
dddfb3db
BV
579static int hw_info_get(int info_id, const void **data,
580 const struct sr_dev_inst *sdi)
a1bb33af 581{
fefc4b85 582 struct dev_context *devc;
a1bb33af 583
dddfb3db 584 switch (info_id) {
2ca4465b
BV
585 case SR_DI_HWCAPS:
586 *data = hwcaps;
587 break;
5a2326a7 588 case SR_DI_NUM_PROBES:
dddfb3db 589 *data = GINT_TO_POINTER(1);
a1bb33af 590 break;
464d12c7 591 case SR_DI_PROBE_NAMES:
dddfb3db 592 *data = probe_names;
464d12c7 593 break;
5a2326a7 594 case SR_DI_SAMPLERATES:
dddfb3db 595 *data = &samplerates;
a1bb33af 596 break;
5a2326a7 597 case SR_DI_TRIGGER_TYPES:
dddfb3db 598 *data = (char *)TRIGGER_TYPES;
a1bb33af 599 break;
5a2326a7 600 case SR_DI_CUR_SAMPLERATE:
dddfb3db 601 if (sdi) {
fefc4b85
BV
602 devc = sdi->priv;
603 *data = &devc->cur_samplerate;
dddfb3db
BV
604 } else
605 return SR_ERR;
a1bb33af 606 break;
dddfb3db
BV
607 default:
608 return SR_ERR_ARG;
a1bb33af
UH
609 }
610
dddfb3db 611 return SR_OK;
a1bb33af
UH
612}
613
6f4b1868 614static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 615{
fefc4b85 616 struct dev_context *devc;
a1bb33af 617
fefc4b85
BV
618 devc = sdi->priv;
619 if (devc->max_samplerate) {
620 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
621 return SR_ERR_SAMPLERATE;
622 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 623 return SR_ERR_SAMPLERATE;
a1bb33af 624
43fc7885 625 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
626 devc->flag_reg |= FLAG_DEMUX;
627 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 628 } else {
fefc4b85
BV
629 devc->flag_reg &= ~FLAG_DEMUX;
630 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 631 }
a1bb33af 632
7583b99d
GM
633 /* Calculate actual samplerate used and complain if it is different
634 * from the requested.
635 */
fefc4b85
BV
636 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
637 if (devc->flag_reg & FLAG_DEMUX)
638 devc->cur_samplerate *= 2;
639 if (devc->cur_samplerate != samplerate)
133a37bf 640 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 641 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 642
e46b8fb1 643 return SR_OK;
a1bb33af
UH
644}
645
6f4b1868
BV
646static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
647 const void *value)
a1bb33af 648{
fefc4b85 649 struct dev_context *devc;
a1bb33af 650 int ret;
1b79df2f 651 const uint64_t *tmp_u64;
a1bb33af 652
fefc4b85 653 devc = sdi->priv;
a1bb33af 654
5a2326a7 655 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 656 return SR_ERR;
a1bb33af 657
ffedd0bf 658 switch (hwcap) {
5a2326a7 659 case SR_HWCAP_SAMPLERATE:
1b79df2f 660 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 661 break;
5a2326a7 662 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 663 tmp_u64 = value;
574ce498 664 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 665 return SR_ERR;
fefc4b85 666 if (*tmp_u64 > devc->max_samples)
133a37bf 667 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
668 devc->limit_samples = *tmp_u64;
669 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 670 ret = SR_OK;
a803c0db 671 break;
5a2326a7 672 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
673 devc->capture_ratio = *(const uint64_t *)value;
674 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
675 devc->capture_ratio = 0;
e46b8fb1 676 ret = SR_ERR;
43fc7885 677 } else
e46b8fb1 678 ret = SR_OK;
a803c0db 679 break;
3a4d09c0 680 case SR_HWCAP_RLE:
4d436e71 681 if (GPOINTER_TO_INT(value)) {
3a4d09c0 682 sr_info("ols: enabling RLE");
fefc4b85 683 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
684 }
685 ret = SR_OK;
686 break;
a803c0db 687 default:
e46b8fb1 688 ret = SR_ERR;
43fc7885 689 }
a1bb33af
UH
690
691 return ret;
692}
693
26bf9d56
BV
694static void abort_acquisition(const struct sr_dev_inst *sdi)
695{
696 struct sr_datafeed_packet packet;
697 struct dev_context *devc;
698
699 devc = sdi->priv;
700 sr_source_remove(devc->serial->fd);
701
702 /* Terminate session */
703 packet.type = SR_DF_END;
704 sr_session_send(sdi, &packet);
705
706}
707
708
709
1f9813eb 710static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 711{
b9c735a2 712 struct sr_datafeed_packet packet;
9c939c51 713 struct sr_datafeed_logic logic;
d68e2d1a 714 struct sr_dev_inst *sdi;
fefc4b85
BV
715 struct drv_context *drvc;
716 struct dev_context *devc;
4fe9a6da 717 GSList *l;
3a4d09c0
GM
718 int num_channels, offset, i, j;
719 unsigned char byte;
a1bb33af 720
fefc4b85
BV
721 drvc = odi->priv;
722
723 /* Find this device's devc struct by its fd. */
724 devc = NULL;
725 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 726 sdi = l->data;
fefc4b85
BV
727 devc = sdi->priv;
728 if (devc->serial->fd == fd) {
4fe9a6da
BV
729 break;
730 }
fefc4b85 731 devc = NULL;
4fe9a6da 732 }
fefc4b85 733 if (!devc)
ea9cfed7 734 /* Shouldn't happen. */
4fe9a6da
BV
735 return TRUE;
736
fefc4b85 737 if (devc->num_transfers++ == 0) {
43fc7885
UH
738 /*
739 * First time round, means the device started sending data,
740 * and will not stop until done. If it stops sending for
741 * longer than it takes to send a byte, that means it's
742 * finished. We'll double that to 30ms to be sure...
a1bb33af 743 */
6f1be0a2 744 sr_source_remove(fd);
1f9813eb 745 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
886a52b6 746 /* TODO: Check malloc return code. */
fefc4b85
BV
747 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
748 if (!devc->raw_sample_buf) {
749 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
750 __func__);
751 return FALSE;
752 }
a803c0db 753 /* fill with 1010... for debugging */
fefc4b85 754 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
755 }
756
6937bb75 757 num_channels = 0;
43fc7885 758 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 759 if ((devc->flag_reg & i) == 0)
6937bb75 760 num_channels++;
43fc7885 761 }
6937bb75 762
3a4d09c0 763 if (revents == G_IO_IN) {
2119ab03 764 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
765 return FALSE;
766
baf1d714 767 /* Ignore it if we've read enough. */
fefc4b85 768 if (devc->num_samples >= devc->limit_samples)
baf1d714 769 return TRUE;
3a4d09c0 770
fefc4b85 771 devc->sample[devc->num_bytes++] = byte;
b08024a8 772 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 773 if (devc->num_bytes == num_channels) {
43fc7885 774 /* Got a full sample. */
b08024a8 775 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
776 devc->num_bytes * 2, *(int *)devc->sample);
777 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
778 /*
779 * In RLE mode -1 should never come in as a
780 * sample, because bit 31 is the "count" flag.
43fc7885 781 */
fefc4b85
BV
782 if (devc->sample[devc->num_bytes - 1] & 0x80) {
783 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
784 /*
785 * FIXME: This will only work on
786 * little-endian systems.
a1bb33af 787 */
fefc4b85
BV
788 devc->rle_count = *(int *)(devc->sample);
789 sr_dbg("ols: RLE count = %d", devc->rle_count);
790 devc->num_bytes = 0;
3a4d09c0 791 return TRUE;
baf1d714 792 }
3a4d09c0 793 }
fefc4b85
BV
794 devc->num_samples += devc->rle_count + 1;
795 if (devc->num_samples > devc->limit_samples) {
baf1d714 796 /* Save us from overrunning the buffer. */
fefc4b85
BV
797 devc->rle_count -= devc->num_samples - devc->limit_samples;
798 devc->num_samples = devc->limit_samples;
a1bb33af
UH
799 }
800
43fc7885
UH
801 if (num_channels < 4) {
802 /*
803 * Some channel groups may have been turned
804 * off, to speed up transfer between the
805 * hardware and the PC. Expand that here before
806 * submitting it over the session bus --
807 * whatever is listening on the bus will be
808 * expecting a full 32-bit sample, based on
809 * the number of probes.
6937bb75
BV
810 */
811 j = 0;
fefc4b85 812 memset(devc->tmp_sample, 0, 4);
43fc7885 813 for (i = 0; i < 4; i++) {
fefc4b85 814 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
815 /*
816 * This channel group was
817 * enabled, copy from received
818 * sample.
819 */
fefc4b85 820 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
821 }
822 }
fefc4b85
BV
823 memcpy(devc->sample, devc->tmp_sample, 4);
824 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
825 }
826
a803c0db
BV
827 /* the OLS sends its sample buffer backwards.
828 * store it in reverse order here, so we can dump
829 * this on the session bus later.
830 */
fefc4b85
BV
831 offset = (devc->limit_samples - devc->num_samples) * 4;
832 for (i = 0; i <= devc->rle_count; i++) {
833 memcpy(devc->raw_sample_buf + offset + (i * 4),
834 devc->sample, 4);
baf1d714 835 }
fefc4b85
BV
836 memset(devc->sample, 0, 4);
837 devc->num_bytes = 0;
838 devc->rle_count = 0;
a1bb33af 839 }
43fc7885
UH
840 } else {
841 /*
842 * This is the main loop telling us a timeout was reached, or
843 * we've acquired all the samples we asked for -- we're done.
a803c0db 844 * Send the (properly-ordered) buffer to the frontend.
43fc7885 845 */
fefc4b85 846 if (devc->trigger_at != -1) {
a803c0db
BV
847 /* a trigger was set up, so we need to tell the frontend
848 * about it.
849 */
fefc4b85 850 if (devc->trigger_at > 0) {
a803c0db 851 /* there are pre-trigger samples, send those first */
5a2326a7 852 packet.type = SR_DF_LOGIC;
9c939c51 853 packet.payload = &logic;
fefc4b85 854 logic.length = devc->trigger_at * 4;
9c939c51 855 logic.unitsize = 4;
fefc4b85
BV
856 logic.data = devc->raw_sample_buf +
857 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 858 sr_session_send(cb_data, &packet);
a803c0db
BV
859 }
860
9c939c51 861 /* send the trigger */
5a2326a7 862 packet.type = SR_DF_TRIGGER;
1f9813eb 863 sr_session_send(cb_data, &packet);
a803c0db 864
9c939c51 865 /* send post-trigger samples */
5a2326a7 866 packet.type = SR_DF_LOGIC;
9c939c51 867 packet.payload = &logic;
fefc4b85 868 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 869 logic.unitsize = 4;
fefc4b85
BV
870 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
871 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 872 sr_session_send(cb_data, &packet);
a803c0db 873 } else {
9c939c51 874 /* no trigger was used */
5a2326a7 875 packet.type = SR_DF_LOGIC;
9c939c51 876 packet.payload = &logic;
fefc4b85 877 logic.length = devc->num_samples * 4;
9c939c51 878 logic.unitsize = 4;
fefc4b85
BV
879 logic.data = devc->raw_sample_buf +
880 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 881 sr_session_send(cb_data, &packet);
a803c0db 882 }
fefc4b85 883 g_free(devc->raw_sample_buf);
a803c0db 884
06d64eb8 885 serial_flush(fd);
d02a535e 886 serial_close(fd);
26bf9d56
BV
887
888 abort_acquisition(sdi);
a1bb33af
UH
889 }
890
891 return TRUE;
892}
893
5d9ed643
BV
894static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
895 void *cb_data)
a1bb33af 896{
b9c735a2
UH
897 struct sr_datafeed_packet *packet;
898 struct sr_datafeed_header *header;
f366e86c 899 struct sr_datafeed_meta_logic meta;
fefc4b85 900 struct dev_context *devc;
a803c0db 901 uint32_t trigger_config[4];
a1bb33af 902 uint32_t data;
6937bb75
BV
903 uint16_t readcount, delaycount;
904 uint8_t changrp_mask;
22130421 905 int num_channels;
4fe9a6da 906 int i;
a1bb33af 907
fefc4b85 908 devc = sdi->priv;
a1bb33af 909
5a2326a7 910 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 911 return SR_ERR;
a1bb33af 912
014359e3
BV
913 if (configure_probes(sdi) != SR_OK) {
914 sr_err("ols: failed to configured probes");
915 return SR_ERR;
916 }
917
22130421
GM
918 /*
919 * Enable/disable channel groups in the flag register according to the
baf1d714 920 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
921 * to limit readcount.
922 */
923 changrp_mask = 0;
924 num_channels = 0;
925 for (i = 0; i < 4; i++) {
fefc4b85 926 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
927 changrp_mask |= (1 << i);
928 num_channels++;
929 }
930 }
931
baf1d714
UH
932 /*
933 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
934 * buffer.
935 */
fefc4b85 936 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
937
938 memset(trigger_config, 0, 16);
fefc4b85
BV
939 trigger_config[devc->num_stages - 1] |= 0x08;
940 if (devc->trigger_mask[0]) {
941 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
942 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 943
fefc4b85
BV
944 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
945 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 946 return SR_ERR;
fefc4b85
BV
947 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
948 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 949 return SR_ERR;
fefc4b85 950 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
951 trigger_config[0]) != SR_OK)
952 return SR_ERR;
6937bb75 953
fefc4b85
BV
954 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_1,
955 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 956 return SR_ERR;
fefc4b85
BV
957 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_1,
958 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 959 return SR_ERR;
fefc4b85 960 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
961 trigger_config[1]) != SR_OK)
962 return SR_ERR;
6937bb75 963
fefc4b85
BV
964 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_2,
965 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 966 return SR_ERR;
fefc4b85
BV
967 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_2,
968 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 969 return SR_ERR;
fefc4b85 970 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
971 trigger_config[2]) != SR_OK)
972 return SR_ERR;
a803c0db 973
fefc4b85
BV
974 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_3,
975 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 976 return SR_ERR;
fefc4b85
BV
977 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_3,
978 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 979 return SR_ERR;
fefc4b85 980 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
981 trigger_config[3]) != SR_OK)
982 return SR_ERR;
6937bb75 983 } else {
fefc4b85
BV
984 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_MASK_0,
985 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 986 return SR_ERR;
fefc4b85
BV
987 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_VALUE_0,
988 devc->trigger_value[0]) != SR_OK)
e46b8fb1 989 return SR_ERR;
fefc4b85 990 if (send_longcommand(devc->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
991 0x00000008) != SR_OK)
992 return SR_ERR;
a803c0db 993 delaycount = readcount;
6937bb75 994 }
a1bb33af 995
b08024a8 996 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
997 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
998 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
999 if (send_longcommand(devc->serial->fd, CMD_SET_DIVIDER,
1000 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 1001 return SR_ERR;
a1bb33af 1002
43fc7885 1003 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
1004 data = ((readcount - 1) & 0xffff) << 16;
1005 data |= (delaycount - 1) & 0xffff;
fefc4b85 1006 if (send_longcommand(devc->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 1007 return SR_ERR;
a1bb33af 1008
43fc7885 1009 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
1010 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
1011 devc->flag_reg |= FLAG_FILTER;
1012 devc->rle_count = 0;
1013 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
1014 if (send_longcommand(devc->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 1015 return SR_ERR;
a1bb33af 1016
43fc7885 1017 /* Start acquisition on the device. */
fefc4b85 1018 if (send_shortcommand(devc->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 1019 return SR_ERR;
a1bb33af 1020
fefc4b85 1021 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1022 cb_data);
a1bb33af 1023
b53738ba
UH
1024 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1025 sr_err("ols: %s: packet malloc failed", __func__);
1026 return SR_ERR_MALLOC;
1027 }
1028
1029 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1030 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1031 g_free(packet);
b53738ba
UH
1032 return SR_ERR_MALLOC;
1033 }
1034
43fc7885 1035 /* Send header packet to the session bus. */
5a2326a7 1036 packet->type = SR_DF_HEADER;
43fc7885 1037 packet->payload = (unsigned char *)header;
a1bb33af
UH
1038 header->feed_version = 1;
1039 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1040 sr_session_send(cb_data, packet);
1041
1042 /* Send metadata about the SR_DF_LOGIC packets to come. */
1043 packet->type = SR_DF_META_LOGIC;
1044 packet->payload = &meta;
fefc4b85 1045 meta.samplerate = devc->cur_samplerate;
f366e86c 1046 meta.num_probes = NUM_PROBES;
3cd3a20b 1047 sr_session_send(cb_data, packet);
c0a4b971 1048
a1bb33af
UH
1049 g_free(header);
1050 g_free(packet);
1051
e46b8fb1 1052 return SR_OK;
a1bb33af
UH
1053}
1054
3cd3a20b 1055/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
69b07d14 1056static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
a1bb33af 1057{
17e1afcb 1058 /* Avoid compiler warnings. */
26bf9d56 1059 (void)cb_data;
afc8e4de 1060
26bf9d56 1061 abort_acquisition(sdi);
3010f21c
UH
1062
1063 return SR_OK;
a1bb33af
UH
1064}
1065
c09f0b57 1066SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1067 .name = "ols",
1068 .longname = "Openbench Logic Sniffer",
1069 .api_version = 1,
1070 .init = hw_init,
1071 .cleanup = hw_cleanup,
61136ea6 1072 .scan = hw_scan,
811deee4
BV
1073 .dev_list = hw_dev_list,
1074 .dev_clear = hw_cleanup,
e7eb703f
UH
1075 .dev_open = hw_dev_open,
1076 .dev_close = hw_dev_close,
dddfb3db 1077 .info_get = hw_info_get,
a9a245b4 1078 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1079 .dev_acquisition_start = hw_dev_acquisition_start,
1080 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1081 .priv = NULL,
a1bb33af 1082};