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ols: if no serial port specified, this driver is not used.
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
fe1c50fb
BV
49#define SERIALCOMM "115200/8n1"
50
915f7cc8 51static const int hwcaps[] = {
5a2326a7
UH
52 SR_HWCAP_LOGIC_ANALYZER,
53 SR_HWCAP_SAMPLERATE,
54 SR_HWCAP_CAPTURE_RATIO,
55 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 56 SR_HWCAP_RLE,
43fc7885 57 0,
a1bb33af
UH
58};
59
d261dbbf 60/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 61static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
62 "0",
63 "1",
64 "2",
65 "3",
66 "4",
67 "5",
68 "6",
69 "7",
70 "8",
71 "9",
72 "10",
73 "11",
74 "12",
75 "13",
76 "14",
77 "15",
78 "16",
79 "17",
80 "18",
81 "19",
82 "20",
83 "21",
84 "22",
85 "23",
86 "24",
87 "25",
88 "26",
89 "27",
90 "28",
91 "29",
92 "30",
93 "31",
94 NULL,
95};
96
4fe9a6da 97/* default supported samplerates, can be overridden by device metadata */
a533743d 98static const struct sr_samplerates samplerates = {
c9140419 99 SR_HZ(10),
59df0c77 100 SR_MHZ(200),
c9140419
UH
101 SR_HZ(1),
102 NULL,
a1bb33af
UH
103};
104
e5e81856
BV
105SR_PRIV struct sr_dev_driver ols_driver_info;
106static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 107
530f201e
BV
108static int send_shortcommand(struct sr_serial_dev_inst *serial,
109 uint8_t command)
a1bb33af
UH
110{
111 char buf[1];
112
b08024a8 113 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 114 buf[0] = command;
530f201e 115 if (serial_write(serial, buf, 1) != 1)
e46b8fb1 116 return SR_ERR;
a1bb33af 117
e46b8fb1 118 return SR_OK;
a1bb33af
UH
119}
120
530f201e
BV
121static int send_longcommand(struct sr_serial_dev_inst *serial,
122 uint8_t command, uint32_t data)
a1bb33af
UH
123{
124 char buf[5];
125
b08024a8 126 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 127 buf[0] = command;
6937bb75
BV
128 buf[1] = (data & 0xff000000) >> 24;
129 buf[2] = (data & 0xff0000) >> 16;
130 buf[3] = (data & 0xff00) >> 8;
131 buf[4] = data & 0xff;
530f201e 132 if (serial_write(serial, buf, 5) != 5)
e46b8fb1 133 return SR_ERR;
a1bb33af 134
e46b8fb1 135 return SR_OK;
a1bb33af
UH
136}
137
014359e3 138static int configure_probes(const struct sr_dev_inst *sdi)
a1bb33af 139{
014359e3 140 struct dev_context *devc;
1b79df2f
JH
141 const struct sr_probe *probe;
142 const GSList *l;
6937bb75 143 int probe_bit, stage, i;
a1bb33af
UH
144 char *tc;
145
014359e3
BV
146 devc = sdi->priv;
147
fefc4b85 148 devc->probe_mask = 0;
43fc7885 149 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
fefc4b85
BV
150 devc->trigger_mask[i] = 0;
151 devc->trigger_value[i] = 0;
a1bb33af
UH
152 }
153
fefc4b85 154 devc->num_stages = 0;
014359e3 155 for (l = sdi->probes; l; l = l->next) {
1b79df2f 156 probe = (const struct sr_probe *)l->data;
43fc7885 157 if (!probe->enabled)
6937bb75
BV
158 continue;
159
43fc7885
UH
160 /*
161 * Set up the probe mask for later configuration into the
162 * flag register.
163 */
b35c8293 164 probe_bit = 1 << (probe->index);
fefc4b85 165 devc->probe_mask |= probe_bit;
6937bb75 166
a803c0db 167 if (!probe->trigger)
6937bb75
BV
168 continue;
169
43fc7885 170 /* Configure trigger mask and value. */
6937bb75 171 stage = 0;
43fc7885 172 for (tc = probe->trigger; tc && *tc; tc++) {
fefc4b85 173 devc->trigger_mask[stage] |= probe_bit;
43fc7885 174 if (*tc == '1')
fefc4b85 175 devc->trigger_value[stage] |= probe_bit;
6937bb75 176 stage++;
43fc7885
UH
177 if (stage > 3)
178 /*
179 * TODO: Only supporting parallel mode, with
180 * up to 4 stages.
181 */
e46b8fb1 182 return SR_ERR;
a1bb33af 183 }
fefc4b85
BV
184 if (stage > devc->num_stages)
185 devc->num_stages = stage;
a1bb33af
UH
186 }
187
e46b8fb1 188 return SR_OK;
a1bb33af
UH
189}
190
a803c0db 191static uint32_t reverse16(uint32_t in)
6937bb75
BV
192{
193 uint32_t out;
194
a803c0db
BV
195 out = (in & 0xff) << 8;
196 out |= (in & 0xff00) >> 8;
197 out |= (in & 0xff0000) << 8;
198 out |= (in & 0xff000000) >> 8;
199
200 return out;
201}
202
203static uint32_t reverse32(uint32_t in)
204{
205 uint32_t out;
206
207 out = (in & 0xff) << 24;
208 out |= (in & 0xff00) << 8;
209 out |= (in & 0xff0000) >> 8;
210 out |= (in & 0xff000000) >> 24;
211
212 return out;
6937bb75
BV
213}
214
fefc4b85 215static struct dev_context *ols_dev_new(void)
4fe9a6da 216{
fefc4b85 217 struct dev_context *devc;
4fe9a6da 218
fefc4b85
BV
219 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
220 sr_err("ols: %s: devc malloc failed", __func__);
b53738ba
UH
221 return NULL;
222 }
223
fefc4b85
BV
224 devc->trigger_at = -1;
225 devc->probe_mask = 0xffffffff;
226 devc->cur_samplerate = SR_KHZ(200);
227 devc->serial = NULL;
4fe9a6da 228
fefc4b85 229 return devc;
4fe9a6da
BV
230}
231
530f201e 232static struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial)
4fe9a6da 233{
d68e2d1a 234 struct sr_dev_inst *sdi;
fefc4b85 235 struct dev_context *devc;
10e5cbed
BV
236 struct sr_probe *probe;
237 uint32_t tmp_int, ui;
4fe9a6da 238 uint8_t key, type, token;
bb7ef793 239 GString *tmp_str, *devname, *version;
10e5cbed 240 guchar tmp_c;
4fe9a6da 241
d3683c42 242 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 243 sdi->driver = odi;
fefc4b85
BV
244 devc = ols_dev_new();
245 sdi->priv = devc;
4fe9a6da 246
bb7ef793 247 devname = g_string_new("");
4fe9a6da
BV
248 version = g_string_new("");
249
250 key = 0xff;
251 while (key) {
530f201e 252 if (serial_read(serial, &key, 1) != 1 || key == 0x00)
4fe9a6da
BV
253 break;
254 type = key >> 5;
255 token = key & 0x1f;
256 switch (type) {
257 case 0:
258 /* NULL-terminated string */
259 tmp_str = g_string_new("");
530f201e 260 while (serial_read(serial, &tmp_c, 1) == 1 && tmp_c != '\0')
4fe9a6da 261 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
262 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
263 key, tmp_str->str);
4fe9a6da
BV
264 switch (token) {
265 case 0x01:
266 /* Device name */
bb7ef793 267 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
268 break;
269 case 0x02:
270 /* FPGA firmware version */
271 if (version->len)
272 g_string_append(version, ", ");
273 g_string_append(version, "FPGA version ");
274 g_string_append(version, tmp_str->str);
275 break;
276 case 0x03:
277 /* Ancillary version */
278 if (version->len)
279 g_string_append(version, ", ");
280 g_string_append(version, "Ancillary version ");
281 g_string_append(version, tmp_str->str);
282 break;
283 default:
b08024a8
UH
284 sr_info("ols: unknown token 0x%.2x: '%s'",
285 token, tmp_str->str);
4fe9a6da
BV
286 break;
287 }
288 g_string_free(tmp_str, TRUE);
289 break;
290 case 1:
291 /* 32-bit unsigned integer */
530f201e 292 if (serial_read(serial, &tmp_int, 4) != 4)
4fe9a6da
BV
293 break;
294 tmp_int = reverse32(tmp_int);
b08024a8
UH
295 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
296 key, tmp_int);
4fe9a6da
BV
297 switch (token) {
298 case 0x00:
299 /* Number of usable probes */
10e5cbed
BV
300 for (ui = 0; ui < tmp_int; ui++) {
301 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
302 probe_names[ui])))
303 return 0;
304 sdi->probes = g_slist_append(sdi->probes, probe);
305 }
4fe9a6da
BV
306 break;
307 case 0x01:
308 /* Amount of sample memory available (bytes) */
fefc4b85 309 devc->max_samples = tmp_int;
4fe9a6da
BV
310 break;
311 case 0x02:
312 /* Amount of dynamic memory available (bytes) */
313 /* what is this for? */
314 break;
315 case 0x03:
316 /* Maximum sample rate (hz) */
fefc4b85 317 devc->max_samplerate = tmp_int;
4fe9a6da
BV
318 break;
319 case 0x04:
320 /* protocol version */
fefc4b85 321 devc->protocol_version = tmp_int;
4fe9a6da
BV
322 break;
323 default:
b08024a8
UH
324 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
325 token, tmp_int);
4fe9a6da
BV
326 break;
327 }
328 break;
329 case 2:
330 /* 8-bit unsigned integer */
530f201e 331 if (serial_read(serial, &tmp_c, 1) != 1)
4fe9a6da 332 break;
b08024a8
UH
333 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
334 key, tmp_c);
4fe9a6da
BV
335 switch (token) {
336 case 0x00:
337 /* Number of usable probes */
10e5cbed
BV
338 for (ui = 0; ui < tmp_c; ui++) {
339 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
340 probe_names[ui])))
341 return 0;
342 sdi->probes = g_slist_append(sdi->probes, probe);
343 }
4fe9a6da
BV
344 break;
345 case 0x01:
346 /* protocol version */
fefc4b85 347 devc->protocol_version = tmp_c;
4fe9a6da
BV
348 break;
349 default:
b08024a8
UH
350 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
351 token, tmp_c);
4fe9a6da
BV
352 break;
353 }
354 break;
355 default:
356 /* unknown type */
357 break;
358 }
359 }
360
bb7ef793 361 sdi->model = devname->str;
4fe9a6da 362 sdi->version = version->str;
bb7ef793 363 g_string_free(devname, FALSE);
4fe9a6da
BV
364 g_string_free(version, FALSE);
365
366 return sdi;
367}
368
40dda2c3 369static int hw_init(void)
61136ea6 370{
fefc4b85 371 struct drv_context *drvc;
61136ea6 372
fefc4b85
BV
373 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
374 sr_err("ols: driver context malloc failed.");
886a52b6 375 return SR_ERR_MALLOC;
fefc4b85
BV
376 }
377 odi->priv = drvc;
61136ea6
BV
378
379 return SR_OK;
380}
381
10e5cbed 382static GSList *hw_scan(GSList *options)
a1bb33af 383{
a99e0d2a 384 struct sr_hwopt *opt;
d68e2d1a 385 struct sr_dev_inst *sdi;
fefc4b85
BV
386 struct drv_context *drvc;
387 struct dev_context *devc;
10e5cbed 388 struct sr_probe *probe;
530f201e 389 struct sr_serial_dev_inst *serial;
a99e0d2a 390 GPollFD probefd;
fe1c50fb 391 GSList *l, *devices;
530f201e 392 int ret, i;
fe1c50fb 393 const char *conn, *serialcomm;
a99e0d2a 394 char buf[8];
a1bb33af 395
10e5cbed 396 (void)options;
fefc4b85 397 drvc = odi->priv;
10e5cbed 398 devices = NULL;
c0a4b971 399
a99e0d2a
AG
400 conn = serialcomm = NULL;
401 for (l = options; l; l = l->next) {
402 opt = l->data;
403 switch (opt->hwopt) {
404 case SR_HWOPT_CONN:
405 conn = opt->value;
406 break;
407 case SR_HWOPT_SERIALCOMM:
408 serialcomm = opt->value;
409 break;
410 }
411 }
90165efe 412 if (!conn)
a99e0d2a 413 return NULL;
c0a4b971 414
fe1c50fb 415 if (serialcomm == NULL)
530f201e
BV
416 serialcomm = SERIALCOMM;
417
418 if (!(serial = sr_serial_dev_inst_new(conn, serialcomm)))
419 return NULL;
c0a4b971 420
a99e0d2a
AG
421 /* The discovery procedure is like this: first send the Reset
422 * command (0x00) 5 times, since the device could be anywhere
423 * in a 5-byte command. Then send the ID command (0x02).
424 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
425 * have a match.
a99e0d2a
AG
426 */
427 sr_info("ols: probing %s .", conn);
530f201e 428 if (serial_open(serial, O_RDWR | O_NONBLOCK) != SR_OK)
a99e0d2a 429 return NULL;
c0a4b971 430
a99e0d2a
AG
431 ret = SR_OK;
432 for (i = 0; i < 5; i++) {
530f201e 433 if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
a99e0d2a 434 sr_err("ols: port %s is not writable.", conn);
fe1c50fb 435 break;
a1bb33af
UH
436 }
437 }
a99e0d2a 438 if (ret != SR_OK) {
530f201e 439 serial_close(serial);
a99e0d2a
AG
440 sr_err("ols: Could not use port %s. Quitting.", conn);
441 return NULL;
442 }
530f201e 443 send_shortcommand(serial, CMD_ID);
a1bb33af 444
fe1c50fb 445 /* Wait 10ms for a response. */
5b15b41e 446 usleep(10000);
a1bb33af 447
530f201e 448 probefd.fd = serial->fd;
fe1c50fb
BV
449 probefd.events = G_IO_IN;
450 g_poll(&probefd, 1, 1);
4fe9a6da 451
a99e0d2a
AG
452 if (probefd.revents != G_IO_IN)
453 return NULL;
530f201e 454 if (serial_read(serial, buf, 4) != 4)
a99e0d2a
AG
455 return NULL;
456 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
457 return NULL;
4fe9a6da 458
fe1c50fb
BV
459 /* Definitely using the OLS protocol, check if it supports
460 * the metadata command.
a99e0d2a 461 */
530f201e 462 send_shortcommand(serial, CMD_METADATA);
a99e0d2a 463 if (g_poll(&probefd, 1, 10) > 0) {
fe1c50fb 464 /* Got metadata. */
530f201e 465 sdi = get_metadata(serial);
fe1c50fb 466 sdi->index = 0;
a99e0d2a
AG
467 devc = sdi->priv;
468 } else {
fe1c50fb
BV
469 /* Not an OLS -- some other board that uses the sump protocol. */
470 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE,
a99e0d2a
AG
471 "Sump", "Logic Analyzer", "v1.0");
472 sdi->driver = odi;
473 devc = ols_dev_new();
474 for (i = 0; i < 32; i++) {
475 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
476 probe_names[i])))
477 return 0;
478 sdi->probes = g_slist_append(sdi->probes, probe);
a1bb33af 479 }
a99e0d2a 480 sdi->priv = devc;
4fe9a6da 481 }
530f201e 482 devc->serial = serial;
a99e0d2a
AG
483 drvc->instances = g_slist_append(drvc->instances, sdi);
484 devices = g_slist_append(devices, sdi);
485
530f201e 486 serial_close(serial);
a1bb33af 487
10e5cbed 488 return devices;
a1bb33af
UH
489}
490
811deee4
BV
491static GSList *hw_dev_list(void)
492{
493 struct drv_context *drvc;
494
495 drvc = odi->priv;
496
497 return drvc->instances;
498}
499
25a0f108 500static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 501{
fefc4b85 502 struct dev_context *devc;
a1bb33af 503
fefc4b85 504 devc = sdi->priv;
69890f73 505
530f201e 506 if (serial_open(devc->serial, O_RDWR) != SR_OK)
e46b8fb1 507 return SR_ERR;
a1bb33af 508
5a2326a7 509 sdi->status = SR_ST_ACTIVE;
a1bb33af 510
e46b8fb1 511 return SR_OK;
a1bb33af
UH
512}
513
25a0f108 514static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 515{
fefc4b85 516 struct dev_context *devc;
a1bb33af 517
fefc4b85 518 devc = sdi->priv;
69890f73 519
530f201e
BV
520 if (devc->serial && devc->serial->fd != -1) {
521 serial_close(devc->serial);
5a2326a7 522 sdi->status = SR_ST_INACTIVE;
a1bb33af 523 }
697785d1
UH
524
525 return SR_OK;
a1bb33af
UH
526}
527
57ab7d9f 528static int hw_cleanup(void)
a1bb33af
UH
529{
530 GSList *l;
d68e2d1a 531 struct sr_dev_inst *sdi;
fefc4b85
BV
532 struct drv_context *drvc;
533 struct dev_context *devc;
57ab7d9f 534 int ret = SR_OK;
a1bb33af 535
fefc4b85
BV
536 if (!(drvc = odi->priv))
537 return SR_OK;
538
8722c31e 539 /* Properly close and free all devices. */
fefc4b85 540 for (l = drvc->instances; l; l = l->next) {
57ab7d9f
UH
541 if (!(sdi = l->data)) {
542 /* Log error, but continue cleaning up the rest. */
543 sr_err("ols: %s: sdi was NULL, continuing", __func__);
544 ret = SR_ERR_BUG;
545 continue;
546 }
fefc4b85 547 if (!(devc = sdi->priv)) {
57ab7d9f
UH
548 /* Log error, but continue cleaning up the rest. */
549 sr_err("ols: %s: sdi->priv was NULL, continuing",
550 __func__);
551 ret = SR_ERR_BUG;
552 continue;
553 }
530f201e 554 hw_dev_close(sdi);
fefc4b85 555 sr_serial_dev_inst_free(devc->serial);
d3683c42 556 sr_dev_inst_free(sdi);
a1bb33af 557 }
fefc4b85
BV
558 g_slist_free(drvc->instances);
559 drvc->instances = NULL;
57ab7d9f
UH
560
561 return ret;
a1bb33af
UH
562}
563
dddfb3db
BV
564static int hw_info_get(int info_id, const void **data,
565 const struct sr_dev_inst *sdi)
a1bb33af 566{
fefc4b85 567 struct dev_context *devc;
a1bb33af 568
dddfb3db 569 switch (info_id) {
2ca4465b
BV
570 case SR_DI_HWCAPS:
571 *data = hwcaps;
572 break;
5a2326a7 573 case SR_DI_NUM_PROBES:
dddfb3db 574 *data = GINT_TO_POINTER(1);
a1bb33af 575 break;
464d12c7 576 case SR_DI_PROBE_NAMES:
dddfb3db 577 *data = probe_names;
464d12c7 578 break;
5a2326a7 579 case SR_DI_SAMPLERATES:
dddfb3db 580 *data = &samplerates;
a1bb33af 581 break;
5a2326a7 582 case SR_DI_TRIGGER_TYPES:
dddfb3db 583 *data = (char *)TRIGGER_TYPES;
a1bb33af 584 break;
5a2326a7 585 case SR_DI_CUR_SAMPLERATE:
dddfb3db 586 if (sdi) {
fefc4b85
BV
587 devc = sdi->priv;
588 *data = &devc->cur_samplerate;
dddfb3db
BV
589 } else
590 return SR_ERR;
a1bb33af 591 break;
dddfb3db
BV
592 default:
593 return SR_ERR_ARG;
a1bb33af
UH
594 }
595
dddfb3db 596 return SR_OK;
a1bb33af
UH
597}
598
6f4b1868 599static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 600{
fefc4b85 601 struct dev_context *devc;
a1bb33af 602
fefc4b85
BV
603 devc = sdi->priv;
604 if (devc->max_samplerate) {
605 if (samplerate > devc->max_samplerate)
4fe9a6da
BV
606 return SR_ERR_SAMPLERATE;
607 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 608 return SR_ERR_SAMPLERATE;
a1bb33af 609
43fc7885 610 if (samplerate > CLOCK_RATE) {
fefc4b85
BV
611 devc->flag_reg |= FLAG_DEMUX;
612 devc->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 613 } else {
fefc4b85
BV
614 devc->flag_reg &= ~FLAG_DEMUX;
615 devc->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 616 }
a1bb33af 617
7583b99d
GM
618 /* Calculate actual samplerate used and complain if it is different
619 * from the requested.
620 */
fefc4b85
BV
621 devc->cur_samplerate = CLOCK_RATE / (devc->cur_samplerate_divider + 1);
622 if (devc->flag_reg & FLAG_DEMUX)
623 devc->cur_samplerate *= 2;
624 if (devc->cur_samplerate != samplerate)
133a37bf 625 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
fefc4b85 626 PRIu64, samplerate, devc->cur_samplerate);
7583b99d 627
e46b8fb1 628 return SR_OK;
a1bb33af
UH
629}
630
6f4b1868
BV
631static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
632 const void *value)
a1bb33af 633{
fefc4b85 634 struct dev_context *devc;
a1bb33af 635 int ret;
1b79df2f 636 const uint64_t *tmp_u64;
a1bb33af 637
fefc4b85 638 devc = sdi->priv;
a1bb33af 639
5a2326a7 640 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 641 return SR_ERR;
a1bb33af 642
ffedd0bf 643 switch (hwcap) {
5a2326a7 644 case SR_HWCAP_SAMPLERATE:
1b79df2f 645 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 646 break;
5a2326a7 647 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 648 tmp_u64 = value;
574ce498 649 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 650 return SR_ERR;
fefc4b85 651 if (*tmp_u64 > devc->max_samples)
133a37bf 652 sr_err("ols: sample limit exceeds hw max");
fefc4b85
BV
653 devc->limit_samples = *tmp_u64;
654 sr_info("ols: sample limit %" PRIu64, devc->limit_samples);
e46b8fb1 655 ret = SR_OK;
a803c0db 656 break;
5a2326a7 657 case SR_HWCAP_CAPTURE_RATIO:
fefc4b85
BV
658 devc->capture_ratio = *(const uint64_t *)value;
659 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
660 devc->capture_ratio = 0;
e46b8fb1 661 ret = SR_ERR;
43fc7885 662 } else
e46b8fb1 663 ret = SR_OK;
a803c0db 664 break;
3a4d09c0 665 case SR_HWCAP_RLE:
4d436e71 666 if (GPOINTER_TO_INT(value)) {
3a4d09c0 667 sr_info("ols: enabling RLE");
fefc4b85 668 devc->flag_reg |= FLAG_RLE;
3a4d09c0
GM
669 }
670 ret = SR_OK;
671 break;
a803c0db 672 default:
e46b8fb1 673 ret = SR_ERR;
43fc7885 674 }
a1bb33af
UH
675
676 return ret;
677}
678
26bf9d56
BV
679static void abort_acquisition(const struct sr_dev_inst *sdi)
680{
681 struct sr_datafeed_packet packet;
682 struct dev_context *devc;
683
684 devc = sdi->priv;
685 sr_source_remove(devc->serial->fd);
686
687 /* Terminate session */
688 packet.type = SR_DF_END;
689 sr_session_send(sdi, &packet);
690
691}
692
693
694
1f9813eb 695static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 696{
b9c735a2 697 struct sr_datafeed_packet packet;
9c939c51 698 struct sr_datafeed_logic logic;
d68e2d1a 699 struct sr_dev_inst *sdi;
fefc4b85
BV
700 struct drv_context *drvc;
701 struct dev_context *devc;
4fe9a6da 702 GSList *l;
3a4d09c0
GM
703 int num_channels, offset, i, j;
704 unsigned char byte;
a1bb33af 705
fefc4b85
BV
706 drvc = odi->priv;
707
708 /* Find this device's devc struct by its fd. */
709 devc = NULL;
710 for (l = drvc->instances; l; l = l->next) {
4fe9a6da 711 sdi = l->data;
fefc4b85 712 devc = sdi->priv;
530f201e 713 if (devc->serial->fd == fd)
4fe9a6da 714 break;
fefc4b85 715 devc = NULL;
4fe9a6da 716 }
fefc4b85 717 if (!devc)
ea9cfed7 718 /* Shouldn't happen. */
4fe9a6da
BV
719 return TRUE;
720
fefc4b85 721 if (devc->num_transfers++ == 0) {
43fc7885
UH
722 /*
723 * First time round, means the device started sending data,
724 * and will not stop until done. If it stops sending for
725 * longer than it takes to send a byte, that means it's
726 * finished. We'll double that to 30ms to be sure...
a1bb33af 727 */
6f1be0a2 728 sr_source_remove(fd);
1f9813eb 729 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
886a52b6 730 /* TODO: Check malloc return code. */
fefc4b85
BV
731 devc->raw_sample_buf = g_try_malloc(devc->limit_samples * 4);
732 if (!devc->raw_sample_buf) {
733 sr_err("ols: %s: devc->raw_sample_buf malloc failed",
c0a4b971
UH
734 __func__);
735 return FALSE;
736 }
a803c0db 737 /* fill with 1010... for debugging */
fefc4b85 738 memset(devc->raw_sample_buf, 0x82, devc->limit_samples * 4);
a1bb33af
UH
739 }
740
6937bb75 741 num_channels = 0;
43fc7885 742 for (i = 0x20; i > 0x02; i /= 2) {
fefc4b85 743 if ((devc->flag_reg & i) == 0)
6937bb75 744 num_channels++;
43fc7885 745 }
6937bb75 746
3a4d09c0 747 if (revents == G_IO_IN) {
530f201e 748 if (serial_read(devc->serial, &byte, 1) != 1)
a1bb33af
UH
749 return FALSE;
750
baf1d714 751 /* Ignore it if we've read enough. */
fefc4b85 752 if (devc->num_samples >= devc->limit_samples)
baf1d714 753 return TRUE;
3a4d09c0 754
fefc4b85 755 devc->sample[devc->num_bytes++] = byte;
b08024a8 756 sr_dbg("ols: received byte 0x%.2x", byte);
fefc4b85 757 if (devc->num_bytes == num_channels) {
43fc7885 758 /* Got a full sample. */
b08024a8 759 sr_dbg("ols: received sample 0x%.*x",
fefc4b85
BV
760 devc->num_bytes * 2, *(int *)devc->sample);
761 if (devc->flag_reg & FLAG_RLE) {
43fc7885
UH
762 /*
763 * In RLE mode -1 should never come in as a
764 * sample, because bit 31 is the "count" flag.
43fc7885 765 */
fefc4b85
BV
766 if (devc->sample[devc->num_bytes - 1] & 0x80) {
767 devc->sample[devc->num_bytes - 1] &= 0x7f;
baf1d714
UH
768 /*
769 * FIXME: This will only work on
770 * little-endian systems.
a1bb33af 771 */
fefc4b85
BV
772 devc->rle_count = *(int *)(devc->sample);
773 sr_dbg("ols: RLE count = %d", devc->rle_count);
774 devc->num_bytes = 0;
3a4d09c0 775 return TRUE;
baf1d714 776 }
3a4d09c0 777 }
fefc4b85
BV
778 devc->num_samples += devc->rle_count + 1;
779 if (devc->num_samples > devc->limit_samples) {
baf1d714 780 /* Save us from overrunning the buffer. */
fefc4b85
BV
781 devc->rle_count -= devc->num_samples - devc->limit_samples;
782 devc->num_samples = devc->limit_samples;
a1bb33af
UH
783 }
784
43fc7885
UH
785 if (num_channels < 4) {
786 /*
787 * Some channel groups may have been turned
788 * off, to speed up transfer between the
789 * hardware and the PC. Expand that here before
790 * submitting it over the session bus --
791 * whatever is listening on the bus will be
792 * expecting a full 32-bit sample, based on
793 * the number of probes.
6937bb75
BV
794 */
795 j = 0;
fefc4b85 796 memset(devc->tmp_sample, 0, 4);
43fc7885 797 for (i = 0; i < 4; i++) {
fefc4b85 798 if (((devc->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
799 /*
800 * This channel group was
801 * enabled, copy from received
802 * sample.
803 */
fefc4b85 804 devc->tmp_sample[i] = devc->sample[j++];
6937bb75
BV
805 }
806 }
fefc4b85
BV
807 memcpy(devc->sample, devc->tmp_sample, 4);
808 sr_dbg("ols: full sample 0x%.8x", *(int *)devc->sample);
6937bb75
BV
809 }
810
a803c0db
BV
811 /* the OLS sends its sample buffer backwards.
812 * store it in reverse order here, so we can dump
813 * this on the session bus later.
814 */
fefc4b85
BV
815 offset = (devc->limit_samples - devc->num_samples) * 4;
816 for (i = 0; i <= devc->rle_count; i++) {
817 memcpy(devc->raw_sample_buf + offset + (i * 4),
818 devc->sample, 4);
baf1d714 819 }
fefc4b85
BV
820 memset(devc->sample, 0, 4);
821 devc->num_bytes = 0;
822 devc->rle_count = 0;
a1bb33af 823 }
43fc7885
UH
824 } else {
825 /*
826 * This is the main loop telling us a timeout was reached, or
827 * we've acquired all the samples we asked for -- we're done.
a803c0db 828 * Send the (properly-ordered) buffer to the frontend.
43fc7885 829 */
fefc4b85 830 if (devc->trigger_at != -1) {
a803c0db
BV
831 /* a trigger was set up, so we need to tell the frontend
832 * about it.
833 */
fefc4b85 834 if (devc->trigger_at > 0) {
a803c0db 835 /* there are pre-trigger samples, send those first */
5a2326a7 836 packet.type = SR_DF_LOGIC;
9c939c51 837 packet.payload = &logic;
fefc4b85 838 logic.length = devc->trigger_at * 4;
9c939c51 839 logic.unitsize = 4;
fefc4b85
BV
840 logic.data = devc->raw_sample_buf +
841 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 842 sr_session_send(cb_data, &packet);
a803c0db
BV
843 }
844
9c939c51 845 /* send the trigger */
5a2326a7 846 packet.type = SR_DF_TRIGGER;
1f9813eb 847 sr_session_send(cb_data, &packet);
a803c0db 848
9c939c51 849 /* send post-trigger samples */
5a2326a7 850 packet.type = SR_DF_LOGIC;
9c939c51 851 packet.payload = &logic;
fefc4b85 852 logic.length = (devc->num_samples * 4) - (devc->trigger_at * 4);
9c939c51 853 logic.unitsize = 4;
fefc4b85
BV
854 logic.data = devc->raw_sample_buf + devc->trigger_at * 4 +
855 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 856 sr_session_send(cb_data, &packet);
a803c0db 857 } else {
9c939c51 858 /* no trigger was used */
5a2326a7 859 packet.type = SR_DF_LOGIC;
9c939c51 860 packet.payload = &logic;
fefc4b85 861 logic.length = devc->num_samples * 4;
9c939c51 862 logic.unitsize = 4;
fefc4b85
BV
863 logic.data = devc->raw_sample_buf +
864 (devc->limit_samples - devc->num_samples) * 4;
1f9813eb 865 sr_session_send(cb_data, &packet);
a803c0db 866 }
fefc4b85 867 g_free(devc->raw_sample_buf);
a803c0db 868
530f201e 869 serial_flush(devc->serial);
26bf9d56 870 abort_acquisition(sdi);
530f201e 871 serial_close(devc->serial);
a1bb33af
UH
872 }
873
874 return TRUE;
875}
876
5d9ed643
BV
877static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
878 void *cb_data)
a1bb33af 879{
b9c735a2
UH
880 struct sr_datafeed_packet *packet;
881 struct sr_datafeed_header *header;
f366e86c 882 struct sr_datafeed_meta_logic meta;
fefc4b85 883 struct dev_context *devc;
a803c0db 884 uint32_t trigger_config[4];
a1bb33af 885 uint32_t data;
6937bb75
BV
886 uint16_t readcount, delaycount;
887 uint8_t changrp_mask;
22130421 888 int num_channels;
4fe9a6da 889 int i;
a1bb33af 890
fefc4b85 891 devc = sdi->priv;
a1bb33af 892
5a2326a7 893 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 894 return SR_ERR;
a1bb33af 895
014359e3
BV
896 if (configure_probes(sdi) != SR_OK) {
897 sr_err("ols: failed to configured probes");
898 return SR_ERR;
899 }
900
22130421
GM
901 /*
902 * Enable/disable channel groups in the flag register according to the
baf1d714 903 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
904 * to limit readcount.
905 */
906 changrp_mask = 0;
907 num_channels = 0;
908 for (i = 0; i < 4; i++) {
fefc4b85 909 if (devc->probe_mask & (0xff << (i * 8))) {
22130421
GM
910 changrp_mask |= (1 << i);
911 num_channels++;
912 }
913 }
914
baf1d714
UH
915 /*
916 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
917 * buffer.
918 */
fefc4b85 919 readcount = MIN(devc->max_samples / num_channels, devc->limit_samples) / 4;
a803c0db
BV
920
921 memset(trigger_config, 0, 16);
fefc4b85
BV
922 trigger_config[devc->num_stages - 1] |= 0x08;
923 if (devc->trigger_mask[0]) {
924 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
925 devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
a803c0db 926
530f201e 927 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 928 reverse32(devc->trigger_mask[0])) != SR_OK)
e46b8fb1 929 return SR_ERR;
530f201e 930 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 931 reverse32(devc->trigger_value[0])) != SR_OK)
e46b8fb1 932 return SR_ERR;
530f201e 933 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
934 trigger_config[0]) != SR_OK)
935 return SR_ERR;
6937bb75 936
530f201e 937 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_1,
fefc4b85 938 reverse32(devc->trigger_mask[1])) != SR_OK)
e46b8fb1 939 return SR_ERR;
530f201e 940 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_1,
fefc4b85 941 reverse32(devc->trigger_value[1])) != SR_OK)
e46b8fb1 942 return SR_ERR;
530f201e 943 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
944 trigger_config[1]) != SR_OK)
945 return SR_ERR;
6937bb75 946
530f201e 947 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_2,
fefc4b85 948 reverse32(devc->trigger_mask[2])) != SR_OK)
e46b8fb1 949 return SR_ERR;
530f201e 950 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_2,
fefc4b85 951 reverse32(devc->trigger_value[2])) != SR_OK)
e46b8fb1 952 return SR_ERR;
530f201e 953 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
954 trigger_config[2]) != SR_OK)
955 return SR_ERR;
a803c0db 956
530f201e 957 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_3,
fefc4b85 958 reverse32(devc->trigger_mask[3])) != SR_OK)
e46b8fb1 959 return SR_ERR;
530f201e 960 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_3,
fefc4b85 961 reverse32(devc->trigger_value[3])) != SR_OK)
e46b8fb1 962 return SR_ERR;
530f201e 963 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
964 trigger_config[3]) != SR_OK)
965 return SR_ERR;
6937bb75 966 } else {
530f201e 967 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_MASK_0,
fefc4b85 968 devc->trigger_mask[0]) != SR_OK)
e46b8fb1 969 return SR_ERR;
530f201e 970 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_VALUE_0,
fefc4b85 971 devc->trigger_value[0]) != SR_OK)
e46b8fb1 972 return SR_ERR;
530f201e 973 if (send_longcommand(devc->serial, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
974 0x00000008) != SR_OK)
975 return SR_ERR;
a803c0db 976 delaycount = readcount;
6937bb75 977 }
a1bb33af 978
b08024a8 979 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
fefc4b85
BV
980 "demux %s)", devc->cur_samplerate, devc->cur_samplerate_divider,
981 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
530f201e 982 if (send_longcommand(devc->serial, CMD_SET_DIVIDER,
fefc4b85 983 reverse32(devc->cur_samplerate_divider)) != SR_OK)
4fe9a6da 984 return SR_ERR;
a1bb33af 985
43fc7885 986 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
987 data = ((readcount - 1) & 0xffff) << 16;
988 data |= (delaycount - 1) & 0xffff;
530f201e 989 if (send_longcommand(devc->serial, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 990 return SR_ERR;
a1bb33af 991
43fc7885 992 /* The flag register wants them here, and 1 means "disable channel". */
fefc4b85
BV
993 devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
994 devc->flag_reg |= FLAG_FILTER;
995 devc->rle_count = 0;
996 data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
530f201e 997 if (send_longcommand(devc->serial, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 998 return SR_ERR;
a1bb33af 999
43fc7885 1000 /* Start acquisition on the device. */
530f201e 1001 if (send_shortcommand(devc->serial, CMD_RUN) != SR_OK)
e46b8fb1 1002 return SR_ERR;
a1bb33af 1003
fefc4b85 1004 sr_source_add(devc->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 1005 cb_data);
a1bb33af 1006
b53738ba
UH
1007 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1008 sr_err("ols: %s: packet malloc failed", __func__);
1009 return SR_ERR_MALLOC;
1010 }
1011
1012 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1013 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1014 g_free(packet);
b53738ba
UH
1015 return SR_ERR_MALLOC;
1016 }
1017
43fc7885 1018 /* Send header packet to the session bus. */
5a2326a7 1019 packet->type = SR_DF_HEADER;
43fc7885 1020 packet->payload = (unsigned char *)header;
a1bb33af
UH
1021 header->feed_version = 1;
1022 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1023 sr_session_send(cb_data, packet);
1024
1025 /* Send metadata about the SR_DF_LOGIC packets to come. */
1026 packet->type = SR_DF_META_LOGIC;
1027 packet->payload = &meta;
fefc4b85 1028 meta.samplerate = devc->cur_samplerate;
f366e86c 1029 meta.num_probes = NUM_PROBES;
3cd3a20b 1030 sr_session_send(cb_data, packet);
c0a4b971 1031
a1bb33af
UH
1032 g_free(header);
1033 g_free(packet);
1034
e46b8fb1 1035 return SR_OK;
a1bb33af
UH
1036}
1037
3cd3a20b 1038/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
69b07d14 1039static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
a1bb33af 1040{
17e1afcb 1041 /* Avoid compiler warnings. */
26bf9d56 1042 (void)cb_data;
afc8e4de 1043
26bf9d56 1044 abort_acquisition(sdi);
3010f21c
UH
1045
1046 return SR_OK;
a1bb33af
UH
1047}
1048
c09f0b57 1049SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1050 .name = "ols",
1051 .longname = "Openbench Logic Sniffer",
1052 .api_version = 1,
1053 .init = hw_init,
1054 .cleanup = hw_cleanup,
61136ea6 1055 .scan = hw_scan,
811deee4
BV
1056 .dev_list = hw_dev_list,
1057 .dev_clear = hw_cleanup,
e7eb703f
UH
1058 .dev_open = hw_dev_open,
1059 .dev_close = hw_dev_close,
dddfb3db 1060 .info_get = hw_info_get,
a9a245b4 1061 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1062 .dev_acquisition_start = hw_dev_acquisition_start,
1063 .dev_acquisition_stop = hw_dev_acquisition_stop,
fefc4b85 1064 .priv = NULL,
a1bb33af 1065};