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f44d2db2 | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
f44d2db2 | 3 | ## |
15ac6604 | 4 | ## Copyright (C) 2011-2013 Uwe Hermann <uwe@hermann-uwe.de> |
f44d2db2 UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
f44d2db2 | 21 | # UART protocol decoder |
f44d2db2 | 22 | |
677d597b | 23 | import sigrokdecode as srd |
f44d2db2 | 24 | |
4cace3b8 UH |
25 | ''' |
26 | Protocol output format: | |
27 | ||
28 | UART packet: | |
29 | [<packet-type>, <rxtx>, <packet-data>] | |
30 | ||
31 | This is the list of <packet-type>s and their respective <packet-data>: | |
32 | - 'STARTBIT': The data is the (integer) value of the start bit (0/1). | |
33 | - 'DATA': The data is the (integer) value of the UART data. Valid values | |
34 | range from 0 to 512 (as the data can be up to 9 bits in size). | |
35 | - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). | |
36 | - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). | |
37 | - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). | |
38 | - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). | |
39 | - 'PARITY ERROR': The data is a tuple with two entries. The first one is | |
40 | the expected parity value, the second is the actual parity value. | |
41 | - TODO: Frame error? | |
42 | ||
43 | The <rxtx> field is 0 for RX packets, 1 for TX packets. | |
44 | ''' | |
45 | ||
97cca21f UH |
46 | # Used for differentiating between the two data directions. |
47 | RX = 0 | |
48 | TX = 1 | |
49 | ||
f44d2db2 UH |
50 | # Given a parity type to check (odd, even, zero, one), the value of the |
51 | # parity bit, the value of the data, and the length of the data (5-9 bits, | |
52 | # usually 8 bits) return True if the parity is correct, False otherwise. | |
a7fc4c34 | 53 | # 'none' is _not_ allowed as value for 'parity_type'. |
f44d2db2 UH |
54 | def parity_ok(parity_type, parity_bit, data, num_data_bits): |
55 | ||
56 | # Handle easy cases first (parity bit is always 1 or 0). | |
a7fc4c34 | 57 | if parity_type == 'zero': |
f44d2db2 | 58 | return parity_bit == 0 |
a7fc4c34 | 59 | elif parity_type == 'one': |
f44d2db2 UH |
60 | return parity_bit == 1 |
61 | ||
62 | # Count number of 1 (high) bits in the data (and the parity bit itself!). | |
ac941bf9 | 63 | ones = bin(data).count('1') + parity_bit |
f44d2db2 UH |
64 | |
65 | # Check for odd/even parity. | |
a7fc4c34 | 66 | if parity_type == 'odd': |
ac941bf9 | 67 | return (ones % 2) == 1 |
a7fc4c34 | 68 | elif parity_type == 'even': |
ac941bf9 | 69 | return (ones % 2) == 0 |
f44d2db2 UH |
70 | else: |
71 | raise Exception('Invalid parity type: %d' % parity_type) | |
72 | ||
677d597b | 73 | class Decoder(srd.Decoder): |
a2c2afd9 | 74 | api_version = 1 |
f44d2db2 UH |
75 | id = 'uart' |
76 | name = 'UART' | |
3d3da57d | 77 | longname = 'Universal Asynchronous Receiver/Transmitter' |
a465436e | 78 | desc = 'Asynchronous, serial bus.' |
f44d2db2 UH |
79 | license = 'gplv2+' |
80 | inputs = ['logic'] | |
81 | outputs = ['uart'] | |
29ed0f4c | 82 | probes = [ |
f44d2db2 UH |
83 | # Allow specifying only one of the signals, e.g. if only one data |
84 | # direction exists (or is relevant). | |
29ed0f4c UH |
85 | {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, |
86 | {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, | |
87 | ] | |
b77614bc | 88 | optional_probes = [] |
f44d2db2 | 89 | options = { |
97cca21f | 90 | 'baudrate': ['Baud rate', 115200], |
f44d2db2 | 91 | 'num_data_bits': ['Data bits', 8], # Valid: 5-9. |
a7fc4c34 UH |
92 | 'parity_type': ['Parity type', 'none'], |
93 | 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported? | |
94 | 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5. | |
95 | 'bit_order': ['Bit order', 'lsb-first'], | |
3006c663 | 96 | 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin |
f44d2db2 | 97 | # TODO: Options to invert the signal(s). |
f44d2db2 | 98 | } |
e97b6ef5 | 99 | annotations = [ |
6d6b32d6 UH |
100 | ['RX data', 'UART RX data'], |
101 | ['TX data', 'UART TX data'], | |
3a1803b0 UH |
102 | ['Start bits', 'UART start bits'], |
103 | ['Parity bits', 'UART parity bits'], | |
104 | ['Stop bits', 'UART stop bits'], | |
105 | ['Warnings', 'Warnings'], | |
1bb57ab8 | 106 | ] |
f44d2db2 | 107 | |
97cca21f | 108 | def putx(self, rxtx, data): |
15ac6604 UH |
109 | s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) |
110 | self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) | |
111 | ||
112 | def putg(self, data): | |
113 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
114 | self.put(s - halfbit, s + halfbit, self.out_ann, data) | |
115 | ||
116 | def putp(self, data): | |
117 | s, halfbit = self.samplenum, int(self.bit_width / 2) | |
118 | self.put(s - halfbit, s + halfbit, self.out_proto, data) | |
97cca21f | 119 | |
f44d2db2 | 120 | def __init__(self, **kwargs): |
f44d2db2 | 121 | self.samplenum = 0 |
97cca21f UH |
122 | self.frame_start = [-1, -1] |
123 | self.startbit = [-1, -1] | |
124 | self.cur_data_bit = [0, 0] | |
125 | self.databyte = [0, 0] | |
1ccef461 | 126 | self.paritybit = [-1, -1] |
97cca21f UH |
127 | self.stopbit1 = [-1, -1] |
128 | self.startsample = [-1, -1] | |
2b716038 | 129 | self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] |
83be7b83 UH |
130 | self.oldbit = [1, 1] |
131 | self.oldpins = [1, 1] | |
f44d2db2 UH |
132 | |
133 | def start(self, metadata): | |
f44d2db2 | 134 | self.samplerate = metadata['samplerate'] |
56202222 UH |
135 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart') |
136 | self.out_ann = self.add(srd.OUTPUT_ANN, 'uart') | |
f44d2db2 | 137 | |
f44d2db2 | 138 | # The width of one UART bit in number of samples. |
4a04ece4 UH |
139 | self.bit_width = \ |
140 | float(self.samplerate) / float(self.options['baudrate']) | |
f44d2db2 UH |
141 | |
142 | def report(self): | |
143 | pass | |
144 | ||
145 | # Return true if we reached the middle of the desired bit, false otherwise. | |
97cca21f | 146 | def reached_bit(self, rxtx, bitnum): |
f44d2db2 UH |
147 | # bitpos is the samplenumber which is in the middle of the |
148 | # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit | |
149 | # (if used) or the first stop bit, and so on). | |
97cca21f | 150 | bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) |
f44d2db2 UH |
151 | bitpos += bitnum * self.bit_width |
152 | if self.samplenum >= bitpos: | |
153 | return True | |
154 | return False | |
155 | ||
97cca21f UH |
156 | def reached_bit_last(self, rxtx, bitnum): |
157 | bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) | |
f44d2db2 UH |
158 | if self.samplenum >= bitpos: |
159 | return True | |
160 | return False | |
161 | ||
97cca21f | 162 | def wait_for_start_bit(self, rxtx, old_signal, signal): |
f44d2db2 UH |
163 | # The start bit is always 0 (low). As the idle UART (and the stop bit) |
164 | # level is 1 (high), the beginning of a start bit is a falling edge. | |
165 | if not (old_signal == 1 and signal == 0): | |
166 | return | |
167 | ||
168 | # Save the sample number where the start bit begins. | |
97cca21f | 169 | self.frame_start[rxtx] = self.samplenum |
f44d2db2 | 170 | |
2b716038 | 171 | self.state[rxtx] = 'GET START BIT' |
f44d2db2 | 172 | |
97cca21f | 173 | def get_start_bit(self, rxtx, signal): |
f44d2db2 | 174 | # Skip samples until we're in the middle of the start bit. |
97cca21f | 175 | if not self.reached_bit(rxtx, 0): |
1bb57ab8 | 176 | return |
f44d2db2 | 177 | |
97cca21f | 178 | self.startbit[rxtx] = signal |
f44d2db2 | 179 | |
5cc4b6a0 | 180 | # The startbit must be 0. If not, we report an error. |
97cca21f | 181 | if self.startbit[rxtx] != 0: |
15ac6604 | 182 | self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) |
5cc4b6a0 | 183 | # TODO: Abort? Ignore rest of the frame? |
f44d2db2 | 184 | |
97cca21f UH |
185 | self.cur_data_bit[rxtx] = 0 |
186 | self.databyte[rxtx] = 0 | |
187 | self.startsample[rxtx] = -1 | |
f44d2db2 | 188 | |
2b716038 | 189 | self.state[rxtx] = 'GET DATA BITS' |
f44d2db2 | 190 | |
15ac6604 | 191 | self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) |
6d6b32d6 | 192 | self.putg([2, ['Start bit', 'Start', 'S']]) |
f44d2db2 | 193 | |
97cca21f | 194 | def get_data_bits(self, rxtx, signal): |
f44d2db2 | 195 | # Skip samples until we're in the middle of the desired data bit. |
97cca21f | 196 | if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): |
1bb57ab8 | 197 | return |
f44d2db2 | 198 | |
15ac6604 | 199 | # Save the sample number of the middle of the first data bit. |
97cca21f UH |
200 | if self.startsample[rxtx] == -1: |
201 | self.startsample[rxtx] = self.samplenum | |
f44d2db2 UH |
202 | |
203 | # Get the next data bit in LSB-first or MSB-first fashion. | |
a7fc4c34 | 204 | if self.options['bit_order'] == 'lsb-first': |
97cca21f | 205 | self.databyte[rxtx] >>= 1 |
fd4aa8aa UH |
206 | self.databyte[rxtx] |= \ |
207 | (signal << (self.options['num_data_bits'] - 1)) | |
a7fc4c34 | 208 | elif self.options['bit_order'] == 'msb-first': |
97cca21f UH |
209 | self.databyte[rxtx] <<= 1 |
210 | self.databyte[rxtx] |= (signal << 0) | |
f44d2db2 | 211 | else: |
a7fc4c34 | 212 | raise Exception('Invalid bit order value: %s', |
4a04ece4 | 213 | self.options['bit_order']) |
f44d2db2 UH |
214 | |
215 | # Return here, unless we already received all data bits. | |
4a04ece4 | 216 | if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: |
97cca21f | 217 | self.cur_data_bit[rxtx] += 1 |
1bb57ab8 | 218 | return |
f44d2db2 | 219 | |
2b716038 | 220 | self.state[rxtx] = 'GET PARITY BIT' |
f44d2db2 | 221 | |
15ac6604 | 222 | self.putp(['DATA', rxtx, self.databyte[rxtx]]) |
f44d2db2 | 223 | |
3006c663 UH |
224 | b, f = self.databyte[rxtx], self.options['format'] |
225 | if f == 'ascii': | |
6d6b32d6 | 226 | self.putx(rxtx, [rxtx, [chr(b)]]) |
3006c663 | 227 | elif f == 'dec': |
6d6b32d6 | 228 | self.putx(rxtx, [rxtx, [str(b)]]) |
3006c663 | 229 | elif f == 'hex': |
6d6b32d6 | 230 | self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]]) |
3006c663 | 231 | elif f == 'oct': |
6d6b32d6 | 232 | self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) |
3006c663 | 233 | elif f == 'bin': |
6d6b32d6 | 234 | self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) |
3006c663 UH |
235 | else: |
236 | raise Exception('Invalid data format option: %s' % f) | |
f44d2db2 | 237 | |
97cca21f | 238 | def get_parity_bit(self, rxtx, signal): |
f44d2db2 | 239 | # If no parity is used/configured, skip to the next state immediately. |
a7fc4c34 | 240 | if self.options['parity_type'] == 'none': |
2b716038 | 241 | self.state[rxtx] = 'GET STOP BITS' |
1bb57ab8 | 242 | return |
f44d2db2 UH |
243 | |
244 | # Skip samples until we're in the middle of the parity bit. | |
4a04ece4 | 245 | if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): |
1bb57ab8 | 246 | return |
f44d2db2 | 247 | |
97cca21f | 248 | self.paritybit[rxtx] = signal |
f44d2db2 | 249 | |
2b716038 | 250 | self.state[rxtx] = 'GET STOP BITS' |
f44d2db2 | 251 | |
ac941bf9 | 252 | if parity_ok(self.options['parity_type'], self.paritybit[rxtx], |
4a04ece4 | 253 | self.databyte[rxtx], self.options['num_data_bits']): |
15ac6604 | 254 | self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) |
6d6b32d6 | 255 | self.putg([3, ['Parity bit', 'Parity', 'P']]) |
f44d2db2 | 256 | else: |
61132abd | 257 | # TODO: Return expected/actual parity values. |
15ac6604 | 258 | self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... |
6d6b32d6 | 259 | self.putg([5, ['Parity error', 'Parity err', 'PE']]) |
f44d2db2 UH |
260 | |
261 | # TODO: Currently only supports 1 stop bit. | |
97cca21f | 262 | def get_stop_bits(self, rxtx, signal): |
f44d2db2 | 263 | # Skip samples until we're in the middle of the stop bit(s). |
a7fc4c34 | 264 | skip_parity = 0 if self.options['parity_type'] == 'none' else 1 |
4a04ece4 UH |
265 | b = self.options['num_data_bits'] + 1 + skip_parity |
266 | if not self.reached_bit(rxtx, b): | |
1bb57ab8 | 267 | return |
f44d2db2 | 268 | |
97cca21f | 269 | self.stopbit1[rxtx] = signal |
f44d2db2 | 270 | |
5cc4b6a0 | 271 | # Stop bits must be 1. If not, we report an error. |
97cca21f | 272 | if self.stopbit1[rxtx] != 1: |
15ac6604 | 273 | self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) |
6d6b32d6 | 274 | self.putg([5, ['Frame error', 'Frame err', 'FE']]) |
5cc4b6a0 | 275 | # TODO: Abort? Ignore the frame? Other? |
f44d2db2 | 276 | |
2b716038 | 277 | self.state[rxtx] = 'WAIT FOR START BIT' |
f44d2db2 | 278 | |
15ac6604 | 279 | self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) |
6d6b32d6 | 280 | self.putg([4, ['Stop bit', 'Stop', 'T']]) |
f44d2db2 | 281 | |
decde15e UH |
282 | def decode(self, ss, es, data): |
283 | # TODO: Either RX or TX could be omitted (optional probe). | |
2fcd7c22 UH |
284 | for (self.samplenum, pins) in data: |
285 | ||
b0827236 UH |
286 | # Note: Ignoring identical samples here for performance reasons |
287 | # is not possible for this PD, at least not in the current state. | |
288 | # if self.oldpins == pins: | |
289 | # continue | |
2fcd7c22 | 290 | self.oldpins, (rx, tx) = pins, pins |
f44d2db2 | 291 | |
f44d2db2 | 292 | # State machine. |
97cca21f UH |
293 | for rxtx in (RX, TX): |
294 | signal = rx if (rxtx == RX) else tx | |
295 | ||
2b716038 | 296 | if self.state[rxtx] == 'WAIT FOR START BIT': |
97cca21f | 297 | self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) |
2b716038 | 298 | elif self.state[rxtx] == 'GET START BIT': |
97cca21f | 299 | self.get_start_bit(rxtx, signal) |
2b716038 | 300 | elif self.state[rxtx] == 'GET DATA BITS': |
97cca21f | 301 | self.get_data_bits(rxtx, signal) |
2b716038 | 302 | elif self.state[rxtx] == 'GET PARITY BIT': |
97cca21f | 303 | self.get_parity_bit(rxtx, signal) |
2b716038 | 304 | elif self.state[rxtx] == 'GET STOP BITS': |
97cca21f UH |
305 | self.get_stop_bits(rxtx, signal) |
306 | else: | |
0eeeb544 | 307 | raise Exception('Invalid state: %s' % self.state[rxtx]) |
97cca21f UH |
308 | |
309 | # Save current RX/TX values for the next round. | |
310 | self.oldbit[rxtx] = signal | |
f44d2db2 | 311 |