[sigrok-firmware-fx2lafw.git] / hantek_6022bl.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 0

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 1, 2 & 3
 * For channel 1 we want to set bits 4, 5 & 6
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x02;
		break;
	case 2:
		bits = 0x01;
		break;
	case 5:
		bits = 0x00;
		break;
	case 10:
		bits = 0x03;
		break;
	default:
		return FALSE;
	}

	bits = bits << (channel ? 1 : 4);
	mask = (channel) ? 0x70 : 0x0e;
	IOA = (IOA & ~mask) | (bits & mask);

	return TRUE;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe4) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
1d203181 STA	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
e583c3fc UH	29	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	30	#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2
	31
65b34f7e UH	32	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	33	#define LED_GREEN() PC0 = 1; PC1 = 0;
	34	#define LED_RED() PC0 = 0; PC1 = 1;
	35
e1c5ba21 UH	36	/* CTLx pin index (IFCLK, ADC clock input). */
	37	#define CTL_BIT 0
	38
	39	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	40	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	41
1d203181 STA	42	/* Change to support as many interfaces as you need. */
	43	static BYTE altiface = 0;
	44
	45	static volatile WORD ledcounter = 0;
	46
	47	static volatile __bit dosud = FALSE;
	48	static volatile __bit dosuspend = FALSE;
	49
	50	extern __code BYTE highspd_dscr;
	51	extern __code BYTE fullspd_dscr;
	52
	53	void resume_isr(void) __interrupt RESUME_ISR
	54	{
	55	CLEAR_RESUME();
	56	}
	57
	58	void sudav_isr(void) __interrupt SUDAV_ISR
	59	{
	60	dosud = TRUE;
	61	CLEAR_SUDAV();
	62	}
	63
	64	void usbreset_isr(void) __interrupt USBRESET_ISR
	65	{
	66	handle_hispeed(FALSE);
	67	CLEAR_USBRESET();
	68	}
	69
	70	void hispeed_isr(void) __interrupt HISPEED_ISR
	71	{
	72	handle_hispeed(TRUE);
	73	CLEAR_HISPEED();
	74	}
	75
	76	void suspend_isr(void) __interrupt SUSPEND_ISR
	77	{
	78	dosuspend = TRUE;
	79	CLEAR_SUSPEND();
	80	}
	81
	82	void timer2_isr(void) __interrupt TF2_ISR
	83	{
e583c3fc	84	TOGGLE_CALIBRATION_PIN();
cbd1bc65	85
65b34f7e UH	86	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	87	LED_CLEAR();
3968bbfb	88
1d203181 STA	89	TF2 = 0;
	90	}
	91
	92	/*
	93	* This sets three bits for each channel, one channel at a time.
ae56b4f6 JL	94	* For channel 0 we want to set bits 1, 2 & 3
ae56b4f6 JL	95	* For channel 1 we want to set bits 4, 5 & 6
1d203181 STA	96	*
	97	* We convert the input values that are strange due to original
	98	* firmware code into the value of the three bits as follows:
	99	*
	100	* val -> bits
	101	* 1 -> 010b
	102	* 2 -> 001b
	103	* 5 -> 000b
	104	* 10 -> 011b
	105	*
	106	* The third bit is always zero since there are only four outputs connected
	107	* in the serial selector chip.
	108	*
	109	* The multiplication of the converted value by 0x24 sets the relevant bits in
	110	* both channels and then we mask it out to only affect the channel currently
	111	* requested.
	112	*/
	113	static BOOL set_voltage(BYTE channel, BYTE val)
	114	{
	115	BYTE bits, mask;
	116
	117	switch (val) {
	118	case 1:
ae56b4f6	119	bits = 0x02;
1d203181 STA	120	break;
1d203181 STA	121	case 2:
ae56b4f6	122	bits = 0x01;
1d203181 STA	123	break;
1d203181 STA	124	case 5:
ae56b4f6	125	bits = 0x00;
1d203181 STA	126	break;
1d203181 STA	127	case 10:
ae56b4f6	128	bits = 0x03;
1d203181 STA	129	break;
	130	default:
	131	return FALSE;
	132	}
	133
ae56b4f6 JL	134	bits = bits << (channel ? 1 : 4);
	135	mask = (channel) ? 0x70 : 0x0e;
	136	IOA = (IOA & ~mask) \| (bits & mask);
1d203181 STA	137
	138	return TRUE;
	139	}
	140
	141	static BOOL set_numchannels(BYTE numchannels)
	142	{
	143	if (numchannels == 1 \|\| numchannels == 2) {
	144	BYTE fifocfg = 7 + numchannels;
	145	EP2FIFOCFG = fifocfg;
	146	EP6FIFOCFG = fifocfg;
	147	return TRUE;
	148	}
	149
	150	return FALSE;
	151	}
	152
	153	static void clear_fifo(void)
	154	{
	155	GPIFABORT = 0xff;
	156	SYNCDELAY3;
	157	FIFORESET = 0x80;
	158	SYNCDELAY3;
	159	FIFORESET = 0x82;
	160	SYNCDELAY3;
	161	FIFORESET = 0x86;
	162	SYNCDELAY3;
	163	FIFORESET = 0;
	164	}
	165
	166	static void stop_sampling(void)
	167	{
	168	GPIFABORT = 0xff;
	169	SYNCDELAY3;
	170	INPKTEND = (altiface == 0) ? 6 : 2;
	171	}
	172
	173	static void start_sampling(void)
	174	{
	175	int i;
	176
be6d306d	177	SET_ANALOG_MODE();
59562384	178
1d203181 STA	179	clear_fifo();
	180
	181	for (i = 0; i < 1000; i++);
	182
	183	while (!(GPIFTRIG & 0x80))
	184	;
	185
	186	SYNCDELAY3;
	187	GPIFTCB1 = 0x28;
	188	SYNCDELAY3;
	189	GPIFTCB0 = 0;
	190	GPIFTRIG = (altiface == 0) ? 6 : 4;
	191
65b34f7e UH	192	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	193	LED_GREEN();
1d203181	194	ledcounter = 0;
1d203181 STA	195	}
	196
	197	static void select_interface(BYTE alt)
	198	{
	199	const BYTE *pPacketSize = \
	200	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	201	+ (9 + (16 * alt) + 9 + 4);
	202
	203	altiface = alt;
	204
	205	if (alt == 0) {
	206	/* Bulk on EP6. */
	207	EP2CFG = 0x00;
	208	EP6CFG = 0xe0;
	209	EP6GPIFFLGSEL = 1;
	210	EP6AUTOINLENL = pPacketSize[0];
	211	EP6AUTOINLENH = pPacketSize[1];
	212	} else {
	213	/* Iso on EP2. */
	214	EP2CFG = 0xd8;
	215	EP6CFG = 0x00;
	216	EP2GPIFFLGSEL = 1;
	217	EP2AUTOINLENL = pPacketSize[0];
	218	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	219	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	220	}
	221	}
	222
	223	static const struct samplerate_info {
	224	BYTE rate;
	225	BYTE wait0;
	226	BYTE wait1;
	227	BYTE opc0;
	228	BYTE opc1;
	229	BYTE out0;
	230	BYTE ifcfg;
	231	} samplerates[] = {
	232	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	233	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	234	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	235	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	236	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	237	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	238	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	239	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	240	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	241	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	242	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	243	{ 10, 240, 239, 2, 0, OUT0, 0xca },
1d203181 STA	244	};
	245
	246	static BOOL set_samplerate(BYTE rate)
	247	{
	248	BYTE i = 0;
	249
	250	while (samplerates[i].rate != rate) {
	251	i++;
	252	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	253	return FALSE;
	254	}
	255
	256	IFCONFIG = samplerates[i].ifcfg;
	257
	258	AUTOPTRSETUP = 7;
	259	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	260	AUTOPTRL2 = 0x00;
	261
	262	/*
	263	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	264	* wait 24, CTLx=0, FIFO
	265	* wait 23, CTLx=1
	266	* jump 0, CTLx=1
1d203181 STA	267	*
1d203181 STA	268	* The program for 24 MHz is:
3968bbfb UH	269	* wait 1, CTLx=0, FIFO
3968bbfb UH	270	* jump 0, CTLx=1
1d203181 STA	271	*
1d203181 STA	272	* The program for 30/48 MHz is:
3968bbfb UH	273	* jump 0, CTLx=Z, FIFO, LOOP
	274	*
	275	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
1d203181 STA	276	*/
	277
	278	/* LENGTH / BRANCH 0-7 */
	279	EXTAUTODAT2 = samplerates[i].wait0;
	280	EXTAUTODAT2 = samplerates[i].wait1;
	281	EXTAUTODAT2 = 1;
	282	EXTAUTODAT2 = 0;
	283	EXTAUTODAT2 = 0;
	284	EXTAUTODAT2 = 0;
	285	EXTAUTODAT2 = 0;
	286	EXTAUTODAT2 = 0;
	287
	288	/* OPCODE 0-7 */
	289	EXTAUTODAT2 = samplerates[i].opc0;
	290	EXTAUTODAT2 = samplerates[i].opc1;
	291	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	292	EXTAUTODAT2 = 0;
	293	EXTAUTODAT2 = 0;
	294	EXTAUTODAT2 = 0;
	295	EXTAUTODAT2 = 0;
	296	EXTAUTODAT2 = 0;
	297
	298	/* OUTPUT 0-7 */
	299	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	300	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	301	EXTAUTODAT2 = OE_CTL;
1d203181 STA	302	EXTAUTODAT2 = 0;
	303	EXTAUTODAT2 = 0;
	304	EXTAUTODAT2 = 0;
	305	EXTAUTODAT2 = 0;
	306	EXTAUTODAT2 = 0;
	307
	308	/* LOGIC FUNCTION 0-7 */
	309	EXTAUTODAT2 = 0;
	310	EXTAUTODAT2 = 0;
	311	EXTAUTODAT2 = 0;
	312	EXTAUTODAT2 = 0;
	313	EXTAUTODAT2 = 0;
	314	EXTAUTODAT2 = 0;
	315	EXTAUTODAT2 = 0;
	316	EXTAUTODAT2 = 0;
	317
	318	for (i = 0; i < 96; i++)
	319	EXTAUTODAT2 = 0;
	320
	321	return TRUE;
	322	}
	323
	324	/* Set alt_ifc to the current alt interface for ifc. /
	325	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	326	{
	327	(void)ifc;
	328
	329	*alt_ifc = altiface;
	330
	331	return TRUE;
	332	}
	333
	334	/*
	335	* Return TRUE if you set the interface requested.
	336	*
	337	* Note: This function should reconfigure and reset the endpoints
	338	* according to the interface descriptors you provided.
	339	*/
	340	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	341	{
	342	if (ifc == 0)
	343	select_interface(alt_ifc);
	344
	345	return TRUE;
	346	}
	347
	348	BYTE handle_get_configuration(void)
	349	{
	350	/* We only support configuration 0. */
	351	return 0;
	352	}
	353
	354	BOOL handle_set_configuration(BYTE cfg)
	355	{
	356	/* We only support configuration 0. */
	357	(void)cfg;
	358
	359	return TRUE;
	360	}
	361
	362	BOOL handle_vendorcommand(BYTE cmd)
	363	{
	364	stop_sampling();
	365
65b34f7e UH	366	/* Set red LED, clear after timeout. */
65b34f7e UH	367	LED_RED();
1d203181 STA	368	ledcounter = 1000;
	369
	370	/* Clear EP0BCH/L for each valid command. */
	371	if (cmd >= 0xe0 && cmd <= 0xe4) {
	372	EP0BCH = 0;
	373	EP0BCL = 0;
	374	while (EP0CS & bmEPBUSY);
	375	}
	376
	377	switch (cmd) {
	378	case 0xe0:
	379	case 0xe1:
	380	set_voltage(cmd - 0xe0, EP0BUF[0]);
	381	return TRUE;
	382	case 0xe2:
	383	set_samplerate(EP0BUF[0]);
	384	return TRUE;
	385	case 0xe3:
	386	if (EP0BUF[0] == 1)
	387	start_sampling();
	388	return TRUE;
	389	case 0xe4:
	390	set_numchannels(EP0BUF[0]);
	391	return TRUE;
	392	}
	393
	394	return FALSE; /* Not handled by handlers. */
	395	}
	396
	397	static void init(void)
	398	{
	399	EP4CFG = 0;
	400	EP8CFG = 0;
	401
be6d306d	402	SET_ANALOG_MODE();
eb52aca4	403
1d203181 STA	404	/* In idle mode tristate all outputs. */
	405	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	406	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	407	GPIFWFSELECT = 0x00;
	408	GPIFREADYSTAT = 0x00;
	409
	410	stop_sampling();
	411
	412	set_voltage(0, 1);
	413	set_voltage(1, 1);
	414	set_samplerate(1);
	415	set_numchannels(2);
	416	select_interface(0);
	417	}
	418
	419	static void main(void)
	420	{
	421	/* Save energy. */
	422	SETCPUFREQ(CLK_12M);
	423
	424	init();
	425
	426	/* Set up interrupts. */
	427	USE_USB_INTS();
	428
	429	ENABLE_SUDAV();
	430	ENABLE_USBRESET();
	431	ENABLE_HISPEED();
	432	ENABLE_SUSPEND();
	433	ENABLE_RESUME();
	434
	435	/* Global (8051) interrupt enable. */
	436	EA = 1;
	437
	438	/* Init timer2. */
	439	RCAP2L = -500 & 0xff;
	440	RCAP2H = (-500 & 0xff00) >> 8;
	441	T2CON = 0;
	442	ET2 = 1;
	443	TR2 = 1;
	444
beaa03fc	445	RENUMERATE_UNCOND();
1d203181	446
4d971e01	447	PORTECFG = 0;
1d203181 STA	448	PORTCCFG = 0;
1d203181 STA	449	PORTACFG = 0;
4d971e01	450	OEE = 0xff;
1d203181	451	OEC = 0xff;
f6eb6aec	452	OEA = 0xff;
1d203181 STA	453
	454	while (TRUE) {
	455	if (dosud) {
	456	dosud = FALSE;
	457	handle_setupdata();
	458	}
	459
	460	if (dosuspend) {
	461	dosuspend = FALSE;
	462	do {
	463	/* Make sure ext wakeups are cleared. */
3968bbfb	464	WAKEUPCS \|= bmWU \| bmWU2;
1d203181 STA	465	SUSPEND = 1;
	466	PCON \|= 1;
	467	__asm
	468	nop
	469	nop
	470	nop
	471	nop
	472	nop
	473	nop
	474	nop
	475	__endasm;
	476	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	477
	478	/* Resume (TRM 6.4). */
	479	if (REMOTE_WAKEUP()) {
	480	delay(5);
	481	USBCS \|= bmSIGRESUME;
	482	delay(15);
	483	USBCS &= ~bmSIGRESUME;
	484	}
	485	}
	486	}
	487	}