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d5f5ea73 1/*
a986cfff 2 * This file is part of the sigrok-firmware-fx2lafw project.
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3 *
4 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
23 *
24 * It is written in C, using fx2lib as helper library, and sdcc as compiler.
25 * The code is licensed under the terms of the GNU GPL, version 2 or later.
26 *
27 * Technical notes:
28 *
29 * - We use the FX2 in GPIF mode to sample the data (asynchronously).
30 * - We use the internal 48MHz clock for GPIF.
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31 * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7,
32 * or PB0-PB7 + PD0-PD7 for 16-channel sampling.
33 * - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host.
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34 *
35 * Documentation:
36 *
37 * - See http://sigrok.org/wiki/Fx2lafw
38 */
39
40#include <fx2regs.h>
41#include <fx2macros.h>
42#include <delay.h>
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43#include <setupdat.h>
44#include <eputils.h>
45#include <gpif.h>
64d47730 46#include <command.h>
8f4a701f 47#include <fx2lafw.h>
e41576ec 48#include <gpif-acquisition.h>
d5f5ea73 49
d5f5ea73 50/* ... */
8819f75c 51volatile __bit got_sud;
2846a114 52BYTE vendor_command;
d5f5ea73 53
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54static void setup_endpoints(void)
55{
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56 /* Setup EP2 (IN). */
57 EP2CFG = (1 << 7) | /* EP is valid/activated */
58 (1 << 6) | /* EP direction: IN */
59 (1 << 5) | (0 << 4) | /* EP Type: bulk */
5a95b634 60 (1 << 3) | /* EP buffer size: 1024 */
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61 (0 << 2) | /* Reserved. */
62 (0 << 1) | (0 << 0); /* EP buffering: quad buffering */
63 SYNCDELAY();
64
576c6627 65 /* Disable all other EPs (EP1, EP4, EP6, and EP8). */
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66 EP1INCFG &= ~bmVALID;
67 SYNCDELAY();
68 EP1OUTCFG &= ~bmVALID;
69 SYNCDELAY();
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70 EP4CFG &= ~bmVALID;
71 SYNCDELAY();
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72 EP6CFG &= ~bmVALID;
73 SYNCDELAY();
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74 EP8CFG &= ~bmVALID;
75 SYNCDELAY();
76
4ad20a4c 77 /* EP2: Reset the FIFOs. */
d5f5ea73 78 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73 79 RESETFIFO(0x02)
2d62ae47 80
dc7ac8bf 81 /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
2d62ae47 82 EP2FIFOCFG = bmAUTOIN;
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83 SYNCDELAY();
84
85 /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
86 EP2AUTOINLENH = 0x02;
87 SYNCDELAY();
88 EP2AUTOINLENL = 0x00;
89 SYNCDELAY();
90
4ad20a4c 91 /* EP2: Set the GPIF flag to 'full'. */
fb0b6d28 92 EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
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93 SYNCDELAY();
94}
95
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96static void send_fw_version(void)
97{
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98 /* Populate the buffer. */
99 struct version_info *const vi = (struct version_info *)EP0BUF;
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100 vi->major = FX2LAFW_VERSION_MAJOR;
101 vi->minor = FX2LAFW_VERSION_MINOR;
102
cd29817d 103 /* Send the message. */
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104 EP0BCH = 0;
105 EP0BCL = sizeof(struct version_info);
106}
107
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108static void send_revid_version(void)
109{
110 uint8_t *p;
111
112 /* Populate the buffer. */
113 p = (uint8_t *)EP0BUF;
114 *p = REVID;
115
116 /* Send the message. */
117 EP0BCH = 0;
118 EP0BCL = 1;
119}
120
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121BOOL handle_vendorcommand(BYTE cmd)
122{
c7283c28 123 /* Protocol implementation */
c7283c28 124 switch (cmd) {
3b6919fa 125 case CMD_START:
18544912 126 vendor_command = cmd;
2846a114 127 EP0BCL = 0;
18544912 128 return TRUE;
cd29817d 129 break;
2846a114 130 case CMD_GET_FW_VERSION:
18544912 131 send_fw_version();
3b6919fa 132 return TRUE;
cd29817d 133 break;
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134 case CMD_GET_REVID_VERSION:
135 send_revid_version();
136 return TRUE;
137 break;
c7283c28 138 }
4ad20a4c 139
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140 return FALSE;
141}
142
143BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
144{
145 /* We only support interface 0, alternate interface 0. */
146 if (ifc != 0)
147 return FALSE;
148
149 *alt_ifc = 0;
150 return TRUE;
151}
152
153BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
154{
155 /* We only support interface 0, alternate interface 0. */
156 if (ifc != 0 || alt_ifc != 0)
157 return FALSE;
c7e02d8c 158
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159 /* Perform procedure from TRM, section 2.3.7: */
160
161 /* (1) TODO. */
162
163 /* (2) Reset data toggles of the EPs in the interface. */
164 /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
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165 RESETTOGGLE(0x82);
166
167 /* (3) Restore EPs to their default conditions. */
168 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
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169 RESETFIFO(0x02);
170 /* TODO */
c430e296 171
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172 /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
173
174 return TRUE;
175}
176
177BYTE handle_get_configuration(void)
178{
179 /* We only support configuration 1. */
180 return 1;
181}
182
183BOOL handle_set_configuration(BYTE cfg)
184{
185 /* We only support configuration 1. */
186 return (cfg == 1) ? TRUE : FALSE;
187}
188
8819f75c 189void sudav_isr(void) __interrupt SUDAV_ISR
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190{
191 got_sud = TRUE;
192 CLEAR_SUDAV();
193}
194
8819f75c 195void sof_isr(void) __interrupt SOF_ISR __using 1
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196{
197 CLEAR_SOF();
198}
199
8819f75c 200void usbreset_isr(void) __interrupt USBRESET_ISR
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201{
202 handle_hispeed(FALSE);
203 CLEAR_USBRESET();
204}
205
8819f75c 206void hispeed_isr(void) __interrupt HISPEED_ISR
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207{
208 handle_hispeed(TRUE);
209 CLEAR_HISPEED();
210}
211
1cbff47d 212void fx2lafw_init(void)
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213{
214 /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
e7434142 215 REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;
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216
217 got_sud = FALSE;
2846a114 218 vendor_command = 0;
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219
220 /* Renumerate. */
221 RENUMERATE_UNCOND();
222
223 SETCPUFREQ(CLK_48M);
224
225 USE_USB_INTS();
226
227 /* TODO: Does the order of the following lines matter? */
228 ENABLE_SUDAV();
229 ENABLE_SOF();
230 ENABLE_HISPEED();
231 ENABLE_USBRESET();
232
233 /* Global (8051) interrupt enable. */
234 EA = 1;
235
236 /* Setup the endpoints. */
237 setup_endpoints();
238
239 /* Put the FX2 into GPIF master mode and setup the GPIF. */
240 gpif_init_la();
1cbff47d 241}
d5f5ea73 242
28d52f41 243void fx2lafw_poll(void)
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244{
245 if (got_sud) {
246 handle_setupdata();
247 got_sud = FALSE;
d5f5ea73 248 }
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249
250 if (vendor_command) {
251 switch (vendor_command) {
2846a114 252 case CMD_START:
cd29817d 253 if ((EP0CS & bmEPBUSY) != 0)
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254 break;
255
75630581 256 if (EP0BCL == sizeof(struct cmd_start_acquisition)) {
2846a114 257 gpif_acquisition_start(
cd29817d 258 (const struct cmd_start_acquisition *)EP0BUF);
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259 }
260
261 /* Acknowledge the vendor command. */
262 vendor_command = 0;
263 break;
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264 default:
265 /* Unimplemented command. */
266 vendor_command = 0;
267 break;
268 }
269 }
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270
271 gpif_poll();
d5f5ea73 272}
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273
274void main(void)
275{
276 fx2lafw_init();
277 while (1)
278 fx2lafw_poll();
279}