[sigrok-firmware-fx2lafw.git] / fx2lafw.c

/*
 * This file is part of the fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

/*
 * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
 *
 * It is written in C, using fx2lib as helper library, and sdcc as compiler.
 * The code is licensed under the terms of the GNU GPL, version 2 or later.
 *
 * Technical notes:
 *
 *  - We use the FX2 in GPIF mode to sample the data (asynchronously).
 *  - We use the internal 48MHz clock for GPIF.
 *  - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7.
 *    Support for 16 channels is not yet included, but might be added later.
 *  - Endpoint 2 is used for data transfers from FX2 to host.
 *  - The endpoint is quad-buffered.
 *
 * Documentation:
 *
 *  - See http://sigrok.org/wiki/Fx2lafw
 */

#include <fx2regs.h>
#include <fx2macros.h>
#include <delay.h>
#include <autovector.h>
#include <setupdat.h>
#include <eputils.h>
#include <gpif.h>

/* Protocol commands */
#define CMD_SET_SAMPLERATE	0xb0
#define CMD_START		0xb1
#define CMD_STOP		0xb2
#define CMD_GET_FW_VERSION	0xb3
/* ... */

#define SYNCDELAY() SYNCDELAY4

/* ... */
volatile bit got_sud;

/* GPIF terminology: DP = decision point, NDP = non-decision-point */

/*
 * GPIF waveforms.
 *
 * See section "10.3.4 State Instructions" in the TRM for details.
 */
static const BYTE wavedata[128] = {
	/* Waveform 0: */

	/*
	 * This is the basic algorithm implemented in our GPIF state machine:
	 *
	 * State 0: NDP: Sample the FIFO data bus.
	 * State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
	 *          end the current waveform. Otherwise, go to state 0 again,
	 *          i.e., sample data until EP2 is full.
	 * State 2: Unused.
	 * State 3: Unused.
	 * State 4: Unused.
	 * State 5: Unused.
	 * State 6: Unused.
	 */

	/* S0-S6: LENGTH/BRANCH */
	/*
	 * For NDPs (LENGTH): Number of IFCLK cycles to stay in this state.
	 * For DPs (BRANCH): [7] ReExec, [5:3]: BRANCHON1, [2:0]: BRANCHON0.
	 *
	 * 0x01: Stay one IFCLK cycle in this state.
	 * 0x38: No Re-execution, BRANCHON1 = state 7, BRANCHON0 = state 0.
	 */
	// 0x01, 0x38, 0x01, 0x01, 0x01, 0x01, 0x01,
	// FIXME: For now just loop over the "sample data" state forever.
	0x01, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,
	/* TRM says "reserved", but GPIF designer always puts a 0x07 here. */
	0x07,

	/* S0-S6: OPCODE */
	/*
	 * 0x02: NDP, sample the FIFO data bus.
	 * 0x01: DP, don't sample the FIFO data bus.
	 */
	0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Reserved */
	0x00,

	/* S0-S6: OUTPUT */
	/* Unused, we don't output anything, we only sample the pins. */
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Reserved */
	0x00,

	/* S0-S6: LOGIC FUNCTION (not used for NDPs) */
	/*
	 * 0x36: LFUNC = "A AND B", A = FIFO flag, B = FIFO flag.
	 * The FIFO flag (FF == full flag, in our case) is configured via
	 * EP2GPIFFLGSEL.
	 *
	 * So: If the EP2 FIFO is full and the EP2 FIFO is full, go to
	 * the state specified by BRANCHON1 (state 7), otherwise BRANCHON0
	 * (state 0). See the LENGTH/BRANCH value above for details.
	 */
	0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* TRM says "reserved", but GPIF designer always puts a 0x3f here. */
	0x3f,

	/* TODO: Must unused waveforms be "valid"? */

	/* Waveform 1 (unused): */
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

	/* Waveform 2 (unused): */
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

	/* Waveform 3 (unused): */
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};

static void gpif_setup_registers(void)
{
	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	GPIFREADYCFG = 0;

	/*
	 * Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	 * TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	 */
	GPIFCTLCFG = 0;

	/* When GPIF is idle, tri-state the data bus. */
	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	GPIFIDLECS = (1 << 0);

	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	GPIFIDLECTL = 0;

	/*
	 * Map index 0 in wavedata[] to FIFORD. The rest is assigned too,
	 * but not used by us.
	 *
	 * GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	 *               [3:2] = FIFOWR index, [1:0] = FIFORD index
	 */
	GPIFWFSELECT = (0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0);

	/* Contains RDY* pin values. Read-only according to TRM. */
	GPIFREADYSTAT = 0;
}

static void gpif_write_waveforms(void)
{
	int i;

	/*
	 * Write the four waveforms into the respective WAVEDATA register
	 * locations (0xe400 - 0xe47f) using the FX2's autopointer feature.
	 */
	AUTOPTRSETUP = 0x07;             /* Increment autopointers 1 & 2. */
	AUTOPTRH1 = MSB((WORD)wavedata); /* Source is the 'wavedata' array. */
	AUTOPTRL1 = LSB((WORD)wavedata);
	AUTOPTRH2 = 0xe4;                /* Dest is WAVEDATA (0xe400). */
	AUTOPTRL2 = 0x00;
	for (i = 0; i < 128; i++)
		EXTAUTODAT2 = EXTAUTODAT1;
}

static void gpif_init_addr_pins(void)
{
	/*
	 * Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
	 * PORTC[7:0] and PORTE[7]), and output an initial address (zero).
	 * TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
	 */
	PORTCCFG = 0xff;    /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
	OEC = 0xff;         /* Configure PORTC[7:0] as outputs. */
	PORTECFG |= 0x80;   /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
	OEE |= 0x80;        /* Configure PORTE[7] as output. */
	SYNCDELAY();
	GPIFADRL = 0x00;    /* Clear GPIFADR[7:0]. */
	SYNCDELAY();
	GPIFADRH = 0x00;    /* Clear GPIFADR[8]. */
}

static void gpif_init_flowstates(void)
{
	/* Clear all flowstate registers, we don't use this functionality. */
	FLOWSTATE = 0;
	FLOWLOGIC = 0;
	FLOWEQ0CTL = 0;
	FLOWEQ1CTL = 0;
	FLOWHOLDOFF = 0;
	FLOWSTB = 0;
	FLOWSTBEDGE = 0;
	FLOWSTBHPERIOD = 0;
}

static void gpif_init_la(void)
{
	/*
	 * Setup the FX2 in GPIF master mode, using the internal clock
	 * (non-inverted) at 48MHz, and using async sampling.
	 */
	IFCONFIG = 0xee;

	/* Abort currently executing GPIF waveform (if any). */
	GPIFABORT = 0xff;

	/* Setup the GPIF registers. */
	gpif_setup_registers();

	/* Write the four GPIF waveforms into the WAVEDATA register. */
	gpif_write_waveforms();

	/* Initialize GPIF address pins, output initial values. */
	gpif_init_addr_pins();

	/* Initialize flowstate registers (not used by us). */
	gpif_init_flowstates();
}

static void setup_endpoints(void)
{
	/* Setup EP2 (IN). */
	EP2CFG = (1 << 7) |		  /* EP is valid/activated */
		 (1 << 6) |		  /* EP direction: IN */
		 (1 << 5) | (0 << 4) |	  /* EP Type: bulk */
		 (0 << 3) |		  /* EP buffer size: 512 */
		 (0 << 2) |		  /* Reserved. */
		 (0 << 1) | (0 << 0);	  /* EP buffering: quad buffering */
	SYNCDELAY();

	/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
	EP1INCFG &= ~bmVALID;
	SYNCDELAY();
	EP1OUTCFG &= ~bmVALID;
	SYNCDELAY();
	EP4CFG &= ~bmVALID;
	SYNCDELAY();
	EP6CFG &= ~bmVALID;
	SYNCDELAY();
	EP8CFG &= ~bmVALID;
	SYNCDELAY();

	/* EP2: Reset the FIFOs. */
	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
	RESETFIFO(0x02)

	/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
	EP2FIFOCFG = bmAUTOIN | ~bmWORDWIDE;
	SYNCDELAY();

	/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
	EP2AUTOINLENH = 0x02;
	SYNCDELAY();
	EP2AUTOINLENL = 0x00;
	SYNCDELAY();

	/* EP2: Set the GPIF flag to 'full'. */
	EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
	SYNCDELAY();
}

BOOL handle_vendorcommand(BYTE cmd)
{
	/* Protocol implementation */

	switch (cmd) {
	case CMD_SET_SAMPLERATE:
		/* TODO */
		break;
	case CMD_START:
		/* TODO */
		break;
	case CMD_STOP:
		GPIFABORT = 0xff;
		/* TODO */
		return TRUE;
		break;
	case CMD_GET_FW_VERSION:
		/* TODO */
		break;
	default:
		/* Unimplemented command. */
		break;
	}

	return FALSE;
}

BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	/* We only support interface 0, alternate interface 0. */
	if (ifc != 0)
		return FALSE;

	*alt_ifc = 0;
	return TRUE;
}

BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
{
	/* We only support interface 0, alternate interface 0. */
	if (ifc != 0 || alt_ifc != 0)
		return FALSE;
	
	/* Perform procedure from TRM, section 2.3.7: */

	/* (1) TODO. */

	/* (2) Reset data toggles of the EPs in the interface. */
	/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
	RESETTOGGLE(0x82);

	/* (3) Restore EPs to their default conditions. */
	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
	RESETFIFO(0x02);
	/* TODO */

	/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 1. */
	return 1;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 1. */
	return (cfg == 1) ? TRUE : FALSE;
}

void sudav_isr(void) interrupt SUDAV_ISR
{
	got_sud = TRUE;
	CLEAR_SUDAV();
}

void sof_isr(void) interrupt SOF_ISR using 1
{
	CLEAR_SOF();
}

void usbreset_isr(void) interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void main(void)
{
	/* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
	REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;

	got_sud = FALSE;

	/* Renumerate. */
	RENUMERATE_UNCOND();

	SETCPUFREQ(CLK_48M);

	USE_USB_INTS();

	/* TODO: Does the order of the following lines matter? */
	ENABLE_SUDAV();
	ENABLE_SOF();
	ENABLE_HISPEED();
	ENABLE_USBRESET();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Setup the endpoints. */
	setup_endpoints();

	/* Put the FX2 into GPIF master mode and setup the GPIF. */
	gpif_init_la();

	/* Perform the initial GPIF read. */
	gpif_fifo_read(GPIF_EP2);

	while (1) {
		if (got_sud) {
			handle_setupdata();
			got_sud = FALSE;
		}
	}
}
Commit	Line	Data
d5f5ea73 UH	1	/*
	2	* This file is part of the fx2lafw project.
	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
	21	/*
	22	* fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
	23	*
	24	* It is written in C, using fx2lib as helper library, and sdcc as compiler.
	25	* The code is licensed under the terms of the GNU GPL, version 2 or later.
	26	*
	27	* Technical notes:
	28	*
	29	* - We use the FX2 in GPIF mode to sample the data (asynchronously).
	30	* - We use the internal 48MHz clock for GPIF.
	31	* - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7.
	32	* Support for 16 channels is not yet included, but might be added later.
	33	* - Endpoint 2 is used for data transfers from FX2 to host.
	34	* - The endpoint is quad-buffered.
	35	*
	36	* Documentation:
	37	*
	38	* - See http://sigrok.org/wiki/Fx2lafw
	39	*/
	40
	41	#include <fx2regs.h>
	42	#include <fx2macros.h>
	43	#include <delay.h>
	44	#include <autovector.h>
	45	#include <setupdat.h>
	46	#include <eputils.h>
	47	#include <gpif.h>
	48
c7283c28 UH	49	/* Protocol commands */
	50	#define CMD_SET_SAMPLERATE 0xb0
	51	#define CMD_START 0xb1
	52	#define CMD_STOP 0xb2
	53	#define CMD_GET_FW_VERSION 0xb3
	54	/* ... */
	55
d5f5ea73 UH	56	#define SYNCDELAY() SYNCDELAY4
	57
	58	/* ... */
	59	volatile bit got_sud;
	60
	61	/* GPIF terminology: DP = decision point, NDP = non-decision-point */
	62
fb0b6d28 UH	63	/*
	64	* GPIF waveforms.
	65	*
	66	* See section "10.3.4 State Instructions" in the TRM for details.
	67	*/
d5f5ea73 UH	68	static const BYTE wavedata[128] = {
	69	/* Waveform 0: */
	70
fb0b6d28 UH	71	/*
	72	* This is the basic algorithm implemented in our GPIF state machine:
	73	*
	74	* State 0: NDP: Sample the FIFO data bus.
	75	* State 1: DP: If EP2 is full, go to state 7 (the IDLE state), i.e.,
	76	* end the current waveform. Otherwise, go to state 0 again,
	77	* i.e., sample data until EP2 is full.
	78	* State 2: Unused.
	79	* State 3: Unused.
	80	* State 4: Unused.
	81	* State 5: Unused.
	82	* State 6: Unused.
	83	*/
d5f5ea73 UH	84
d5f5ea73 UH	85	/* S0-S6: LENGTH/BRANCH */
fb0b6d28 UH	86	/*
	87	* For NDPs (LENGTH): Number of IFCLK cycles to stay in this state.
	88	* For DPs (BRANCH): [7] ReExec, [5:3]: BRANCHON1, [2:0]: BRANCHON0.
	89	*
	90	* 0x01: Stay one IFCLK cycle in this state.
	91	* 0x38: No Re-execution, BRANCHON1 = state 7, BRANCHON0 = state 0.
	92	*/
dc7ac8bf UH	93	// 0x01, 0x38, 0x01, 0x01, 0x01, 0x01, 0x01,
	94	// FIXME: For now just loop over the "sample data" state forever.
	95	0x01, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,
d5f5ea73 UH	96	/* TRM says "reserved", but GPIF designer always puts a 0x07 here. */
d5f5ea73 UH	97	0x07,
fb0b6d28	98
d5f5ea73	99	/* S0-S6: OPCODE */
fb0b6d28 UH	100	/*
	101	* 0x02: NDP, sample the FIFO data bus.
	102	* 0x01: DP, don't sample the FIFO data bus.
	103	*/
	104	0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
d5f5ea73 UH	105	/* Reserved */
d5f5ea73 UH	106	0x00,
fb0b6d28	107
d5f5ea73	108	/* S0-S6: OUTPUT */
fb0b6d28	109	/* Unused, we don't output anything, we only sample the pins. */
d5f5ea73 UH	110	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	111	/* Reserved */
	112	0x00,
fb0b6d28	113
d5f5ea73	114	/* S0-S6: LOGIC FUNCTION (not used for NDPs) */
fb0b6d28 UH	115	/*
	116	* 0x36: LFUNC = "A AND B", A = FIFO flag, B = FIFO flag.
	117	* The FIFO flag (FF == full flag, in our case) is configured via
	118	* EP2GPIFFLGSEL.
	119	*
	120	* So: If the EP2 FIFO is full and the EP2 FIFO is full, go to
	121	* the state specified by BRANCHON1 (state 7), otherwise BRANCHON0
	122	* (state 0). See the LENGTH/BRANCH value above for details.
	123	*/
	124	0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00,
d5f5ea73 UH	125	/* TRM says "reserved", but GPIF designer always puts a 0x3f here. */
	126	0x3f,
	127
	128	/* TODO: Must unused waveforms be "valid"? */
	129
	130	/* Waveform 1 (unused): */
	131	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	132	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	133	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	134	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	135
	136	/* Waveform 2 (unused): */
	137	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	138	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	139	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	140	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	141
	142	/* Waveform 3 (unused): */
	143	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	144	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	145	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	146	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
	147	};
	148
	149	static void gpif_setup_registers(void)
	150	{
	151	/* TODO. Value probably irrelevant, as we don't use RDY* signals? */
	152	GPIFREADYCFG = 0;
	153
	154	/*
	155	* Set TRICTL = 0, thus CTL0-CTL5 are CMOS outputs.
	156	* TODO: Probably irrelevant, as we don't use CTL0-CTL5?
	157	*/
	158	GPIFCTLCFG = 0;
	159
	160	/* When GPIF is idle, tri-state the data bus. */
	161	/* Bit 7: DONE, bit 0: IDLEDRV. TODO: Set/clear DONE bit? */
	162	GPIFIDLECS = (1 << 0);
	163
	164	/* When GPIF is idle, set CTL0-CTL5 to 0. */
	165	GPIFIDLECTL = 0;
	166
	167	/*
	168	* Map index 0 in wavedata[] to FIFORD. The rest is assigned too,
	169	* but not used by us.
	170	*
	171	* GPIFWFSELECT: [7:6] = SINGLEWR index, [5:4] = SINGLERD index,
	172	* [3:2] = FIFOWR index, [1:0] = FIFORD index
	173	*/
	174	GPIFWFSELECT = (0x3 << 6) \| (0x2 << 4) \| (0x1 << 2) \| (0x0 << 0);
	175
	176	/* Contains RDY* pin values. Read-only according to TRM. */
	177	GPIFREADYSTAT = 0;
	178	}
	179
	180	static void gpif_write_waveforms(void)
	181	{
	182	int i;
	183
	184	/*
	185	* Write the four waveforms into the respective WAVEDATA register
	186	* locations (0xe400 - 0xe47f) using the FX2's autopointer feature.
	187	*/
	188	AUTOPTRSETUP = 0x07; /* Increment autopointers 1 & 2. */
189	AUTOPTRH1 = MSB((WORD)wavedata); /* Source is the 'wavedata' array. */
190	AUTOPTRL1 = LSB((WORD)wavedata);
191	AUTOPTRH2 = 0xe4; /* Dest is WAVEDATA (0xe400). */
192	AUTOPTRL2 = 0x00;
193	for (i = 0; i < 128; i++)
194	EXTAUTODAT2 = EXTAUTODAT1;
195	}
196
197	static void gpif_init_addr_pins(void)
198	{
199	/*
200	* Configure the 9 GPIF address pins (GPIFADR[8:0], which consist of
201	* PORTC[7:0] and PORTE[7]), and output an initial address (zero).
202	* TODO: Probably irrelevant, the 56pin FX2 has no ports C and E.
203	*/
204	PORTCCFG = 0xff; /* Set PORTC[7:0] as alt. func. (GPIFADR[7:0]). */
205	OEC = 0xff; /* Configure PORTC[7:0] as outputs. */
206	PORTECFG \|= 0x80; /* Set PORTE[7] as alt. func. (GPIFADR[8]). */
207	OEE \|= 0x80; /* Configure PORTE[7] as output. */
208	SYNCDELAY();
209	GPIFADRL = 0x00; /* Clear GPIFADR[7:0]. */
210	SYNCDELAY();
211	GPIFADRH = 0x00; /* Clear GPIFADR[8]. */
212	}
213
214	static void gpif_init_flowstates(void)
215	{
216	/* Clear all flowstate registers, we don't use this functionality. */
217	FLOWSTATE = 0;
218	FLOWLOGIC = 0;
219	FLOWEQ0CTL = 0;
220	FLOWEQ1CTL = 0;
221	FLOWHOLDOFF = 0;
222	FLOWSTB = 0;
223	FLOWSTBEDGE = 0;
224	FLOWSTBHPERIOD = 0;
225	}
226
227	static void gpif_init_la(void)
228	{
229	/*
230	* Setup the FX2 in GPIF master mode, using the internal clock
231	* (non-inverted) at 48MHz, and using async sampling.
232	*/
233	IFCONFIG = 0xee;
234
235	/* Abort currently executing GPIF waveform (if any). */
236	GPIFABORT = 0xff;
237
238	/* Setup the GPIF registers. */
239	gpif_setup_registers();
240
241	/* Write the four GPIF waveforms into the WAVEDATA register. */
242	gpif_write_waveforms();
243
244	/* Initialize GPIF address pins, output initial values. */
245	gpif_init_addr_pins();
246
247	/* Initialize flowstate registers (not used by us). */
248	gpif_init_flowstates();
249	}
250
251	static void setup_endpoints(void)
252	{
d5f5ea73 UH	253	/* Setup EP2 (IN). */
	254	EP2CFG = (1 << 7) \| /* EP is valid/activated */
	255	(1 << 6) \| /* EP direction: IN */
	256	(1 << 5) \| (0 << 4) \| /* EP Type: bulk */
	257	(0 << 3) \| /* EP buffer size: 512 */
	258	(0 << 2) \| /* Reserved. */
	259	(0 << 1) \| (0 << 0); /* EP buffering: quad buffering */
	260	SYNCDELAY();
	261
4ad20a4c UH	262	/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
	263	EP1INCFG &= ~bmVALID;
	264	SYNCDELAY();
	265	EP1OUTCFG &= ~bmVALID;
	266	SYNCDELAY();
d5f5ea73 UH	267	EP4CFG &= ~bmVALID;
	268	SYNCDELAY();
	269	EP6CFG &= ~bmVALID;
	270	SYNCDELAY();
	271	EP8CFG &= ~bmVALID;
	272	SYNCDELAY();
	273
4ad20a4c	274	/* EP2: Reset the FIFOs. */
d5f5ea73	275	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73 UH	276	RESETFIFO(0x02)
d5f5ea73 UH	277
dc7ac8bf UH	278	/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
	279	EP2FIFOCFG = bmAUTOIN \| ~bmWORDWIDE;
	280	SYNCDELAY();
	281
	282	/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
	283	EP2AUTOINLENH = 0x02;
	284	SYNCDELAY();
	285	EP2AUTOINLENL = 0x00;
	286	SYNCDELAY();
	287
4ad20a4c	288	/* EP2: Set the GPIF flag to 'full'. */
fb0b6d28	289	EP2GPIFFLGSEL = (1 << 1) \| (0 << 1);
d5f5ea73 UH	290	SYNCDELAY();
	291	}
	292
	293	BOOL handle_vendorcommand(BYTE cmd)
	294	{
c7283c28 UH	295	/* Protocol implementation */
	296
	297	switch (cmd) {
	298	case CMD_SET_SAMPLERATE:
	299	/* TODO */
	300	break;
	301	case CMD_START:
	302	/* TODO */
	303	break;
	304	case CMD_STOP:
	305	GPIFABORT = 0xff;
	306	/* TODO */
	307	return TRUE;
	308	break;
	309	case CMD_GET_FW_VERSION:
	310	/* TODO */
	311	break;
	312	default:
	313	/* Unimplemented command. */
	314	break;
	315	}
4ad20a4c	316
d5f5ea73 UH	317	return FALSE;
	318	}
	319
	320	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	321	{
	322	/* We only support interface 0, alternate interface 0. */
	323	if (ifc != 0)
	324	return FALSE;
	325
	326	*alt_ifc = 0;
	327	return TRUE;
	328	}
	329
	330	BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
	331	{
	332	/* We only support interface 0, alternate interface 0. */
	333	if (ifc != 0 \|\| alt_ifc != 0)
	334	return FALSE;
	335
	336	/* Perform procedure from TRM, section 2.3.7: */
	337
	338	/* (1) TODO. */
	339
	340	/* (2) Reset data toggles of the EPs in the interface. */
	341	/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
d5f5ea73 UH	342	RESETTOGGLE(0x82);
	343
	344	/* (3) Restore EPs to their default conditions. */
	345	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73 UH	346	RESETFIFO(0x02);
	347	/* TODO */
	348
	349	/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
	350
	351	return TRUE;
	352	}
	353
	354	BYTE handle_get_configuration(void)
	355	{
	356	/* We only support configuration 1. */
	357	return 1;
	358	}
	359
	360	BOOL handle_set_configuration(BYTE cfg)
	361	{
	362	/* We only support configuration 1. */
	363	return (cfg == 1) ? TRUE : FALSE;
	364	}
	365
	366	void sudav_isr(void) interrupt SUDAV_ISR
	367	{
	368	got_sud = TRUE;
	369	CLEAR_SUDAV();
	370	}
	371
	372	void sof_isr(void) interrupt SOF_ISR using 1
	373	{
	374	CLEAR_SOF();
	375	}
	376
	377	void usbreset_isr(void) interrupt USBRESET_ISR
	378	{
	379	handle_hispeed(FALSE);
	380	CLEAR_USBRESET();
	381	}
	382
	383	void hispeed_isr(void) interrupt HISPEED_ISR
	384	{
	385	handle_hispeed(TRUE);
	386	CLEAR_HISPEED();
	387	}
	388
	389	void main(void)
	390	{
	391	/* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
e7434142	392	REVCTL = bmNOAUTOARM \| bmSKIPCOMMIT;
d5f5ea73 UH	393
	394	got_sud = FALSE;
	395
	396	/* Renumerate. */
	397	RENUMERATE_UNCOND();
	398
	399	SETCPUFREQ(CLK_48M);
	400
	401	USE_USB_INTS();
	402
	403	/* TODO: Does the order of the following lines matter? */
	404	ENABLE_SUDAV();
	405	ENABLE_SOF();
	406	ENABLE_HISPEED();
	407	ENABLE_USBRESET();
	408
	409	/* Global (8051) interrupt enable. */
	410	EA = 1;
	411
	412	/* Setup the endpoints. */
	413	setup_endpoints();
	414
	415	/* Put the FX2 into GPIF master mode and setup the GPIF. */
	416	gpif_init_la();
	417
dc7ac8bf	418	/* Perform the initial GPIF read. */
d5f5ea73	419	gpif_fifo_read(GPIF_EP2);
d5f5ea73 UH	420
	421	while (1) {
	422	if (got_sud) {
	423	handle_setupdata();
	424	got_sud = FALSE;
	425	}
	426	}
	427	}