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Commit | Line | Data |
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d5f5ea73 UH |
1 | /* |
2 | * This file is part of the fx2lafw project. | |
3 | * | |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
21 | /* | |
22 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
23 | * | |
24 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
25 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
26 | * | |
27 | * Technical notes: | |
28 | * | |
29 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
30 | * - We use the internal 48MHz clock for GPIF. | |
31 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7. | |
32 | * Support for 16 channels is not yet included, but might be added later. | |
33 | * - Endpoint 2 is used for data transfers from FX2 to host. | |
34 | * - The endpoint is quad-buffered. | |
35 | * | |
36 | * Documentation: | |
37 | * | |
38 | * - See http://sigrok.org/wiki/Fx2lafw | |
39 | */ | |
40 | ||
41 | #include <fx2regs.h> | |
42 | #include <fx2macros.h> | |
43 | #include <delay.h> | |
d5f5ea73 UH |
44 | #include <setupdat.h> |
45 | #include <eputils.h> | |
46 | #include <gpif.h> | |
e41576ec | 47 | |
64d47730 | 48 | #include <command.h> |
8f4a701f | 49 | #include <fx2lafw.h> |
e41576ec | 50 | #include <gpif-acquisition.h> |
d5f5ea73 | 51 | |
d5f5ea73 | 52 | /* ... */ |
8819f75c | 53 | volatile __bit got_sud; |
2846a114 | 54 | BYTE vendor_command; |
d5f5ea73 | 55 | |
d5f5ea73 UH |
56 | static void setup_endpoints(void) |
57 | { | |
d5f5ea73 UH |
58 | /* Setup EP2 (IN). */ |
59 | EP2CFG = (1 << 7) | /* EP is valid/activated */ | |
60 | (1 << 6) | /* EP direction: IN */ | |
61 | (1 << 5) | (0 << 4) | /* EP Type: bulk */ | |
5a95b634 | 62 | (1 << 3) | /* EP buffer size: 1024 */ |
d5f5ea73 UH |
63 | (0 << 2) | /* Reserved. */ |
64 | (0 << 1) | (0 << 0); /* EP buffering: quad buffering */ | |
65 | SYNCDELAY(); | |
66 | ||
576c6627 | 67 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ |
4ad20a4c UH |
68 | EP1INCFG &= ~bmVALID; |
69 | SYNCDELAY(); | |
70 | EP1OUTCFG &= ~bmVALID; | |
71 | SYNCDELAY(); | |
d5f5ea73 UH |
72 | EP4CFG &= ~bmVALID; |
73 | SYNCDELAY(); | |
576c6627 JH |
74 | EP6CFG &= ~bmVALID; |
75 | SYNCDELAY(); | |
d5f5ea73 UH |
76 | EP8CFG &= ~bmVALID; |
77 | SYNCDELAY(); | |
78 | ||
4ad20a4c | 79 | /* EP2: Reset the FIFOs. */ |
d5f5ea73 | 80 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ |
d5f5ea73 | 81 | RESETFIFO(0x02) |
2d62ae47 | 82 | |
dc7ac8bf | 83 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ |
2d62ae47 | 84 | EP2FIFOCFG = bmAUTOIN; |
dc7ac8bf UH |
85 | SYNCDELAY(); |
86 | ||
87 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
88 | EP2AUTOINLENH = 0x02; | |
89 | SYNCDELAY(); | |
90 | EP2AUTOINLENL = 0x00; | |
91 | SYNCDELAY(); | |
92 | ||
4ad20a4c | 93 | /* EP2: Set the GPIF flag to 'full'. */ |
fb0b6d28 | 94 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); |
d5f5ea73 UH |
95 | SYNCDELAY(); |
96 | } | |
97 | ||
18544912 JH |
98 | static void send_fw_version(void) |
99 | { | |
cd29817d UH |
100 | /* Populate the buffer. */ |
101 | struct version_info *const vi = (struct version_info *)EP0BUF; | |
18544912 JH |
102 | vi->major = FX2LAFW_VERSION_MAJOR; |
103 | vi->minor = FX2LAFW_VERSION_MINOR; | |
104 | ||
cd29817d | 105 | /* Send the message. */ |
18544912 JH |
106 | EP0BCH = 0; |
107 | EP0BCL = sizeof(struct version_info); | |
108 | } | |
109 | ||
c23ad602 UH |
110 | static void send_revid_version(void) |
111 | { | |
112 | uint8_t *p; | |
113 | ||
114 | /* Populate the buffer. */ | |
115 | p = (uint8_t *)EP0BUF; | |
116 | *p = REVID; | |
117 | ||
118 | /* Send the message. */ | |
119 | EP0BCH = 0; | |
120 | EP0BCL = 1; | |
121 | } | |
122 | ||
d5f5ea73 UH |
123 | BOOL handle_vendorcommand(BYTE cmd) |
124 | { | |
c7283c28 | 125 | /* Protocol implementation */ |
c7283c28 | 126 | switch (cmd) { |
3b6919fa | 127 | case CMD_START: |
18544912 | 128 | vendor_command = cmd; |
2846a114 | 129 | EP0BCL = 0; |
18544912 | 130 | return TRUE; |
cd29817d | 131 | break; |
2846a114 | 132 | case CMD_GET_FW_VERSION: |
18544912 | 133 | send_fw_version(); |
3b6919fa | 134 | return TRUE; |
cd29817d | 135 | break; |
c23ad602 UH |
136 | case CMD_GET_REVID_VERSION: |
137 | send_revid_version(); | |
138 | return TRUE; | |
139 | break; | |
c7283c28 | 140 | } |
4ad20a4c | 141 | |
d5f5ea73 UH |
142 | return FALSE; |
143 | } | |
144 | ||
145 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
146 | { | |
147 | /* We only support interface 0, alternate interface 0. */ | |
148 | if (ifc != 0) | |
149 | return FALSE; | |
150 | ||
151 | *alt_ifc = 0; | |
152 | return TRUE; | |
153 | } | |
154 | ||
155 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
156 | { | |
157 | /* We only support interface 0, alternate interface 0. */ | |
158 | if (ifc != 0 || alt_ifc != 0) | |
159 | return FALSE; | |
160 | ||
161 | /* Perform procedure from TRM, section 2.3.7: */ | |
162 | ||
163 | /* (1) TODO. */ | |
164 | ||
165 | /* (2) Reset data toggles of the EPs in the interface. */ | |
166 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
d5f5ea73 | 167 | RESETTOGGLE(0x82); |
106ee45c UH |
168 | #ifdef DEBUG |
169 | RESETTOGGLE(0x86); | |
170 | #endif | |
d5f5ea73 UH |
171 | |
172 | /* (3) Restore EPs to their default conditions. */ | |
173 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
d5f5ea73 UH |
174 | RESETFIFO(0x02); |
175 | /* TODO */ | |
106ee45c | 176 | #ifdef DEBUG |
c430e296 | 177 | RESETFIFO(0x06); |
106ee45c | 178 | #endif |
c430e296 | 179 | |
d5f5ea73 UH |
180 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ |
181 | ||
182 | return TRUE; | |
183 | } | |
184 | ||
185 | BYTE handle_get_configuration(void) | |
186 | { | |
187 | /* We only support configuration 1. */ | |
188 | return 1; | |
189 | } | |
190 | ||
191 | BOOL handle_set_configuration(BYTE cfg) | |
192 | { | |
193 | /* We only support configuration 1. */ | |
194 | return (cfg == 1) ? TRUE : FALSE; | |
195 | } | |
196 | ||
8819f75c | 197 | void sudav_isr(void) __interrupt SUDAV_ISR |
d5f5ea73 UH |
198 | { |
199 | got_sud = TRUE; | |
200 | CLEAR_SUDAV(); | |
201 | } | |
202 | ||
8819f75c | 203 | void sof_isr(void) __interrupt SOF_ISR __using 1 |
d5f5ea73 UH |
204 | { |
205 | CLEAR_SOF(); | |
206 | } | |
207 | ||
8819f75c | 208 | void usbreset_isr(void) __interrupt USBRESET_ISR |
d5f5ea73 UH |
209 | { |
210 | handle_hispeed(FALSE); | |
211 | CLEAR_USBRESET(); | |
212 | } | |
213 | ||
8819f75c | 214 | void hispeed_isr(void) __interrupt HISPEED_ISR |
d5f5ea73 UH |
215 | { |
216 | handle_hispeed(TRUE); | |
217 | CLEAR_HISPEED(); | |
218 | } | |
219 | ||
1cbff47d | 220 | void fx2lafw_init(void) |
d5f5ea73 UH |
221 | { |
222 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
e7434142 | 223 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; |
d5f5ea73 UH |
224 | |
225 | got_sud = FALSE; | |
2846a114 | 226 | vendor_command = 0; |
d5f5ea73 UH |
227 | |
228 | /* Renumerate. */ | |
229 | RENUMERATE_UNCOND(); | |
230 | ||
231 | SETCPUFREQ(CLK_48M); | |
232 | ||
233 | USE_USB_INTS(); | |
234 | ||
235 | /* TODO: Does the order of the following lines matter? */ | |
236 | ENABLE_SUDAV(); | |
237 | ENABLE_SOF(); | |
238 | ENABLE_HISPEED(); | |
239 | ENABLE_USBRESET(); | |
240 | ||
241 | /* Global (8051) interrupt enable. */ | |
242 | EA = 1; | |
243 | ||
244 | /* Setup the endpoints. */ | |
245 | setup_endpoints(); | |
246 | ||
247 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
248 | gpif_init_la(); | |
1cbff47d | 249 | } |
d5f5ea73 | 250 | |
28d52f41 | 251 | void fx2lafw_poll(void) |
1cbff47d JH |
252 | { |
253 | if (got_sud) { | |
254 | handle_setupdata(); | |
255 | got_sud = FALSE; | |
d5f5ea73 | 256 | } |
2846a114 JH |
257 | |
258 | if (vendor_command) { | |
259 | switch (vendor_command) { | |
2846a114 | 260 | case CMD_START: |
cd29817d | 261 | if ((EP0CS & bmEPBUSY) != 0) |
2846a114 JH |
262 | break; |
263 | ||
75630581 | 264 | if (EP0BCL == sizeof(struct cmd_start_acquisition)) { |
2846a114 | 265 | gpif_acquisition_start( |
cd29817d | 266 | (const struct cmd_start_acquisition *)EP0BUF); |
2846a114 JH |
267 | } |
268 | ||
269 | /* Acknowledge the vendor command. */ | |
270 | vendor_command = 0; | |
271 | break; | |
2846a114 JH |
272 | default: |
273 | /* Unimplemented command. */ | |
274 | vendor_command = 0; | |
275 | break; | |
276 | } | |
277 | } | |
293d7e9e JH |
278 | |
279 | gpif_poll(); | |
d5f5ea73 | 280 | } |
f7f91781 JH |
281 | |
282 | void main(void) | |
283 | { | |
284 | fx2lafw_init(); | |
285 | while (1) | |
286 | fx2lafw_poll(); | |
287 | } |