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1/*
2 * This file is part of the fx2lafw project.
3 *
4 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
23 *
24 * It is written in C, using fx2lib as helper library, and sdcc as compiler.
25 * The code is licensed under the terms of the GNU GPL, version 2 or later.
26 *
27 * Technical notes:
28 *
29 * - We use the FX2 in GPIF mode to sample the data (asynchronously).
30 * - We use the internal 48MHz clock for GPIF.
31 * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7.
32 * Support for 16 channels is not yet included, but might be added later.
33 * - Endpoint 2 is used for data transfers from FX2 to host.
34 * - The endpoint is quad-buffered.
35 *
36 * Documentation:
37 *
38 * - See http://sigrok.org/wiki/Fx2lafw
39 */
40
41#include <fx2regs.h>
42#include <fx2macros.h>
43#include <delay.h>
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44#include <setupdat.h>
45#include <eputils.h>
46#include <gpif.h>
e41576ec 47
64d47730 48#include <command.h>
8f4a701f 49#include <fx2lafw.h>
e41576ec 50#include <gpif-acquisition.h>
d5f5ea73 51
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52/* ... */
53volatile bit got_sud;
2846a114 54BYTE vendor_command;
d5f5ea73 55
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56static void setup_endpoints(void)
57{
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58 /* Setup EP2 (IN). */
59 EP2CFG = (1 << 7) | /* EP is valid/activated */
60 (1 << 6) | /* EP direction: IN */
61 (1 << 5) | (0 << 4) | /* EP Type: bulk */
62 (0 << 3) | /* EP buffer size: 512 */
63 (0 << 2) | /* Reserved. */
64 (0 << 1) | (0 << 0); /* EP buffering: quad buffering */
65 SYNCDELAY();
66
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67 /* Setup EP6 (IN) in the debug build. */
68#ifdef DEBUG
69 EP6CFG = (1 << 7) | /* EP is valid/activated */
70 (1 << 6) | /* EP direction: IN */
71 (1 << 5) | (0 << 4) | /* EP Type: bulk */
72 (0 << 3) | /* EP buffer size: 512 */
73 (0 << 2) | /* Reserved */
74 (1 << 1) | (0 << 0); /* EP buffering: double buffering */
75#else
76 EP6CFG &= ~bmVALID;
77#endif
78 SYNCDELAY();
79
106ee45c 80 /* Disable all other EPs (EP1, EP4, and EP8). */
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81 EP1INCFG &= ~bmVALID;
82 SYNCDELAY();
83 EP1OUTCFG &= ~bmVALID;
84 SYNCDELAY();
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85 EP4CFG &= ~bmVALID;
86 SYNCDELAY();
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87 EP8CFG &= ~bmVALID;
88 SYNCDELAY();
89
4ad20a4c 90 /* EP2: Reset the FIFOs. */
d5f5ea73 91 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73 92 RESETFIFO(0x02)
2d62ae47 93
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94#ifdef DEBUG
95 /* Reset the FIFOs of EP6 when in debug mode. */
96 RESETFIFO(0x06)
97#endif
d5f5ea73 98
dc7ac8bf 99 /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
2d62ae47 100 EP2FIFOCFG = bmAUTOIN;
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101 SYNCDELAY();
102
103 /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
104 EP2AUTOINLENH = 0x02;
105 SYNCDELAY();
106 EP2AUTOINLENL = 0x00;
107 SYNCDELAY();
108
4ad20a4c 109 /* EP2: Set the GPIF flag to 'full'. */
fb0b6d28 110 EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
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111 SYNCDELAY();
112}
113
114BOOL handle_vendorcommand(BYTE cmd)
115{
c7283c28 116 /* Protocol implementation */
c7283c28 117 switch (cmd) {
3b6919fa 118 case CMD_START:
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119 /* There is data to receive - arm EP0 */
120 EP0BCL = 0;
121 case CMD_GET_FW_VERSION:
122 vendor_command = cmd;
3b6919fa 123 return TRUE;
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124 default:
125 /* Unimplemented command. */
126 break;
127 }
4ad20a4c 128
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129 return FALSE;
130}
131
132BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
133{
134 /* We only support interface 0, alternate interface 0. */
135 if (ifc != 0)
136 return FALSE;
137
138 *alt_ifc = 0;
139 return TRUE;
140}
141
142BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
143{
144 /* We only support interface 0, alternate interface 0. */
145 if (ifc != 0 || alt_ifc != 0)
146 return FALSE;
147
148 /* Perform procedure from TRM, section 2.3.7: */
149
150 /* (1) TODO. */
151
152 /* (2) Reset data toggles of the EPs in the interface. */
153 /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
d5f5ea73 154 RESETTOGGLE(0x82);
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155#ifdef DEBUG
156 RESETTOGGLE(0x86);
157#endif
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158
159 /* (3) Restore EPs to their default conditions. */
160 /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
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161 RESETFIFO(0x02);
162 /* TODO */
106ee45c 163#ifdef DEBUG
c430e296 164 RESETFIFO(0x06);
106ee45c 165#endif
c430e296 166
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167 /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
168
169 return TRUE;
170}
171
172BYTE handle_get_configuration(void)
173{
174 /* We only support configuration 1. */
175 return 1;
176}
177
178BOOL handle_set_configuration(BYTE cfg)
179{
180 /* We only support configuration 1. */
181 return (cfg == 1) ? TRUE : FALSE;
182}
183
184void sudav_isr(void) interrupt SUDAV_ISR
185{
186 got_sud = TRUE;
187 CLEAR_SUDAV();
188}
189
190void sof_isr(void) interrupt SOF_ISR using 1
191{
192 CLEAR_SOF();
193}
194
195void usbreset_isr(void) interrupt USBRESET_ISR
196{
197 handle_hispeed(FALSE);
198 CLEAR_USBRESET();
199}
200
201void hispeed_isr(void) interrupt HISPEED_ISR
202{
203 handle_hispeed(TRUE);
204 CLEAR_HISPEED();
205}
206
1cbff47d 207void fx2lafw_init(void)
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208{
209 /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
e7434142 210 REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;
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211
212 got_sud = FALSE;
2846a114 213 vendor_command = 0;
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214
215 /* Renumerate. */
216 RENUMERATE_UNCOND();
217
218 SETCPUFREQ(CLK_48M);
219
220 USE_USB_INTS();
221
222 /* TODO: Does the order of the following lines matter? */
223 ENABLE_SUDAV();
224 ENABLE_SOF();
225 ENABLE_HISPEED();
226 ENABLE_USBRESET();
227
228 /* Global (8051) interrupt enable. */
229 EA = 1;
230
231 /* Setup the endpoints. */
232 setup_endpoints();
233
234 /* Put the FX2 into GPIF master mode and setup the GPIF. */
235 gpif_init_la();
1cbff47d 236}
d5f5ea73 237
28d52f41 238void fx2lafw_poll(void)
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239{
240 if (got_sud) {
241 handle_setupdata();
242 got_sud = FALSE;
d5f5ea73 243 }
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244
245 if (vendor_command) {
246 switch (vendor_command) {
247 case CMD_GET_FW_VERSION:
248 /* TODO */
249
250 /* Acknowledge the vendor command. */
251 vendor_command = 0;
252 break;
253
254 case CMD_START:
255 if((EP0CS & bmEPBUSY) != 0)
256 break;
257
258 if(EP0BCL == 2) {
259 gpif_acquisition_start(
260 (const struct cmd_start_acquisition*)EP0BUF);
261 }
262
263 /* Acknowledge the vendor command. */
264 vendor_command = 0;
265 break;
266
267 default:
268 /* Unimplemented command. */
269 vendor_command = 0;
270 break;
271 }
272 }
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273
274 gpif_poll();
d5f5ea73 275}