[sigrok-firmware-fx2lafw.git] / fx2lafw.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

/*
 * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
 *
 * It is written in C, using fx2lib as helper library, and sdcc as compiler.
 * The code is licensed under the terms of the GNU GPL, version 2 or later.
 *
 * Technical notes:
 *
 *  - We use the FX2 in GPIF mode to sample the data (asynchronously).
 *  - We use the internal 48MHz clock for GPIF.
 *  - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7,
 *    or PB0-PB7 + PD0-PD7 for 16-channel sampling. 
 *  - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host.
 *
 * Documentation:
 *
 *  - See http://sigrok.org/wiki/Fx2lafw
 */

#include <fx2regs.h>
#include <fx2macros.h>
#include <fx2ints.h>
#include <delay.h>
#include <setupdat.h>
#include <eputils.h>
#include <gpif.h>
#include <command.h>
#include <fx2lafw.h>
#include <gpif-acquisition.h>

/* ... */
volatile __bit got_sud;
BYTE vendor_command;

volatile WORD ledcounter = 0;

static void setup_endpoints(void)
{
	/* Setup EP2 (IN). */
	EP2CFG = (1 << 7) |		  /* EP is valid/activated */
		 (1 << 6) |		  /* EP direction: IN */
		 (1 << 5) | (0 << 4) |	  /* EP Type: bulk */
		 (1 << 3) |		  /* EP buffer size: 1024 */
		 (0 << 2) |		  /* Reserved. */
		 (0 << 1) | (0 << 0);	  /* EP buffering: quad buffering */
	SYNCDELAY();

	/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
	EP1INCFG &= ~bmVALID;
	SYNCDELAY();
	EP1OUTCFG &= ~bmVALID;
	SYNCDELAY();
	EP4CFG &= ~bmVALID;
	SYNCDELAY();
	EP6CFG &= ~bmVALID;
	SYNCDELAY();
	EP8CFG &= ~bmVALID;
	SYNCDELAY();

	/* EP2: Reset the FIFOs. */
	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
	RESETFIFO(0x02)

	/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
	EP2FIFOCFG = bmAUTOIN;
	SYNCDELAY();

	/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
	EP2AUTOINLENH = 0x02;
	SYNCDELAY();
	EP2AUTOINLENL = 0x00;
	SYNCDELAY();

	/* EP2: Set the GPIF flag to 'full'. */
	EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
	SYNCDELAY();
}

static void send_fw_version(void)
{
	/* Populate the buffer. */
	struct version_info *const vi = (struct version_info *)EP0BUF;
	vi->major = FX2LAFW_VERSION_MAJOR;
	vi->minor = FX2LAFW_VERSION_MINOR;

	/* Send the message. */
	EP0BCH = 0;
	EP0BCL = sizeof(struct version_info);
}

static void send_revid_version(void)
{
	uint8_t *p;

	/* Populate the buffer. */
	p = (uint8_t *)EP0BUF;
	*p = REVID;

	/* Send the message. */
	EP0BCH = 0;
	EP0BCL = 1;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	/* Protocol implementation */
	switch (cmd) {
	case CMD_START:
		/* Tell hardware we are ready to receive data. */
		vendor_command = cmd;
		EP0BCL = 0;
		return TRUE;
	case CMD_GET_FW_VERSION:
		send_fw_version();
		return TRUE;
	case CMD_GET_REVID_VERSION:
		send_revid_version();
		return TRUE;
	}

	return FALSE;
}

BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	/* We only support interface 0, alternate interface 0. */
	if (ifc != 0)
		return FALSE;

	*alt_ifc = 0;
	return TRUE;
}

BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
{
	/* We only support interface 0, alternate interface 0. */
	if (ifc != 0 || alt_ifc != 0)
		return FALSE;

	/* Perform procedure from TRM, section 2.3.7: */

	/* (1) TODO. */

	/* (2) Reset data toggles of the EPs in the interface. */
	/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
	RESETTOGGLE(0x82);

	/* (3) Restore EPs to their default conditions. */
	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
	RESETFIFO(0x02);
	/* TODO */

	/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 1. */
	return 1;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 1. */
	return (cfg == 1) ? TRUE : FALSE;
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	got_sud = TRUE;
	CLEAR_SUDAV();
}

/* IN BULK NAK - the host started requesting data. */
void ibn_isr(void) __interrupt IBN_ISR
{
	/*
	 * If the IBN interrupt is not disabled, clearing
	 * does not work. See AN78446, 6.2.
	 */
	BYTE ibnsave = IBNIE;
	IBNIE = 0;
	CLEAR_USBINT();

	/*
	 * If the host sent the START command, start the GPIF
	 * engine. The host will repeat the BULK IN in the next
	 * microframe.
	 */
	if ((IBNIRQ & bmEP2IBN) && (gpif_acquiring == PREPARED)) {
		ledcounter = 1;
		PA1 = 0;
		gpif_acquisition_start();
	}

	/* Clear IBN flags for all EPs. */
	IBNIRQ = 0xff;

	NAKIRQ = bmIBN;
	SYNCDELAY();

	IBNIE = ibnsave;
	SYNCDELAY();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	/* Blink LED during acquisition, keep it on otherwise. */
	if (gpif_acquiring == RUNNING) {
		if (--ledcounter == 0) {
			PA1 = !PA1;
			ledcounter = 1000;
		}
	} else if (gpif_acquiring == STOPPED) {
		PA1 = 1; /* LED on. */
	}
	TF2 = 0;
}

void fx2lafw_init(void)
{
	/* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
	REVCTL = bmNOAUTOARM | bmSKIPCOMMIT;

	got_sud = FALSE;
	vendor_command = 0;

	/* Renumerate. */
	RENUMERATE_UNCOND();

	SETCPUFREQ(CLK_48M);

	USE_USB_INTS();

	/* TODO: Does the order of the following lines matter? */
	ENABLE_SUDAV();
	ENABLE_EP2IBN();
	ENABLE_HISPEED();
	ENABLE_USBRESET();

	/* PA1 (LED) is an output. */
	PORTACFG = 0;
	OEA = (1 << 1);
	PA1 = 1; /* LED on. */

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Setup the endpoints. */
	setup_endpoints();

	/* Put the FX2 into GPIF master mode and setup the GPIF. */
	gpif_init_la();
}

void fx2lafw_poll(void)
{
	if (got_sud) {
		handle_setupdata();
		got_sud = FALSE;
	}

	if (vendor_command) {
		switch (vendor_command) {
		case CMD_START:
			if ((EP0CS & bmEPBUSY) != 0)
				break;

			if (EP0BCL == sizeof(struct cmd_start_acquisition)) {
				gpif_acquisition_prepare(
				 (const struct cmd_start_acquisition *)EP0BUF);
			}

			/* Acknowledge the vendor command. */
			vendor_command = 0;
			break;
		default:
			/* Unimplemented command. */
			vendor_command = 0;
			break;
		}
	}

	gpif_poll();
}

void main(void)
{
	fx2lafw_init();
	while (1)
		fx2lafw_poll();
}
Commit	Line	Data
d5f5ea73	1	/*
a986cfff	2	* This file is part of the sigrok-firmware-fx2lafw project.
d5f5ea73 UH	3	*
	4	* Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
040a6eae	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
d5f5ea73 UH	18	*/
	19
	20	/*
	21	* fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers.
	22	*
	23	* It is written in C, using fx2lib as helper library, and sdcc as compiler.
	24	* The code is licensed under the terms of the GNU GPL, version 2 or later.
	25	*
	26	* Technical notes:
	27	*
	28	* - We use the FX2 in GPIF mode to sample the data (asynchronously).
	29	* - We use the internal 48MHz clock for GPIF.
c7e02d8c UH	30	* - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7,
	31	* or PB0-PB7 + PD0-PD7 for 16-channel sampling.
	32	* - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host.
d5f5ea73 UH	33	*
	34	* Documentation:
	35	*
	36	* - See http://sigrok.org/wiki/Fx2lafw
	37	*/
	38
	39	#include <fx2regs.h>
	40	#include <fx2macros.h>
cf43e09a	41	#include <fx2ints.h>
d5f5ea73	42	#include <delay.h>
d5f5ea73 UH	43	#include <setupdat.h>
	44	#include <eputils.h>
	45	#include <gpif.h>
64d47730	46	#include <command.h>
8f4a701f	47	#include <fx2lafw.h>
e41576ec	48	#include <gpif-acquisition.h>
d5f5ea73	49
d5f5ea73	50	/* ... */
8819f75c	51	volatile __bit got_sud;
2846a114	52	BYTE vendor_command;
d5f5ea73	53
cfeb1a36	54	volatile WORD ledcounter = 0;
cf43e09a	55
d5f5ea73 UH	56	static void setup_endpoints(void)
d5f5ea73 UH	57	{
d5f5ea73 UH	58	/* Setup EP2 (IN). */
	59	EP2CFG = (1 << 7) \| /* EP is valid/activated */
	60	(1 << 6) \| /* EP direction: IN */
	61	(1 << 5) \| (0 << 4) \| /* EP Type: bulk */
5a95b634	62	(1 << 3) \| /* EP buffer size: 1024 */
d5f5ea73 UH	63	(0 << 2) \| /* Reserved. */
	64	(0 << 1) \| (0 << 0); /* EP buffering: quad buffering */
	65	SYNCDELAY();
	66
576c6627	67	/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
4ad20a4c UH	68	EP1INCFG &= ~bmVALID;
	69	SYNCDELAY();
	70	EP1OUTCFG &= ~bmVALID;
	71	SYNCDELAY();
d5f5ea73 UH	72	EP4CFG &= ~bmVALID;
d5f5ea73 UH	73	SYNCDELAY();
576c6627 JH	74	EP6CFG &= ~bmVALID;
576c6627 JH	75	SYNCDELAY();
d5f5ea73 UH	76	EP8CFG &= ~bmVALID;
	77	SYNCDELAY();
	78
4ad20a4c	79	/* EP2: Reset the FIFOs. */
d5f5ea73	80	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73	81	RESETFIFO(0x02)
2d62ae47	82
dc7ac8bf	83	/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
2d62ae47	84	EP2FIFOCFG = bmAUTOIN;
dc7ac8bf UH	85	SYNCDELAY();
	86
	87	/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
	88	EP2AUTOINLENH = 0x02;
	89	SYNCDELAY();
	90	EP2AUTOINLENL = 0x00;
	91	SYNCDELAY();
	92
4ad20a4c	93	/* EP2: Set the GPIF flag to 'full'. */
fb0b6d28	94	EP2GPIFFLGSEL = (1 << 1) \| (0 << 1);
d5f5ea73 UH	95	SYNCDELAY();
	96	}
	97
18544912 JH	98	static void send_fw_version(void)
18544912 JH	99	{
cd29817d UH	100	/* Populate the buffer. */
cd29817d UH	101	struct version_info const vi = (struct version_info )EP0BUF;
18544912 JH	102	vi->major = FX2LAFW_VERSION_MAJOR;
	103	vi->minor = FX2LAFW_VERSION_MINOR;
	104
cd29817d	105	/* Send the message. */
18544912 JH	106	EP0BCH = 0;
	107	EP0BCL = sizeof(struct version_info);
	108	}
	109
c23ad602 UH	110	static void send_revid_version(void)
	111	{
	112	uint8_t *p;
	113
	114	/* Populate the buffer. */
	115	p = (uint8_t *)EP0BUF;
	116	*p = REVID;
	117
	118	/* Send the message. */
	119	EP0BCH = 0;
	120	EP0BCL = 1;
	121	}
	122
d5f5ea73 UH	123	BOOL handle_vendorcommand(BYTE cmd)
d5f5ea73 UH	124	{
c7283c28	125	/* Protocol implementation */
c7283c28	126	switch (cmd) {
3b6919fa	127	case CMD_START:
cfeb1a36	128	/* Tell hardware we are ready to receive data. */
18544912	129	vendor_command = cmd;
2846a114	130	EP0BCL = 0;
18544912	131	return TRUE;
2846a114	132	case CMD_GET_FW_VERSION:
18544912	133	send_fw_version();
3b6919fa	134	return TRUE;
c23ad602 UH	135	case CMD_GET_REVID_VERSION:
	136	send_revid_version();
	137	return TRUE;
c7283c28	138	}
4ad20a4c	139
d5f5ea73 UH	140	return FALSE;
	141	}
	142
	143	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	144	{
	145	/* We only support interface 0, alternate interface 0. */
	146	if (ifc != 0)
	147	return FALSE;
	148
	149	*alt_ifc = 0;
	150	return TRUE;
	151	}
	152
	153	BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
	154	{
	155	/* We only support interface 0, alternate interface 0. */
	156	if (ifc != 0 \|\| alt_ifc != 0)
	157	return FALSE;
c7e02d8c	158
d5f5ea73 UH	159	/* Perform procedure from TRM, section 2.3.7: */
	160
	161	/* (1) TODO. */
	162
	163	/* (2) Reset data toggles of the EPs in the interface. */
	164	/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
d5f5ea73 UH	165	RESETTOGGLE(0x82);
	166
	167	/* (3) Restore EPs to their default conditions. */
	168	/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
d5f5ea73 UH	169	RESETFIFO(0x02);
d5f5ea73 UH	170	/* TODO */
c430e296	171
d5f5ea73 UH	172	/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
	173
	174	return TRUE;
	175	}
	176
	177	BYTE handle_get_configuration(void)
	178	{
	179	/* We only support configuration 1. */
	180	return 1;
	181	}
	182
	183	BOOL handle_set_configuration(BYTE cfg)
	184	{
	185	/* We only support configuration 1. */
	186	return (cfg == 1) ? TRUE : FALSE;
	187	}
	188
8819f75c	189	void sudav_isr(void) __interrupt SUDAV_ISR
d5f5ea73 UH	190	{
	191	got_sud = TRUE;
	192	CLEAR_SUDAV();
	193	}
	194
cfeb1a36 SB	195	/* IN BULK NAK - the host started requesting data. */
	196	void ibn_isr(void) __interrupt IBN_ISR
	197	{
	198	/*
	199	* If the IBN interrupt is not disabled, clearing
	200	* does not work. See AN78446, 6.2.
	201	*/
	202	BYTE ibnsave = IBNIE;
	203	IBNIE = 0;
	204	CLEAR_USBINT();
	205
	206	/*
	207	* If the host sent the START command, start the GPIF
	208	* engine. The host will repeat the BULK IN in the next
	209	* microframe.
	210	*/
	211	if ((IBNIRQ & bmEP2IBN) && (gpif_acquiring == PREPARED)) {
	212	ledcounter = 1;
	213	PA1 = 0;
	214	gpif_acquisition_start();
	215	}
	216
	217	/* Clear IBN flags for all EPs. */
	218	IBNIRQ = 0xff;
	219
	220	NAKIRQ = bmIBN;
	221	SYNCDELAY();
	222
	223	IBNIE = ibnsave;
	224	SYNCDELAY();
	225	}
	226
8819f75c	227	void usbreset_isr(void) __interrupt USBRESET_ISR
d5f5ea73 UH	228	{
	229	handle_hispeed(FALSE);
	230	CLEAR_USBRESET();
	231	}
	232
8819f75c	233	void hispeed_isr(void) __interrupt HISPEED_ISR
d5f5ea73 UH	234	{
	235	handle_hispeed(TRUE);
	236	CLEAR_HISPEED();
	237	}
	238
cf43e09a UH	239	void timer2_isr(void) __interrupt TF2_ISR
	240	{
	241	/* Blink LED during acquisition, keep it on otherwise. */
cfeb1a36	242	if (gpif_acquiring == RUNNING) {
cf43e09a UH	243	if (--ledcounter == 0) {
	244	PA1 = !PA1;
	245	ledcounter = 1000;
	246	}
cfeb1a36	247	} else if (gpif_acquiring == STOPPED) {
cf43e09a UH	248	PA1 = 1; /* LED on. */
	249	}
	250	TF2 = 0;
	251	}
	252
1cbff47d	253	void fx2lafw_init(void)
d5f5ea73 UH	254	{
d5f5ea73 UH	255	/* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */
e7434142	256	REVCTL = bmNOAUTOARM \| bmSKIPCOMMIT;
d5f5ea73 UH	257
d5f5ea73 UH	258	got_sud = FALSE;
2846a114	259	vendor_command = 0;
d5f5ea73 UH	260
	261	/* Renumerate. */
	262	RENUMERATE_UNCOND();
	263
	264	SETCPUFREQ(CLK_48M);
	265
	266	USE_USB_INTS();
	267
	268	/* TODO: Does the order of the following lines matter? */
	269	ENABLE_SUDAV();
cfeb1a36	270	ENABLE_EP2IBN();
d5f5ea73 UH	271	ENABLE_HISPEED();
	272	ENABLE_USBRESET();
	273
cf43e09a UH	274	/* PA1 (LED) is an output. */
	275	PORTACFG = 0;
	276	OEA = (1 << 1);
	277	PA1 = 1; /* LED on. */
	278
	279	/* Init timer2. */
	280	RCAP2L = -500 & 0xff;
	281	RCAP2H = (-500 & 0xff00) >> 8;
	282	T2CON = 0;
	283	ET2 = 1;
	284	TR2 = 1;
	285
d5f5ea73 UH	286	/* Global (8051) interrupt enable. */
	287	EA = 1;
	288
	289	/* Setup the endpoints. */
	290	setup_endpoints();
	291
	292	/* Put the FX2 into GPIF master mode and setup the GPIF. */
	293	gpif_init_la();
1cbff47d	294	}
d5f5ea73	295
28d52f41	296	void fx2lafw_poll(void)
1cbff47d JH	297	{
	298	if (got_sud) {
	299	handle_setupdata();
	300	got_sud = FALSE;
d5f5ea73	301	}
2846a114 JH	302
	303	if (vendor_command) {
	304	switch (vendor_command) {
2846a114	305	case CMD_START:
cd29817d	306	if ((EP0CS & bmEPBUSY) != 0)
2846a114 JH	307	break;
2846a114 JH	308
75630581	309	if (EP0BCL == sizeof(struct cmd_start_acquisition)) {
cfeb1a36	310	gpif_acquisition_prepare(
cd29817d	311	(const struct cmd_start_acquisition *)EP0BUF);
2846a114 JH	312	}
	313
	314	/* Acknowledge the vendor command. */
	315	vendor_command = 0;
	316	break;
2846a114 JH	317	default:
	318	/* Unimplemented command. */
	319	vendor_command = 0;
	320	break;
	321	}
	322	}
293d7e9e JH	323
293d7e9e JH	324	gpif_poll();
d5f5ea73	325	}
f7f91781 JH	326
	327	void main(void)
	328	{
	329	fx2lafw_init();
	330	while (1)
	331	fx2lafw_poll();
	332	}