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Commit | Line | Data |
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d5f5ea73 | 1 | /* |
a986cfff | 2 | * This file is part of the sigrok-firmware-fx2lafw project. |
d5f5ea73 UH |
3 | * |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
040a6eae | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
d5f5ea73 UH |
18 | */ |
19 | ||
20 | /* | |
21 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
22 | * | |
23 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
24 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
25 | * | |
26 | * Technical notes: | |
27 | * | |
28 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
29 | * - We use the internal 48MHz clock for GPIF. | |
c7e02d8c UH |
30 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7, |
31 | * or PB0-PB7 + PD0-PD7 for 16-channel sampling. | |
32 | * - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host. | |
d5f5ea73 UH |
33 | * |
34 | * Documentation: | |
35 | * | |
36 | * - See http://sigrok.org/wiki/Fx2lafw | |
37 | */ | |
38 | ||
39 | #include <fx2regs.h> | |
40 | #include <fx2macros.h> | |
41 | #include <delay.h> | |
d5f5ea73 UH |
42 | #include <setupdat.h> |
43 | #include <eputils.h> | |
44 | #include <gpif.h> | |
64d47730 | 45 | #include <command.h> |
8f4a701f | 46 | #include <fx2lafw.h> |
e41576ec | 47 | #include <gpif-acquisition.h> |
d5f5ea73 | 48 | |
d5f5ea73 | 49 | /* ... */ |
8819f75c | 50 | volatile __bit got_sud; |
2846a114 | 51 | BYTE vendor_command; |
d5f5ea73 | 52 | |
d5f5ea73 UH |
53 | static void setup_endpoints(void) |
54 | { | |
d5f5ea73 UH |
55 | /* Setup EP2 (IN). */ |
56 | EP2CFG = (1 << 7) | /* EP is valid/activated */ | |
57 | (1 << 6) | /* EP direction: IN */ | |
58 | (1 << 5) | (0 << 4) | /* EP Type: bulk */ | |
5a95b634 | 59 | (1 << 3) | /* EP buffer size: 1024 */ |
d5f5ea73 UH |
60 | (0 << 2) | /* Reserved. */ |
61 | (0 << 1) | (0 << 0); /* EP buffering: quad buffering */ | |
62 | SYNCDELAY(); | |
63 | ||
576c6627 | 64 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ |
4ad20a4c UH |
65 | EP1INCFG &= ~bmVALID; |
66 | SYNCDELAY(); | |
67 | EP1OUTCFG &= ~bmVALID; | |
68 | SYNCDELAY(); | |
d5f5ea73 UH |
69 | EP4CFG &= ~bmVALID; |
70 | SYNCDELAY(); | |
576c6627 JH |
71 | EP6CFG &= ~bmVALID; |
72 | SYNCDELAY(); | |
d5f5ea73 UH |
73 | EP8CFG &= ~bmVALID; |
74 | SYNCDELAY(); | |
75 | ||
4ad20a4c | 76 | /* EP2: Reset the FIFOs. */ |
d5f5ea73 | 77 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ |
d5f5ea73 | 78 | RESETFIFO(0x02) |
2d62ae47 | 79 | |
dc7ac8bf | 80 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ |
2d62ae47 | 81 | EP2FIFOCFG = bmAUTOIN; |
dc7ac8bf UH |
82 | SYNCDELAY(); |
83 | ||
84 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
85 | EP2AUTOINLENH = 0x02; | |
86 | SYNCDELAY(); | |
87 | EP2AUTOINLENL = 0x00; | |
88 | SYNCDELAY(); | |
89 | ||
4ad20a4c | 90 | /* EP2: Set the GPIF flag to 'full'. */ |
fb0b6d28 | 91 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); |
d5f5ea73 UH |
92 | SYNCDELAY(); |
93 | } | |
94 | ||
18544912 JH |
95 | static void send_fw_version(void) |
96 | { | |
cd29817d UH |
97 | /* Populate the buffer. */ |
98 | struct version_info *const vi = (struct version_info *)EP0BUF; | |
18544912 JH |
99 | vi->major = FX2LAFW_VERSION_MAJOR; |
100 | vi->minor = FX2LAFW_VERSION_MINOR; | |
101 | ||
cd29817d | 102 | /* Send the message. */ |
18544912 JH |
103 | EP0BCH = 0; |
104 | EP0BCL = sizeof(struct version_info); | |
105 | } | |
106 | ||
c23ad602 UH |
107 | static void send_revid_version(void) |
108 | { | |
109 | uint8_t *p; | |
110 | ||
111 | /* Populate the buffer. */ | |
112 | p = (uint8_t *)EP0BUF; | |
113 | *p = REVID; | |
114 | ||
115 | /* Send the message. */ | |
116 | EP0BCH = 0; | |
117 | EP0BCL = 1; | |
118 | } | |
119 | ||
d5f5ea73 UH |
120 | BOOL handle_vendorcommand(BYTE cmd) |
121 | { | |
c7283c28 | 122 | /* Protocol implementation */ |
c7283c28 | 123 | switch (cmd) { |
3b6919fa | 124 | case CMD_START: |
18544912 | 125 | vendor_command = cmd; |
2846a114 | 126 | EP0BCL = 0; |
18544912 | 127 | return TRUE; |
cd29817d | 128 | break; |
2846a114 | 129 | case CMD_GET_FW_VERSION: |
18544912 | 130 | send_fw_version(); |
3b6919fa | 131 | return TRUE; |
cd29817d | 132 | break; |
c23ad602 UH |
133 | case CMD_GET_REVID_VERSION: |
134 | send_revid_version(); | |
135 | return TRUE; | |
136 | break; | |
c7283c28 | 137 | } |
4ad20a4c | 138 | |
d5f5ea73 UH |
139 | return FALSE; |
140 | } | |
141 | ||
142 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
143 | { | |
144 | /* We only support interface 0, alternate interface 0. */ | |
145 | if (ifc != 0) | |
146 | return FALSE; | |
147 | ||
148 | *alt_ifc = 0; | |
149 | return TRUE; | |
150 | } | |
151 | ||
152 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
153 | { | |
154 | /* We only support interface 0, alternate interface 0. */ | |
155 | if (ifc != 0 || alt_ifc != 0) | |
156 | return FALSE; | |
c7e02d8c | 157 | |
d5f5ea73 UH |
158 | /* Perform procedure from TRM, section 2.3.7: */ |
159 | ||
160 | /* (1) TODO. */ | |
161 | ||
162 | /* (2) Reset data toggles of the EPs in the interface. */ | |
163 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
d5f5ea73 UH |
164 | RESETTOGGLE(0x82); |
165 | ||
166 | /* (3) Restore EPs to their default conditions. */ | |
167 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
d5f5ea73 UH |
168 | RESETFIFO(0x02); |
169 | /* TODO */ | |
c430e296 | 170 | |
d5f5ea73 UH |
171 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ |
172 | ||
173 | return TRUE; | |
174 | } | |
175 | ||
176 | BYTE handle_get_configuration(void) | |
177 | { | |
178 | /* We only support configuration 1. */ | |
179 | return 1; | |
180 | } | |
181 | ||
182 | BOOL handle_set_configuration(BYTE cfg) | |
183 | { | |
184 | /* We only support configuration 1. */ | |
185 | return (cfg == 1) ? TRUE : FALSE; | |
186 | } | |
187 | ||
8819f75c | 188 | void sudav_isr(void) __interrupt SUDAV_ISR |
d5f5ea73 UH |
189 | { |
190 | got_sud = TRUE; | |
191 | CLEAR_SUDAV(); | |
192 | } | |
193 | ||
8819f75c | 194 | void sof_isr(void) __interrupt SOF_ISR __using 1 |
d5f5ea73 UH |
195 | { |
196 | CLEAR_SOF(); | |
197 | } | |
198 | ||
8819f75c | 199 | void usbreset_isr(void) __interrupt USBRESET_ISR |
d5f5ea73 UH |
200 | { |
201 | handle_hispeed(FALSE); | |
202 | CLEAR_USBRESET(); | |
203 | } | |
204 | ||
8819f75c | 205 | void hispeed_isr(void) __interrupt HISPEED_ISR |
d5f5ea73 UH |
206 | { |
207 | handle_hispeed(TRUE); | |
208 | CLEAR_HISPEED(); | |
209 | } | |
210 | ||
1cbff47d | 211 | void fx2lafw_init(void) |
d5f5ea73 UH |
212 | { |
213 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
e7434142 | 214 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; |
d5f5ea73 UH |
215 | |
216 | got_sud = FALSE; | |
2846a114 | 217 | vendor_command = 0; |
d5f5ea73 UH |
218 | |
219 | /* Renumerate. */ | |
220 | RENUMERATE_UNCOND(); | |
221 | ||
222 | SETCPUFREQ(CLK_48M); | |
223 | ||
224 | USE_USB_INTS(); | |
225 | ||
226 | /* TODO: Does the order of the following lines matter? */ | |
227 | ENABLE_SUDAV(); | |
228 | ENABLE_SOF(); | |
229 | ENABLE_HISPEED(); | |
230 | ENABLE_USBRESET(); | |
231 | ||
232 | /* Global (8051) interrupt enable. */ | |
233 | EA = 1; | |
234 | ||
235 | /* Setup the endpoints. */ | |
236 | setup_endpoints(); | |
237 | ||
238 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
239 | gpif_init_la(); | |
1cbff47d | 240 | } |
d5f5ea73 | 241 | |
28d52f41 | 242 | void fx2lafw_poll(void) |
1cbff47d JH |
243 | { |
244 | if (got_sud) { | |
245 | handle_setupdata(); | |
246 | got_sud = FALSE; | |
d5f5ea73 | 247 | } |
2846a114 JH |
248 | |
249 | if (vendor_command) { | |
250 | switch (vendor_command) { | |
2846a114 | 251 | case CMD_START: |
cd29817d | 252 | if ((EP0CS & bmEPBUSY) != 0) |
2846a114 JH |
253 | break; |
254 | ||
75630581 | 255 | if (EP0BCL == sizeof(struct cmd_start_acquisition)) { |
2846a114 | 256 | gpif_acquisition_start( |
cd29817d | 257 | (const struct cmd_start_acquisition *)EP0BUF); |
2846a114 JH |
258 | } |
259 | ||
260 | /* Acknowledge the vendor command. */ | |
261 | vendor_command = 0; | |
262 | break; | |
2846a114 JH |
263 | default: |
264 | /* Unimplemented command. */ | |
265 | vendor_command = 0; | |
266 | break; | |
267 | } | |
268 | } | |
293d7e9e JH |
269 | |
270 | gpif_poll(); | |
d5f5ea73 | 271 | } |
f7f91781 JH |
272 | |
273 | void main(void) | |
274 | { | |
275 | fx2lafw_init(); | |
276 | while (1) | |
277 | fx2lafw_poll(); | |
278 | } |