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Commit | Line | Data |
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d5f5ea73 | 1 | /* |
a986cfff | 2 | * This file is part of the sigrok-firmware-fx2lafw project. |
d5f5ea73 UH |
3 | * |
4 | * Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
040a6eae | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
d5f5ea73 UH |
18 | */ |
19 | ||
20 | /* | |
21 | * fx2lafw is an open-source firmware for Cypress FX2 based logic analyzers. | |
22 | * | |
23 | * It is written in C, using fx2lib as helper library, and sdcc as compiler. | |
24 | * The code is licensed under the terms of the GNU GPL, version 2 or later. | |
25 | * | |
26 | * Technical notes: | |
27 | * | |
28 | * - We use the FX2 in GPIF mode to sample the data (asynchronously). | |
29 | * - We use the internal 48MHz clock for GPIF. | |
c7e02d8c UH |
30 | * - The 8 channels/pins we sample (the GPIF data bus) are PB0-PB7, |
31 | * or PB0-PB7 + PD0-PD7 for 16-channel sampling. | |
32 | * - Endpoint 2 (quad-buffered) is used for data transfers from FX2 to host. | |
d5f5ea73 UH |
33 | * |
34 | * Documentation: | |
35 | * | |
36 | * - See http://sigrok.org/wiki/Fx2lafw | |
37 | */ | |
38 | ||
39 | #include <fx2regs.h> | |
40 | #include <fx2macros.h> | |
cf43e09a | 41 | #include <fx2ints.h> |
d5f5ea73 | 42 | #include <delay.h> |
d5f5ea73 UH |
43 | #include <setupdat.h> |
44 | #include <eputils.h> | |
45 | #include <gpif.h> | |
64d47730 | 46 | #include <command.h> |
8f4a701f | 47 | #include <fx2lafw.h> |
e41576ec | 48 | #include <gpif-acquisition.h> |
d5f5ea73 | 49 | |
d5f5ea73 | 50 | /* ... */ |
8819f75c | 51 | volatile __bit got_sud; |
2846a114 | 52 | BYTE vendor_command; |
d5f5ea73 | 53 | |
cf43e09a UH |
54 | volatile WORD ledcounter = 1000; |
55 | ||
56 | extern __bit gpif_acquiring; | |
57 | ||
d5f5ea73 UH |
58 | static void setup_endpoints(void) |
59 | { | |
d5f5ea73 UH |
60 | /* Setup EP2 (IN). */ |
61 | EP2CFG = (1 << 7) | /* EP is valid/activated */ | |
62 | (1 << 6) | /* EP direction: IN */ | |
63 | (1 << 5) | (0 << 4) | /* EP Type: bulk */ | |
5a95b634 | 64 | (1 << 3) | /* EP buffer size: 1024 */ |
d5f5ea73 UH |
65 | (0 << 2) | /* Reserved. */ |
66 | (0 << 1) | (0 << 0); /* EP buffering: quad buffering */ | |
67 | SYNCDELAY(); | |
68 | ||
576c6627 | 69 | /* Disable all other EPs (EP1, EP4, EP6, and EP8). */ |
4ad20a4c UH |
70 | EP1INCFG &= ~bmVALID; |
71 | SYNCDELAY(); | |
72 | EP1OUTCFG &= ~bmVALID; | |
73 | SYNCDELAY(); | |
d5f5ea73 UH |
74 | EP4CFG &= ~bmVALID; |
75 | SYNCDELAY(); | |
576c6627 JH |
76 | EP6CFG &= ~bmVALID; |
77 | SYNCDELAY(); | |
d5f5ea73 UH |
78 | EP8CFG &= ~bmVALID; |
79 | SYNCDELAY(); | |
80 | ||
4ad20a4c | 81 | /* EP2: Reset the FIFOs. */ |
d5f5ea73 | 82 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ |
d5f5ea73 | 83 | RESETFIFO(0x02) |
2d62ae47 | 84 | |
dc7ac8bf | 85 | /* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */ |
2d62ae47 | 86 | EP2FIFOCFG = bmAUTOIN; |
dc7ac8bf UH |
87 | SYNCDELAY(); |
88 | ||
89 | /* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */ | |
90 | EP2AUTOINLENH = 0x02; | |
91 | SYNCDELAY(); | |
92 | EP2AUTOINLENL = 0x00; | |
93 | SYNCDELAY(); | |
94 | ||
4ad20a4c | 95 | /* EP2: Set the GPIF flag to 'full'. */ |
fb0b6d28 | 96 | EP2GPIFFLGSEL = (1 << 1) | (0 << 1); |
d5f5ea73 UH |
97 | SYNCDELAY(); |
98 | } | |
99 | ||
18544912 JH |
100 | static void send_fw_version(void) |
101 | { | |
cd29817d UH |
102 | /* Populate the buffer. */ |
103 | struct version_info *const vi = (struct version_info *)EP0BUF; | |
18544912 JH |
104 | vi->major = FX2LAFW_VERSION_MAJOR; |
105 | vi->minor = FX2LAFW_VERSION_MINOR; | |
106 | ||
cd29817d | 107 | /* Send the message. */ |
18544912 JH |
108 | EP0BCH = 0; |
109 | EP0BCL = sizeof(struct version_info); | |
110 | } | |
111 | ||
c23ad602 UH |
112 | static void send_revid_version(void) |
113 | { | |
114 | uint8_t *p; | |
115 | ||
116 | /* Populate the buffer. */ | |
117 | p = (uint8_t *)EP0BUF; | |
118 | *p = REVID; | |
119 | ||
120 | /* Send the message. */ | |
121 | EP0BCH = 0; | |
122 | EP0BCL = 1; | |
123 | } | |
124 | ||
d5f5ea73 UH |
125 | BOOL handle_vendorcommand(BYTE cmd) |
126 | { | |
c7283c28 | 127 | /* Protocol implementation */ |
c7283c28 | 128 | switch (cmd) { |
3b6919fa | 129 | case CMD_START: |
18544912 | 130 | vendor_command = cmd; |
2846a114 | 131 | EP0BCL = 0; |
18544912 | 132 | return TRUE; |
cd29817d | 133 | break; |
2846a114 | 134 | case CMD_GET_FW_VERSION: |
18544912 | 135 | send_fw_version(); |
3b6919fa | 136 | return TRUE; |
cd29817d | 137 | break; |
c23ad602 UH |
138 | case CMD_GET_REVID_VERSION: |
139 | send_revid_version(); | |
140 | return TRUE; | |
141 | break; | |
c7283c28 | 142 | } |
4ad20a4c | 143 | |
d5f5ea73 UH |
144 | return FALSE; |
145 | } | |
146 | ||
147 | BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc) | |
148 | { | |
149 | /* We only support interface 0, alternate interface 0. */ | |
150 | if (ifc != 0) | |
151 | return FALSE; | |
152 | ||
153 | *alt_ifc = 0; | |
154 | return TRUE; | |
155 | } | |
156 | ||
157 | BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) | |
158 | { | |
159 | /* We only support interface 0, alternate interface 0. */ | |
160 | if (ifc != 0 || alt_ifc != 0) | |
161 | return FALSE; | |
c7e02d8c | 162 | |
d5f5ea73 UH |
163 | /* Perform procedure from TRM, section 2.3.7: */ |
164 | ||
165 | /* (1) TODO. */ | |
166 | ||
167 | /* (2) Reset data toggles of the EPs in the interface. */ | |
168 | /* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */ | |
d5f5ea73 UH |
169 | RESETTOGGLE(0x82); |
170 | ||
171 | /* (3) Restore EPs to their default conditions. */ | |
172 | /* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */ | |
d5f5ea73 UH |
173 | RESETFIFO(0x02); |
174 | /* TODO */ | |
c430e296 | 175 | |
d5f5ea73 UH |
176 | /* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */ |
177 | ||
178 | return TRUE; | |
179 | } | |
180 | ||
181 | BYTE handle_get_configuration(void) | |
182 | { | |
183 | /* We only support configuration 1. */ | |
184 | return 1; | |
185 | } | |
186 | ||
187 | BOOL handle_set_configuration(BYTE cfg) | |
188 | { | |
189 | /* We only support configuration 1. */ | |
190 | return (cfg == 1) ? TRUE : FALSE; | |
191 | } | |
192 | ||
8819f75c | 193 | void sudav_isr(void) __interrupt SUDAV_ISR |
d5f5ea73 UH |
194 | { |
195 | got_sud = TRUE; | |
196 | CLEAR_SUDAV(); | |
197 | } | |
198 | ||
8819f75c | 199 | void sof_isr(void) __interrupt SOF_ISR __using 1 |
d5f5ea73 UH |
200 | { |
201 | CLEAR_SOF(); | |
202 | } | |
203 | ||
8819f75c | 204 | void usbreset_isr(void) __interrupt USBRESET_ISR |
d5f5ea73 UH |
205 | { |
206 | handle_hispeed(FALSE); | |
207 | CLEAR_USBRESET(); | |
208 | } | |
209 | ||
8819f75c | 210 | void hispeed_isr(void) __interrupt HISPEED_ISR |
d5f5ea73 UH |
211 | { |
212 | handle_hispeed(TRUE); | |
213 | CLEAR_HISPEED(); | |
214 | } | |
215 | ||
cf43e09a UH |
216 | void timer2_isr(void) __interrupt TF2_ISR |
217 | { | |
218 | /* Blink LED during acquisition, keep it on otherwise. */ | |
219 | if (gpif_acquiring) { | |
220 | if (--ledcounter == 0) { | |
221 | PA1 = !PA1; | |
222 | ledcounter = 1000; | |
223 | } | |
224 | } else { | |
225 | PA1 = 1; /* LED on. */ | |
226 | } | |
227 | TF2 = 0; | |
228 | } | |
229 | ||
1cbff47d | 230 | void fx2lafw_init(void) |
d5f5ea73 UH |
231 | { |
232 | /* Set DYN_OUT and ENH_PKT bits, as recommended by the TRM. */ | |
e7434142 | 233 | REVCTL = bmNOAUTOARM | bmSKIPCOMMIT; |
d5f5ea73 UH |
234 | |
235 | got_sud = FALSE; | |
2846a114 | 236 | vendor_command = 0; |
d5f5ea73 UH |
237 | |
238 | /* Renumerate. */ | |
239 | RENUMERATE_UNCOND(); | |
240 | ||
241 | SETCPUFREQ(CLK_48M); | |
242 | ||
243 | USE_USB_INTS(); | |
244 | ||
245 | /* TODO: Does the order of the following lines matter? */ | |
246 | ENABLE_SUDAV(); | |
247 | ENABLE_SOF(); | |
248 | ENABLE_HISPEED(); | |
249 | ENABLE_USBRESET(); | |
250 | ||
cf43e09a UH |
251 | /* PA1 (LED) is an output. */ |
252 | PORTACFG = 0; | |
253 | OEA = (1 << 1); | |
254 | PA1 = 1; /* LED on. */ | |
255 | ||
256 | /* Init timer2. */ | |
257 | RCAP2L = -500 & 0xff; | |
258 | RCAP2H = (-500 & 0xff00) >> 8; | |
259 | T2CON = 0; | |
260 | ET2 = 1; | |
261 | TR2 = 1; | |
262 | ||
d5f5ea73 UH |
263 | /* Global (8051) interrupt enable. */ |
264 | EA = 1; | |
265 | ||
266 | /* Setup the endpoints. */ | |
267 | setup_endpoints(); | |
268 | ||
269 | /* Put the FX2 into GPIF master mode and setup the GPIF. */ | |
270 | gpif_init_la(); | |
1cbff47d | 271 | } |
d5f5ea73 | 272 | |
28d52f41 | 273 | void fx2lafw_poll(void) |
1cbff47d JH |
274 | { |
275 | if (got_sud) { | |
276 | handle_setupdata(); | |
277 | got_sud = FALSE; | |
d5f5ea73 | 278 | } |
2846a114 JH |
279 | |
280 | if (vendor_command) { | |
281 | switch (vendor_command) { | |
2846a114 | 282 | case CMD_START: |
cd29817d | 283 | if ((EP0CS & bmEPBUSY) != 0) |
2846a114 JH |
284 | break; |
285 | ||
75630581 | 286 | if (EP0BCL == sizeof(struct cmd_start_acquisition)) { |
2846a114 | 287 | gpif_acquisition_start( |
cd29817d | 288 | (const struct cmd_start_acquisition *)EP0BUF); |
2846a114 JH |
289 | } |
290 | ||
291 | /* Acknowledge the vendor command. */ | |
292 | vendor_command = 0; | |
293 | break; | |
2846a114 JH |
294 | default: |
295 | /* Unimplemented command. */ | |
296 | vendor_command = 0; | |
297 | break; | |
298 | } | |
299 | } | |
293d7e9e JH |
300 | |
301 | gpif_poll(); | |
d5f5ea73 | 302 | } |
f7f91781 JH |
303 | |
304 | void main(void) | |
305 | { | |
306 | fx2lafw_init(); | |
307 | while (1) | |
308 | fx2lafw_poll(); | |
309 | } |