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== Observations of the LA2016 Internal SPI Bus == It contains around 60 registers which are accessed using the SPI bus between the FX2 MCU and the FPGA (see schematic on sigrok wiki page).<b

| I2C, SPI, UART | I2C, SPI, UART

* '''SPI flash''': [http://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flas

#Endpoint 0 to SPI read/write for FPGA control registers #Endpoint 2 bulk out to SPI for loading FPGA bitstream

...og Devices AD5626|Analog Devices AD5626 12-bit nanoDAC.|IC, Analog/digital|spi|&mdash;|supported}} ...Devices AD79x0|Analog Devices AD7910/AD7920 12-bit ADC.|IC, Analog/digital|spi|&mdash;|supported}}

...edge, pulse width, pattern, video, duration, sequence, CAN, USB, LIN, I2C, SPI

-P spi:wordsize=9:miso=1:mosi=5:clk=3:cs=0 In this example, wordsize is an option supported by the spi pro-

This mode is used to set the i2c or spi triggers. * the difference between i2c and spi capture seems to be the TRIGGER_CFG_H bits (see R15 = 0)

...se '''<tt>channels</tt>''' and '''<tt>optional_channels</tt>'''. To decode SPI, the clock signal is always needed, the chip-select signal is optional and id = 'spi'

* Winbond 25Q16 SPI flash (2MiB, probably netlist, maybe UI resources(?), waveforms(?), setting

* PIC32MZ microcontroller, S25F32 SPI flash