Difference between revisions of "Noname XL-LOGIC16-100M"
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The '''XL-LOGIC16-100M''' is a USB-based, 16-channel logic analyzer with up to 100MHz sampling rate. It is labelled and sold as a Saleae Logic16 Clone, and comes with "modified" Saleae Logic software on a cdrom. | The '''XL-LOGIC16-100M''' is a USB-based, 16-channel logic analyzer with up to 100MHz sampling rate. It is labelled and sold as a [[Saleae Logic16]] Clone, and comes with "modified" Saleae Logic software on a cdrom. | ||
The existing Saleae Logic16 support detects this device as an original, but fails to initialize the FPGA for capture. | The existing Saleae Logic16 support detects this device as an original, but fails to initialize the FPGA for capture. | ||
Revision as of 16:32, 29 January 2014
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| Status | planned |
|---|---|
| Channels | 3/6/9/16 |
| Samplerate | 100/50/32/16MHz |
| Samplerate (state) | — |
| Triggers | ? |
| Min/max voltage | ? |
| Threshold voltage | ? |
| Memory | ? |
| Compression | ? |
| Website | aliexpress.com |
The XL-LOGIC16-100M is a USB-based, 16-channel logic analyzer with up to 100MHz sampling rate. It is labelled and sold as a Saleae Logic16 Clone, and comes with "modified" Saleae Logic software on a cdrom. The existing Saleae Logic16 support detects this device as an original, but fails to initialize the FPGA for capture.
See XL-LOGIC16-100M/Info for more details (such as lsusb -v output) about the device.
Hardware
TODO.
Photos
Firmware
Firmware and FPGA bitstream usage
You can use the sigrok-fwextract-saleae-logic16 tool to extract (from the "Logic" Linux binary) the FX2 firmware and the FPGA bitstreams, exactly as for a real Logic 16. Note, the md5sum of the fx2 firmware is identical to the original Saleae firmware, but the fpga bitstreams are different. Attempting to connect to this device with the "modified" fpga bitstream, which _works_ with the vendor supplied "modified" Logic software fails to load in sigrok, with a FPGA version mismatch. The fx2 firmware loads successfully, at least in as much as the LED blinks a heartbeat pattern as expected.
Protocol
Presumably as per Logic16