Difference between revisions of "Logic Shrimp"
Jump to navigation
Jump to search
Uwe Hermann (talk | contribs) m |
Uwe Hermann (talk | contribs) (Use LA Infobox, add hardware info.) |
||
| Line 1: | Line 1: | ||
[[File:logic-shrimp-front.png| | {{Infobox logic analyzer | ||
| image = [[File:logic-shrimp-front.png|180px]] | |||
| name = Logic Shrimp | |||
| status = supported | |||
| source_code_dir = openbench-logic-sniffer | |||
| channels = 4 | |||
| samplerate = 20MHz | |||
| samplerate_state = ? | |||
| triggers = ? | |||
| voltages = ? | |||
| memory = 256ksamples per channel | |||
| compression = ? | |||
| website = [http://dangerousprototypes.com/docs/Logic_Shrimp_logic_analyzer dangerousprototypes.com] | |||
}} | |||
The | The '''Dangerous Prototypes Logic Shrimp''' is a USB-based, 4-channel logic analyzer with up to 20MHz sampling rate. | ||
The design is available under a Creative Commons (CC-BY-SA) license. | The hardware design is available under a Creative Commons (CC-BY-SA) license. | ||
See [[Logic Shrimp/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | See [[Logic Shrimp/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | ||
| Line 9: | Line 22: | ||
== Hardware == | == Hardware == | ||
The device essentially consists of a PIC | * '''8-bit microcontroller with integrated USB Full-Speed support''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en534039 Microchip PIC18F24J50] ([http://ww1.microchip.com/downloads/en/DeviceDoc/39931d.pdf datasheet]) | ||
* 4x '''32kByte SPI-attached SRAM''': [http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en539039 Microchip 23K256I] ([http://ww1.microchip.com/downloads/en/DeviceDoc/22100F.pdf datasheet]) | |||
* '''Octal transparent D-type latches with 3-state output''': [http://www.ti.com/product/sn74lvc573a Texas Instruments SN74LVC573A] ([http://www.ti.com/lit/gpn/sn74lvc573a datasheet]) | |||
* 20MHz crystal | |||
The device essentially consists of a Microchip PIC microcontroller running at 20MHz, sampling each of its 4 probes into its own 256kBit (32kByte) SRAM chip. A buffer chip makes the design 5V tolerant. | |||
== Photos == | == Photos == | ||
| Line 20: | Line 38: | ||
== Protocol == | == Protocol == | ||
The | The Logic Shrimp uses the [http://dangerousprototypes.com/docs/The_Logic_Sniffer%27s_extended_SUMP_protocol extended SUMP protocol], as used by the [[Openbench Logic Sniffer]] driver. It is thus supported in sigrok out of the box. However, the current firmware in the Logic Shrimp does not properly publish metadata according to its capabilities. In order to get valid data from it, make sure to always restrict the probes sampled to 1-4. | ||
== Resources == | == Resources == | ||
* [http://dangerousprototypes.com/docs/Logic_Shrimp_logic_analyzer Logic Shrimp logic analyzer] (main wiki page) | |||
* [http://dangerousprototypes.com/forum/viewforum.php?f=58 Logic Shrimp forum] | |||
[[Category:Device]] | [[Category:Device]] | ||
[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category:Supported]] | [[Category:Supported]] | ||
Revision as of 19:17, 6 April 2013
 | |
| Status | supported |
|---|---|
| Source code | openbench-logic-sniffer |
| Channels | 4 |
| Samplerate | 20MHz |
| Samplerate (state) | ? |
| Triggers | ? |
| Min/max voltage | ? |
| Memory | 256ksamples per channel |
| Compression | ? |
| Website | dangerousprototypes.com |
The Dangerous Prototypes Logic Shrimp is a USB-based, 4-channel logic analyzer with up to 20MHz sampling rate.
The hardware design is available under a Creative Commons (CC-BY-SA) license.
See Logic Shrimp/Info for more details (such as lsusb -vvv output) about the device.
Hardware
- 8-bit microcontroller with integrated USB Full-Speed support: Microchip PIC18F24J50 (datasheet)
- 4x 32kByte SPI-attached SRAM: Microchip 23K256I (datasheet)
- Octal transparent D-type latches with 3-state output: Texas Instruments SN74LVC573A (datasheet)
- 20MHz crystal
The device essentially consists of a Microchip PIC microcontroller running at 20MHz, sampling each of its 4 probes into its own 256kBit (32kByte) SRAM chip. A buffer chip makes the design 5V tolerant.
Photos
PCB, front
PCB, back
Protocol
The Logic Shrimp uses the extended SUMP protocol, as used by the Openbench Logic Sniffer driver. It is thus supported in sigrok out of the box. However, the current firmware in the Logic Shrimp does not properly publish metadata according to its capabilities. In order to get valid data from it, make sure to always restrict the probes sampled to 1-4.
Resources
- Logic Shrimp logic analyzer (main wiki page)
- Logic Shrimp forum