Difference between revisions of "Saleae Logic16"
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[[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]] | [[File:Saleae Logic16.jpg|thumb|right|Saleae Logic16, front]] | ||
The [http://www.saleae.com/logic16/ Saleae Logic16] is a 16-channel, 100/50/25/12.5MHz USB-based logic analyzer (at 2/4/8/16 enabled channels). The case requires a Torx T5 screwdriver to open. | The [http://www.saleae.com/logic16/ Saleae Logic16] is a 16-channel, 100/50/25/12.5MHz USB-based logic analyzer (at 2/4/8/16 enabled channels). | ||
The case requires a Torx T5 screwdriver to open. | |||
See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | See [[Saleae Logic16/Info]] for more details (such as '''lsusb -vvv''' output) about the device. | ||
== | == Hardware == | ||
* [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Xilinx XC3S200A] 200K gate FPGA | * [http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf Xilinx XC3S200A] 200K gate FPGA | ||
* Cypress CY7C68013A-56PVXC USB interface chip | * Cypress CY7C68013A-56PVXC (FX2LP) USB interface chip | ||
== Photos == | |||
<gallery> | |||
File:Saleae Logic16.jpg|<small>Device, front</small> | |||
File:Saleae Logic16 bottom.jpg|<small>Device, bottom</small> | |||
File:Saleae Logic16 PCB top.jpg|<small>PCB, top</small> | |||
File:Saleae Logic16 PCB bottom.jpg|<small>PCB, bottom</small> | |||
</gallery> | |||
== Protocol == | == Protocol == | ||
TODO. | TODO. | ||
== Resources == | |||
* [http://downloads.saleae.com/Logic+Guide.pdf Manual] | |||
* [http://www.saleae.com/downloads Vendor software] | |||
[[Category:Device]] | [[Category:Device]] | ||
[[Category:Logic analyzer]] | [[Category:Logic analyzer]] | ||
[[Category:Planned]] | [[Category:Planned]] | ||
Revision as of 02:13, 1 January 2013
The Saleae Logic16 is a 16-channel, 100/50/25/12.5MHz USB-based logic analyzer (at 2/4/8/16 enabled channels).
The case requires a Torx T5 screwdriver to open.
See Saleae Logic16/Info for more details (such as lsusb -vvv output) about the device.
Hardware
- Xilinx XC3S200A 200K gate FPGA
- Cypress CY7C68013A-56PVXC (FX2LP) USB interface chip
Photos
Device, front
Device, bottom
PCB, top
PCB, bottom
Protocol
TODO.