Difference between revisions of "Protocol decoder:Z80"
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| probes = D0–D7, /M1, /RD, /WR | | probes = D0–D7, /M1, /RD, /WR | ||
| optional_probes = /MREQ, /IORQ, A0–A15 | | optional_probes = /MREQ, /IORQ, A0–A15 | ||
| options = — | |||
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== Resources == | == Resources == | ||
* [https://en.wikipedia.org/wiki/Zilog_Z80 Wikipedia: Zilog Z80] | |||
[[Category:Protocol decoder]] | [[Category:Protocol decoder]] | ||
Latest revision as of 00:14, 3 April 2015
 | |
| Name | Z80 |
|---|---|
| Description | Zilog Z80 microprocessor disassembly |
| Status | supported |
| License | GPLv3+ |
| Source code | decoders/z80 |
| Input | logic |
| Output | z80 |
| Probes | D0–D7, /M1, /RD, /WR |
| Optional probes | /MREQ, /IORQ, A0–A15 |
| Options | — |
The z80 protocol decoder disassembles the instruction stream of a Zilog Z80 microprocessor.
Hardware
KC 85/4
The z80/kc85 directory in sigrok-dumps contains a set of example bus captures of the Z80-based KC 85/4 computer.
The logic analyzer used was a Sysclk LWLA1034.
Protocol
The data bus lines plus the control signals /M1, /RD and /WR are sufficient to display full disassembly. Optionally, the address bus lines and the control signals /MREQ and /IORQ may also be provided.