|Zilog Z80 microprocessor disassembly
|D0–D7, /M1, /RD, /WR
|/MREQ, /IORQ, A0–A15
The z80 protocol decoder disassembles the instruction stream of a Zilog Z80 microprocessor.
The logic analyzer used was a Sysclk LWLA1034.
The data bus lines plus the control signals /M1, /RD and /WR are sufficient to display full disassembly. Optionally, the address bus lines and the control signals /MREQ and /IORQ may also be provided.