uart: Add a test-case for overlapping RX/TX bytes.

[sigrok-test.git] / decoder / test / uart / test.conf

diff --git a/decoder/test/uart/test.conf b/decoder/test/uart/test.conf
index 2d54f336838a3ee272404a524384f32d788cfe97..f501edb3af663a22c1c557d4e92e4fb5ee7cbc01 100644 (file)
--- a/decoder/test/uart/test.conf
+++ b/decoder/test/uart/test.conf
@@ -114,6 +114,14 @@ test hello_world_8o1_115200
        output uart python match hello_world_8o1_115200.python
        output uart binary class tx match hello_world_8o1_115200.bin_tx
 
+test rxtx_overlapped
+       protocol-decoder uart channel rx=3 channel tx=4
+       input uart/rxtx_overlapped/rxtx_overlapped.sr
+       output uart annotation match rxtx_overlapped.output
+       output uart python match rxtx_overlapped.python
+       output uart binary class rx match rxtx_overlapped.bin_rx
+       output uart binary class tx match rxtx_overlapped.bin_tx
+
 test exception_samplerate
        protocol-decoder uart
        input misc/no-samplerate.sr